Lines Matching +full:0 +full:x80040000
52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
53 #define CONFIG_SYS_MEMTEST_END 0x00400000
58 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
63 #define CONFIG_SYS_CCSRBAR 0xe0000000
75 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
85 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
89 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
91 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
92 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
93 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
94 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0
95 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
96 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
97 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
98 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
99 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
100 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
101 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
102 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
103 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
104 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
105 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
106 #define CONFIG_SYS_DDR_CDR_1 0x80040000
107 #define CONFIG_SYS_DDR_CDR_2 0x00000000
108 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
109 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
110 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
111 #define CONFIG_SYS_DDR_CONTROL2 0x24400000
113 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
114 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
115 #define CONFIG_SYS_DDR_SBE 0x00010000
123 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
126 #define CONFIG_SYS_BCSR_BASE 0xf8000000
129 /*Chip select 0 - Flash*/
130 #define CONFIG_FLASH_BR_PRELIM 0xfe000801
131 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
134 #define CONFIG_SYS_BR1_PRELIM 0xf8000801
135 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
138 #define CONFIG_SYS_BR4_PRELIM 0xf8008801
139 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
142 #define CONFIG_SYS_BR5_PRELIM 0xf8010801
143 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
157 #define CONFIG_SYS_NAND_BASE 0xFC000000
159 #define CONFIG_SYS_NAND_BASE 0xFFF00000
163 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
164 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
168 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
169 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
170 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
182 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
195 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
196 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
197 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
198 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
201 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
202 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
214 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
223 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
231 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
233 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
234 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
235 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
236 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
245 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
249 #define PLPPAR1_I2C_BIT_MASK 0x0000000F
250 #define PLPPAR1_I2C2_VAL 0x00000000
251 #define PLPPAR1_ESDHC_VAL 0x0000000A
252 #define PLPDIR1_I2C_BIT_MASK 0x0000000F
253 #define PLPDIR1_I2C2_VAL 0x0000000F
254 #define PLPDIR1_ESDHC_VAL 0x00000006
255 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0
256 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
257 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0
258 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
262 * Memory Addresses are mapped 1-1. I/O is mapped from 0
265 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
266 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
267 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
268 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
269 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
270 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
271 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
272 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
274 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
275 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
277 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
286 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
295 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
306 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
327 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
348 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
369 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
417 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
418 #define CONFIG_ENV_SIZE 0x2000
426 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000
443 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
479 "netdev=eth0\0" \
480 "consoledev=ttyS0\0" \
481 "ramdiskaddr=600000\0" \
482 "ramdiskfile=your.ramdisk.u-boot\0" \
483 "fdtaddr=400000\0" \
484 "fdtfile=your.fdt.dtb\0" \
488 "console=$consoledev,$baudrate $othbootargs\0" \
490 "console=$consoledev,$baudrate $othbootargs\0" \