1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2f3a8e2b7SMingkai Hu /* 3f3a8e2b7SMingkai Hu * Copyright 2015 Freescale Semiconductor, Inc. 4f3a8e2b7SMingkai Hu */ 5f3a8e2b7SMingkai Hu 6f3a8e2b7SMingkai Hu #ifndef __DDR_H__ 7f3a8e2b7SMingkai Hu #define __DDR_H__ 8074596c0SShengzhou Liu 9074596c0SShengzhou Liu extern void erratum_a008850_post(void); 10074596c0SShengzhou Liu 11f3a8e2b7SMingkai Hu struct board_specific_parameters { 12f3a8e2b7SMingkai Hu u32 n_ranks; 13f3a8e2b7SMingkai Hu u32 datarate_mhz_high; 14f3a8e2b7SMingkai Hu u32 rank_gb; 15f3a8e2b7SMingkai Hu u32 clk_adjust; 16f3a8e2b7SMingkai Hu u32 wrlvl_start; 17f3a8e2b7SMingkai Hu u32 wrlvl_ctl_2; 18f3a8e2b7SMingkai Hu u32 wrlvl_ctl_3; 19f3a8e2b7SMingkai Hu u32 cpo_override; 20f3a8e2b7SMingkai Hu u32 write_data_delay; 21f3a8e2b7SMingkai Hu u32 force_2t; 22f3a8e2b7SMingkai Hu }; 23f3a8e2b7SMingkai Hu 24f3a8e2b7SMingkai Hu /* 25f3a8e2b7SMingkai Hu * These tables contain all valid speeds we want to override with board 26f3a8e2b7SMingkai Hu * specific parameters. datarate_mhz_high values need to be in ascending order 27f3a8e2b7SMingkai Hu * for each n_ranks group. 28f3a8e2b7SMingkai Hu */ 29f3a8e2b7SMingkai Hu static const struct board_specific_parameters udimm0[] = { 30f3a8e2b7SMingkai Hu /* 31f3a8e2b7SMingkai Hu * memory controller 0 32f3a8e2b7SMingkai Hu * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 33f3a8e2b7SMingkai Hu * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 34f3a8e2b7SMingkai Hu */ 35f3a8e2b7SMingkai Hu #ifdef CONFIG_SYS_FSL_DDR4 36e04f9d0cSShengzhou Liu {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,}, 37e04f9d0cSShengzhou Liu {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,}, 38e04f9d0cSShengzhou Liu {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,}, 39f3a8e2b7SMingkai Hu #endif 40f3a8e2b7SMingkai Hu {} 41f3a8e2b7SMingkai Hu }; 42f3a8e2b7SMingkai Hu 43f3a8e2b7SMingkai Hu static const struct board_specific_parameters *udimms[] = { 44f3a8e2b7SMingkai Hu udimm0, 45f3a8e2b7SMingkai Hu }; 46f3a8e2b7SMingkai Hu 47f554411bSYork Sun #ifndef CONFIG_SYS_DDR_RAW_TIMING 48f554411bSYork Sun fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = { 49f554411bSYork Sun .cs[0].bnds = 0x0000007F, 50f554411bSYork Sun .cs[1].bnds = 0, 51f554411bSYork Sun .cs[2].bnds = 0, 52f554411bSYork Sun .cs[3].bnds = 0, 53f554411bSYork Sun .cs[0].config = 0x80040322, 54f554411bSYork Sun .cs[0].config_2 = 0, 55f554411bSYork Sun .cs[1].config = 0, 56f554411bSYork Sun .cs[1].config_2 = 0, 57f554411bSYork Sun .cs[2].config = 0, 58f554411bSYork Sun .cs[3].config = 0, 59f554411bSYork Sun .timing_cfg_3 = 0x010C1000, 60f554411bSYork Sun .timing_cfg_0 = 0x91550018, 61f554411bSYork Sun .timing_cfg_1 = 0xBBB48C42, 62f554411bSYork Sun .timing_cfg_2 = 0x0048C111, 63f554411bSYork Sun .ddr_sdram_cfg = 0xC50C0008, 64f554411bSYork Sun .ddr_sdram_cfg_2 = 0x00401100, 65f554411bSYork Sun .ddr_sdram_cfg_3 = 0, 66f554411bSYork Sun .ddr_sdram_mode = 0x03010210, 67f554411bSYork Sun .ddr_sdram_mode_2 = 0, 68f554411bSYork Sun .ddr_sdram_mode_3 = 0x00010210, 69f554411bSYork Sun .ddr_sdram_mode_4 = 0, 70f554411bSYork Sun .ddr_sdram_mode_5 = 0x00010210, 71f554411bSYork Sun .ddr_sdram_mode_6 = 0, 72f554411bSYork Sun .ddr_sdram_mode_7 = 0x00010210, 73f554411bSYork Sun .ddr_sdram_mode_8 = 0, 74f554411bSYork Sun .ddr_sdram_mode_9 = 0x00000500, 75f554411bSYork Sun .ddr_sdram_mode_10 = 0x04000000, 76f554411bSYork Sun .ddr_sdram_mode_11 = 0x00000400, 77f554411bSYork Sun .ddr_sdram_mode_12 = 0x04000000, 78f554411bSYork Sun .ddr_sdram_mode_13 = 0x00000400, 79f554411bSYork Sun .ddr_sdram_mode_14 = 0x04000000, 80f554411bSYork Sun .ddr_sdram_mode_15 = 0x00000400, 81f554411bSYork Sun .ddr_sdram_mode_16 = 0x04000000, 82f554411bSYork Sun .ddr_sdram_interval = 0x18600618, 83f554411bSYork Sun .ddr_data_init = 0xDEADBEEF, 84f554411bSYork Sun .ddr_sdram_clk_cntl = 0x03000000, 85f554411bSYork Sun .ddr_init_addr = 0, 86f554411bSYork Sun .ddr_init_ext_addr = 0, 87f554411bSYork Sun .timing_cfg_4 = 0x00000002, 88f554411bSYork Sun .timing_cfg_5 = 0x03401400, 89f554411bSYork Sun .timing_cfg_6 = 0, 90f554411bSYork Sun .timing_cfg_7 = 0x13300000, 91f554411bSYork Sun .timing_cfg_8 = 0x02115600, 92f554411bSYork Sun .timing_cfg_9 = 0, 93f554411bSYork Sun .ddr_zq_cntl = 0x8A090705, 94f554411bSYork Sun .ddr_wrlvl_cntl = 0x8675F607, 95f554411bSYork Sun .ddr_wrlvl_cntl_2 = 0x07090800, 96f554411bSYork Sun .ddr_wrlvl_cntl_3 = 0, 97f554411bSYork Sun .ddr_sr_cntr = 0, 98f554411bSYork Sun .ddr_sdram_rcw_1 = 0, 99f554411bSYork Sun .ddr_sdram_rcw_2 = 0, 100f554411bSYork Sun .ddr_cdr1 = 0x80040000, 101f554411bSYork Sun .ddr_cdr2 = 0x0000A181, 102f554411bSYork Sun .dq_map_0 = 0, 103f554411bSYork Sun .dq_map_1 = 0, 104f554411bSYork Sun .dq_map_2 = 0, 105f554411bSYork Sun .dq_map_3 = 0, 106f554411bSYork Sun .debug[28] = 0x00700046, 107f554411bSYork Sun 108f554411bSYork Sun }; 109f554411bSYork Sun 110f554411bSYork Sun fixed_ddr_parm_t fixed_ddr_parm_0[] = { 111f554411bSYork Sun {1550, 1650, &ddr_cfg_regs_1600}, 112f554411bSYork Sun {0, 0, NULL} 113f554411bSYork Sun }; 114f554411bSYork Sun 115f554411bSYork Sun #endif 116f3a8e2b7SMingkai Hu #endif 117