Lines Matching +full:0 +full:x80040000

16 	move.w	#0x2700,%sr;		/* disable intrs */	\
40 INITSP:	.long	0			/* Initial SP	*/
43 INITSP:	.long	0			/* Initial SP	*/
59 /* TRAP #0 - #15 */
103 	.long	0x00000000		/* checksum, not yet implemented */
104 	.long	0x00020000		/* image length */
115 	move.l	#0xFC008000, %a1
117 	move.l	#0xFC008008, %a1
119 	move.l	#0xFC008004, %a1
126 	move.l	#0xFC0A4074, %a1
130 	/* SDRAM Chip 0 and 1 */
131 	move.l	#0xFC0B8110, %a1
132 	move.l	#0xFC0B8114, %a2
135 	move.l	#0x13, %d1
147 	/* SDRAM Chip 0 and 1 */
157 	move.l	#0xFC0B8008, %a1
160 	move.l	#0xFC0B800C, %a2
164 	move.l	#0xFC0B8000, %a1	/* Mode */
165 	move.l	#0xFC0B8004, %a2	/* Ctrl */
195 	and.l	#0x7FFFFFFF, %d0
196 	or.l	#0x10000c00, %d0
202 	 * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
210 	move.l	#0xFC0A4036, %a0
211 	move.b	#0x3F, %d0
217 	or.l	#0xC0, %d0
221 	move.l	#0xFC0A4037, %a0
223 	or.l	#0x10, %d0
229 	move.l	#0xFC05C000, %a0
230 	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
232 	move.l	#0xFC05C00C, %a0
233 	move.l	#0x3E000011, (%a0)
235 	move.l	#0xFC05C034, %a2	/* dtfr */
236 	move.l	#0xFC05C03B, %a3	/* drfr */
245 	move.l	#0xFC05C02C, %a1	/* dspi status */
248 	move.l	#0x8004000B, %d2	/* Fast Read Cmd */
252 	move.l	#0x80040000, %d2	/* Address byte 2 */
256 	move.l	#0x80040000, %d2	/* Address byte 1 */
260 	move.l	#0x80040000, %d2	/* Address byte 0 */
264 	move.l	#0x80040000, %d2	/* Dummy Wr and Rd */
270 	move.l	#0x80040000, %d2
282 	move.l	#0x80040000, %d2
292 	move.l	#0x00040000, %d2	/* Terminate */
297 	move.l	#(CONFIG_SYS_TEXT_BASE + 0x400), %a0
303 	and.l	#0x0000F000, %d0
304 	cmp.l	#0x00003000, %d0
312 	and.l	#0x000000F0, %d0
314 	cmp.l	#0, %d0
322 	. = 0x400
327 	move.w	#0x2700,%sr		/* Mask off Interrupt */
344 	move.l	#0, %d0
349 	move.l	#0, %d0
400 	link.w	%a6,#0
493 .ascii U_BOOT_VERSION_STRING, "\0"