Lines Matching +full:0 +full:x80040000
29 #define DDR_SDRAM_CFG 0x470c0008
30 #define DDR_CS0_BNDS 0x008000bf
31 #define DDR_CS0_CONFIG 0x80014302
32 #define DDR_TIMING_CFG_0 0x50550004
33 #define DDR_TIMING_CFG_1 0xbcb38c56
34 #define DDR_TIMING_CFG_2 0x0040d120
35 #define DDR_TIMING_CFG_3 0x010e1000
36 #define DDR_TIMING_CFG_4 0x00000001
37 #define DDR_TIMING_CFG_5 0x03401400
38 #define DDR_SDRAM_CFG_2 0x00401010
39 #define DDR_SDRAM_MODE 0x00061c60
40 #define DDR_SDRAM_MODE_2 0x00180000
41 #define DDR_SDRAM_INTERVAL 0x18600618
42 #define DDR_DDR_WRLVL_CNTL 0x8655f605
43 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
44 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
45 #define DDR_DDR_CDR1 0x80040000
46 #define DDR_DDR_CDR2 0x00000001
47 #define DDR_SDRAM_CLK_CNTL 0x02000000
48 #define DDR_DDR_ZQ_CNTL 0x89080600
49 #define DDR_CS0_CONFIG_2 0
50 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
51 #define SDRAM_CFG2_D_INIT 0x00000010
52 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
53 #define SDRAM_CFG2_FRC_SR 0x80000000
54 #define SDRAM_CFG_BI 0x00000001
77 #define CONFIG_SPL_TEXT_BASE 0x10000000
78 #define CONFIG_SPL_MAX_SIZE 0x1a000
79 #define CONFIG_SPL_STACK 0x1001d000
80 #define CONFIG_SPL_PAD_TO 0x1c000
84 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
85 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
86 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
95 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
97 #define CONFIG_SYS_MONITOR_LEN 0x100000
101 #define PHYS_SDRAM 0x80000000
104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
119 #define CONFIG_SYS_FLASH_BASE 0x60000000
122 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
132 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
133 FTIM0_NOR_TEADC(0x5) | \
134 FTIM0_NOR_TAVDS(0x0) | \
135 FTIM0_NOR_TEAHC(0x5))
136 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
137 FTIM1_NOR_TRAD_NOR(0x1A) | \
138 FTIM1_NOR_TSEQRAD_NOR(0x13))
139 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
140 FTIM2_NOR_TCH(0x4) | \
141 FTIM2_NOR_TWP(0x1c) | \
142 FTIM2_NOR_TWPH(0x0e))
143 #define CONFIG_SYS_NOR_FTIM3 0
162 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
165 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
176 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
177 FTIM0_GPCM_TEADC(0xf) | \
178 FTIM0_GPCM_TEAHC(0xf))
179 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
180 FTIM1_GPCM_TRAD(0x3f))
181 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
182 FTIM2_GPCM_TCH(0xf) | \
183 FTIM2_GPCM_TWP(0xff))
184 #define CONFIG_SYS_FPGA_FTIM3 0x0
228 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
240 #define QSPI0_AMBA_BASE 0x40000000
261 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
278 #define TSEC2_PHY_ADDR 0
285 #define TSEC1_PHYIDX 0
286 #define TSEC2_PHYIDX 0
287 #define TSEC3_PHYIDX 0
310 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
319 func(MMC, mmc, 0) \
320 func(USB, usb, 0) \
326 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
327 "initrd_high=0xffffffff\0" \
328 "fdt_high=0xffffffff\0" \
329 "fdt_addr=0x64f00000\0" \
330 "kernel_addr=0x65000000\0" \
331 "scriptaddr=0x80000000\0" \
332 "scripthdraddr=0x80080000\0" \
333 "fdtheader_addr_r=0x80100000\0" \
334 "kernelheader_addr_r=0x80200000\0" \
335 "kernel_addr_r=0x81000000\0" \
336 "fdt_addr_r=0x90000000\0" \
337 "ramdisk_addr_r=0xa0000000\0" \
338 "load_addr=0xa0000000\0" \
339 "kernel_size=0x2800000\0" \
340 "kernel_addr_sd=0x8000\0" \
341 "kernel_size_sd=0x14000\0" \
343 "boot_scripts=ls1021atwr_boot.scr\0" \
344 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
354 "done\0" \
361 "\0" \
369 "source ${scriptaddr}\0" \
370 "installer=load mmc 0:2 $load_addr " \
372 "bootm $load_addr#ls1021atwr\0" \
375 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
378 "$kernel_size && bootm $load_addr#$board\0"
381 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
382 "initrd_high=0xffffffff\0" \
383 "fdt_high=0xffffffff\0" \
384 "fdt_addr=0x64f00000\0" \
385 "kernel_addr=0x61000000\0" \
386 "kernelheader_addr=0x60800000\0" \
387 "scriptaddr=0x80000000\0" \
388 "scripthdraddr=0x80080000\0" \
389 "fdtheader_addr_r=0x80100000\0" \
390 "kernelheader_addr_r=0x80200000\0" \
391 "kernel_addr_r=0x81000000\0" \
392 "kernelheader_size=0x40000\0" \
393 "fdt_addr_r=0x90000000\0" \
394 "ramdisk_addr_r=0xa0000000\0" \
395 "load_addr=0xa0000000\0" \
396 "kernel_size=0x2800000\0" \
397 "kernel_addr_sd=0x8000\0" \
398 "kernel_size_sd=0x14000\0" \
399 "kernelhdr_addr_sd=0x4000\0" \
400 "kernelhdr_size_sd=0x10\0" \
402 "boot_scripts=ls1021atwr_boot.scr\0" \
403 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
413 "done\0" \
420 "\0" \
428 "source ${scriptaddr}\0" \
434 "bootm $load_addr#$board\0" \
440 "bootm $load_addr#$board\0" \
447 "bootm $load_addr#$board\0"
466 #define CONFIG_SYS_MEMTEST_START 0x80000000
467 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
469 #define CONFIG_SYS_LOAD_ADDR 0x82000000
484 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
492 #define CONFIG_ENV_OFFSET 0x300000
493 #define CONFIG_SYS_MMC_ENV_DEV 0
494 #define CONFIG_ENV_SIZE 0x20000
496 #define CONFIG_ENV_SIZE 0x2000
497 #define CONFIG_ENV_OFFSET 0x300000
498 #define CONFIG_ENV_SECT_SIZE 0x10000
500 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
501 #define CONFIG_ENV_SIZE 0x20000
502 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */