Home
last modified time | relevance | path

Searched +full:0 +full:x5f800000 (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-soc-glue.yaml78 reg = <0x5f800000 0x2000>;
87 #size-cells = <0>;
89 phy@0 {
90 reg = <0>;
91 #phy-cells = <0>;
96 #phy-cells = <0>;
101 #phy-cells = <0>;
106 #phy-cells = <0>;
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dsg-regs.h14 #define SG_CTRL_BASE 0x5f800000
15 #define SG_DBG_BASE 0x5f900000
18 #define SG_REVISION (SG_CTRL_BASE | 0x0000)
21 #define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
23 #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
24 #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
25 #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
26 #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
27 #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
28 #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
[all …]
/openbmc/u-boot/board/armltd/vexpress64/
H A Dpcie.c16 #define XR3_CONFIG_BASE 0x7ff30000
17 #define XR3_RESET_BASE 0x7ff20000
19 #define XR3_PCI_ECAM_START 0x40000000
20 #define XR3_PCI_ECAM_SIZE 28 /* as power of 2 = 0x10000000 */
21 #define XR3_PCI_IOSPACE_START 0x5f800000
22 #define XR3_PCI_IOSPACE_SIZE 23 /* as power of 2 = 0x800000 */
23 #define XR3_PCI_MEMSPACE_START 0x50000000
24 #define XR3_PCI_MEMSPACE_SIZE 27 /* as power of 2 = 0x8000000 */
25 #define XR3_PCI_MEMSPACE64_START 0x4000000000
26 #define XR3_PCI_MEMSPACE64_SIZE 33 /* as power of 2 = 0x200000000 */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Duniphier-sld8.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
[all …]
H A Duniphier-ld4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
[all …]
H A Duniphier-pro5.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
116 #clock-cells = <0>;
121 #clock-cells = <0>;
136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
137 <0x506c0000 0x400>;
138 interrupts = <0 190 4>, <0 191 4>;
149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
150 <0x506c8000 0x400>;
[all …]
H A Duniphier-ld11.dtsi11 /memreserve/ 0x80000000 0x02000000;
21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0 0x000>;
46 reg = <0 0x001>;
95 #clock-cells = <0>;
113 soc@0 {
117 ranges = <0 0 0 0xffffffff>;
122 reg = <0x54006000 0x100>;
123 interrupts = <0 39 4>;
[all …]
H A Duniphier-pro4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
77 reg = <0x54006000 0x100>;
78 interrupts = <0 39 4>;
[all …]
H A Duniphier-pxs3.dtsi11 /memreserve/ 0x80000000 0x02000000;
21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
52 reg = <0 0x001>;
61 reg = <0 0x002>;
70 reg = <0 0x003>;
123 #clock-cells = <0>;
141 soc@0 {
145 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-pxs2.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
160 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
161 <0x506c0000 0x400>;
162 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
173 reg = <0x54006000 0x100>;
174 interrupts = <0 39 4>;
[all …]
H A Duniphier-ld20.dtsi12 /memreserve/ 0x80000000 0x02000000;
22 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0 0x000>;
57 reg = <0 0x001>;
67 reg = <0 0x100>;
77 reg = <0 0x101>;
169 #clock-cells = <0>;
221 soc@0 {
225 ranges = <0 0 0 0xffffffff>;
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Duniphier-ld4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-sld8.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro5.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
123 #clock-cells = <0>;
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
139 <0x506c0000 0x400>;
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
166 reg = <0x54006000 0x100>;
[all …]
H A Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi20 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0 0x000>;
46 reg = <0 0x001>;
100 #clock-cells = <0>;
124 reg = <0x0 0x81000000 0x0 0x01000000>;
129 soc@0 {
133 ranges = <0 0 0 0xffffffff>;
138 reg = <0x54006000 0x100>;
140 #size-cells = <0>;
[all …]
H A Duniphier-pxs3.dtsi21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
54 reg = <0 0x001>;
65 reg = <0 0x002>;
76 reg = <0 0x003>;
135 #clock-cells = <0>;
190 reg = <0x0 0x81000000 0x0 0x01000000>;
195 soc@0 {
199 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-ld20.dtsi21 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0 0x000>;
57 reg = <0 0x001>;
68 reg = <0 0x100>;
79 reg = <0 0x101>;
96 cluster0_opp: opp-table-0 {
180 #clock-cells = <0>;
235 reg = <0x0 0x81000000 0x0 0x01000000>;
240 soc@0 {
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
16 ranges = <0 0x0 0x2a820000 0x20000>;
21 reg = <0x10000 0x10000>;
27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
38 reg = <0x0 0x2b400000 0x0 0x10000>;
50 reg = <0x0 0x2b500000 0x0 0x10000>;
61 reg = <0x0 0x2b600000 0x0 0x10000>;
67 power-domains = <&scpi_devpd 0>;
72 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125.dtsi23 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
[all …]