armltd/vexpress64/pcie.c

16 #define XR3_CONFIG_BASE			0x7ff30000
17 #define XR3_RESET_BASE			0x7ff20000
19 #define XR3_PCI_ECAM_START		0x40000000
20 #define XR3_PCI_ECAM_SIZE		28	/* as power of 2 = 0x10000000 */
21 #define XR3_PCI_IOSPACE_START		0x5f800000
22 #define XR3_PCI_IOSPACE_SIZE		23	/* as power of 2 = 0x800000 */
23 #define XR3_PCI_MEMSPACE_START		0x50000000
24 #define XR3_PCI_MEMSPACE_SIZE		27	/* as power of 2 = 0x8000000 */
25 #define XR3_PCI_MEMSPACE64_START	0x4000000000
26 #define XR3_PCI_MEMSPACE64_SIZE		33	/* as power of 2 = 0x200000000 */
28 #define JUNO_V2M_MSI_START		0x2c1c0000
31 #define XR3PCI_BASIC_STATUS		0x18
32 #define XR3PCI_BS_GEN_MASK		(0xf << 8)
33 #define XR3PCI_BS_LINK_MASK		0xff
35 #define XR3PCI_VIRTCHAN_CREDITS		0x90
36 #define XR3PCI_BRIDGE_PCI_IDS		0x9c
37 #define XR3PCI_PEX_SPC2			0xd8
39 #define XR3PCI_ATR_PCIE_WIN0		0x600
40 #define XR3PCI_ATR_PCIE_WIN1		0x700
41 #define XR3PCI_ATR_AXI4_SLV0		0x800
43 #define XR3PCI_ATR_TABLE_SIZE		0x20
44 #define XR3PCI_ATR_SRC_ADDR_LOW		0x0
45 #define XR3PCI_ATR_SRC_ADDR_HIGH	0x4
46 #define XR3PCI_ATR_TRSL_ADDR_LOW	0x8
47 #define XR3PCI_ATR_TRSL_ADDR_HIGH	0xc
48 #define XR3PCI_ATR_TRSL_PARAM		0x10
51 #define XR3PCI_ATR_TRSLID_AXIDEVICE	(0x420004)
52 #define XR3PCI_ATR_TRSLID_AXIMEMORY	(0x4e0004)  /* Write-through, read/write allocate */
53 #define XR3PCI_ATR_TRSLID_PCIE_CONF	(0x000001)
54 #define XR3PCI_ATR_TRSLID_PCIE_IO	(0x020000)
55 #define XR3PCI_ATR_TRSLID_PCIE_MEMORY	(0x000000)
61 #define JUNO_RESET_CTRL			0x1004
62 #define JUNO_RESET_CTRL_PHY		BIT(0)
65 #define JUNO_RESET_STATUS		0x1008
66 #define JUNO_RESET_STATUS_PLL		BIT(0)
78 	     - bit 0: enable entry,  in xr3pci_set_atr_entry()
83 	writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,  in xr3pci_set_atr_entry()
86 	writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);  in xr3pci_set_atr_entry()
90 	debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",  in xr3pci_set_atr_entry()
91 	       src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,  in xr3pci_set_atr_entry()
120 	xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,  in xr3pci_setup_atr()
126 	xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,  in xr3pci_setup_atr()
150 	writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);  in xr3pci_init()
151 	writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);  in xr3pci_init()
153 	writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);  in xr3pci_init()