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12

/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt75 reg = <0x4C000000 0x1000>;
82 reg = <0x4c000000 0x200>;
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra74x-p.dtsi17 reg = <0x4c000000 0x200>;
H A Dam33xx.dtsi47 #size-cells = <0>;
48 cpu@0 {
52 reg = <0>;
87 opp-supported-hw = <0x06 0x0010>;
95 opp-supported-hw = <0x01 0x00FF>;
103 opp-supported-hw = <0x06 0x0020>;
111 opp-supported-hw = <0x01 0xFFFF>;
118 opp-supported-hw = <0x06 0x0040>;
125 opp-supported-hw = <0x01 0xFFFF>;
132 opp-supported-hw = <0x06 0x0080>;
[all …]
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Dam4372.dtsi20 memory@0 {
22 reg = <0 0>;
42 #size-cells = <0>;
43 cpu: cpu@0 {
47 reg = <0>;
77 opp-supported-hw = <0xFF 0x01>;
85 opp-supported-hw = <0xFF 0x04>;
92 opp-supported-hw = <0xFF 0x08>;
99 opp-supported-hw = <0xFF 0x10>;
106 opp-supported-hw = <0xFF 0x20>;
[all …]
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
/openbmc/u-boot/include/configs/
H A Dpxa-common.h39 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4c000000
H A Dvexpress_common.h20 #define V2M_PA_CS0 0x40000000
21 #define V2M_PA_CS1 0x44000000
22 #define V2M_PA_CS2 0x48000000
23 #define V2M_PA_CS3 0x4c000000
24 #define V2M_PA_CS7 0x10000000
27 #define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
31 #define V2M_BASE 0x60000000
34 #define V2M_PA_CS0 0x08000000
35 #define V2M_PA_CS1 0x0c000000
36 #define V2M_PA_CS2 0x14000000
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp4xx.dtsi19 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
26 ranges = <0 0x0 0x50000000 0x01000000>,
27 <1 0x0 0x51000000 0x01000000>,
28 <2 0x0 0x52000000 0x01000000>,
29 <3 0x0 0x53000000 0x01000000>,
30 <4 0x0 0x54000000 0x01000000>,
31 <5 0x0 0x55000000 0x01000000>,
32 <6 0x0 0x56000000 0x01000000>,
33 <7 0x0 0x57000000 0x01000000>;
34 dma-ranges = <0 0x0 0x50000000 0x01000000>,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/hwlock/
H A Dst,stm32-hwspinlock.yaml44 reg = <0x4c000000 0x400>;
/openbmc/linux/arch/arm/mach-omap2/
H A Domap44xx.h17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-spear/
H A Dhardware.h10 #define CONFIG_SYS_USBD_BASE 0xE1100000
11 #define CONFIG_SYS_PLUG_BASE 0xE1200000
12 #define CONFIG_SYS_FIFO_BASE 0xE1000800
13 #define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
14 #define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000
15 #define CONFIG_SYS_SMI_BASE 0xFC000000
16 #define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
17 #define CONFIG_SPEAR_TIMERBASE 0xFC800000
18 #define CONFIG_SPEAR_MISCBASE 0xFCA80000
19 #define CONFIG_SPEAR_ETHBASE 0xE0800000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dpxa-usb.txt26 reg = <0x4c000000 0x100000>;
49 reg = <0x40600000 0x10000>;
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dhardware.h30 #define DM_TIMER0_BASE 0x4802C000
31 #define DM_TIMER1_BASE 0x4802E000
32 #define DM_TIMER2_BASE 0x48040000
33 #define DM_TIMER3_BASE 0x48042000
34 #define DM_TIMER4_BASE 0x48044000
35 #define DM_TIMER5_BASE 0x48046000
36 #define DM_TIMER6_BASE 0x48048000
37 #define DM_TIMER7_BASE 0x4804A000
40 #define GPIO0_BASE 0x48032000
41 #define GPIO1_BASE 0x4804C000
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca9.dts16 arm,hbi = <0x191>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 A9_0: cpu@0 {
41 reg = <0>;
69 reg = <0x60000000 0x40000000>;
77 /* Chipselect 3 is physically at 0x4c000000 */
81 reg = <0x4c000000 0x00800000>;
88 reg = <0x10020000 0x1000>;
90 interrupts = <0 44 4>;
[all …]
H A Dvexpress-v2m.dtsi27 ranges = <0x40000000 0x40000000 0x10000000>,
28 <0x10000000 0x10000000 0x00020000>;
31 interrupt-map-mask = <0 63>;
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/arch/arm/mm/
H A Dproc-arm7tdmi.S78 extra_hwcaps=0
83 .long 0
84 .long 0
91 .long 0
92 .long 0
97 arm7tdmi_proc_info arm7tdmi, 0x41007700, 0xfff8ff00, \
99 arm7tdmi_proc_info triscenda7, 0x0001d2ff, 0x0001ffff, \
101 arm7tdmi_proc_info at91, 0x14000040, 0xfff000e0, \
103 arm7tdmi_proc_info s3c4510b, 0x36365000, 0xfffff000, \
105 arm7tdmi_proc_info s3c4530, 0x4c000000, 0xfff000e0, \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dintel,ixp4xx-pci.yaml54 - const: 0xf800
55 - const: 0
56 - const: 0
73 reg = <0xc0000000 0x1000>;
77 bus-range = <0x00 0xff>;
80 <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
81 <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
83 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
86 interrupt-map-mask = <0xf800 0 0 7>;
88 <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear320.dtsi15 ranges = <0x40000000 0x40000000 0x80000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0xb3000000 0x1000>;
26 reg = <0x90000000 0x1000>;
36 reg = <0x4c000000 0x1000 /* FSMC Register */
37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
46 reg = <0x70000000 0x100>;
54 reg = <0xb3000000 0x1000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa27x.dtsi13 reg = <0x40000000 0x10000>;
30 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
31 0x40f00020 0x10>;
37 gpio-ranges = <&pinctrl 0 0 128>;
43 reg = <0x4c000000 0x10000>;
51 reg = <0x40b00000 0x10>;
58 reg = <0x40b00010 0x10>;
65 reg = <0x40c00000 0x10>;
72 reg = <0x40c00010 0x10>;
79 reg = <0x40f00180 0x24>;
[all …]
H A Dpxa3xx.dtsi6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
14 0)
17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/ti/
H A Dk3-bcdma.yaml50 0 - split channel
56 if cell 1 is 0 (split channel):
59 for source thread IDs (rx): 0 - 0x7fff
60 for destination thread IDs (tx): 0x8000 - 0xffff
95 maximum: 0x3f
106 maximum: 0x3f
117 maximum: 0x3f
219 reg = <0x0 0x485c0100 0x0 0x100>,
220 <0x0 0x4c000000 0x0 0x20000>,
221 <0x0 0x4a820000 0x0 0x20000>,
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h9 #define BIT_C 0x00000001
11 #define OP_BLR 0x4e800020
12 #define OP_EXTSB 0x7c000774
13 #define OP_EXTSH 0x7c000734
14 #define OP_NEG 0x7c0000d0
15 #define OP_CNTLZW 0x7c000034
16 #define OP_ADD 0x7c000214
17 #define OP_ADDC 0x7c000014
18 #define OP_ADDME 0x7c0001d4
19 #define OP_ADDZE 0x7c000194
[all …]
/openbmc/qemu/hw/arm/
H A Dvexpress.c50 #define VEXPRESS_BOARD_ID 0x8e0
54 /* Number of virtio transports to create (0..8; limited by
98 [VE_NORFLASHALIAS] = 0,
99 /* CS7: 0x10000000 .. 0x10020000 */
100 [VE_SYSREGS] = 0x10000000,
101 [VE_SP810] = 0x10001000,
102 [VE_SERIALPCI] = 0x10002000,
103 [VE_PL041] = 0x10004000,
104 [VE_MMCI] = 0x10005000,
105 [VE_KMI0] = 0x10006000,
[all …]

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