183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 29b58a3f6SRyan Harkin /* 3cd4f46e1SRyan Harkin * (C) Copyright 2011 ARM Limited 49b58a3f6SRyan Harkin * (C) Copyright 2010 Linaro 59b58a3f6SRyan Harkin * Matt Waddel, <matt.waddel@linaro.org> 69b58a3f6SRyan Harkin * 79b58a3f6SRyan Harkin * Configuration for Versatile Express. Parts were derived from other ARM 89b58a3f6SRyan Harkin * configurations. 99b58a3f6SRyan Harkin */ 109b58a3f6SRyan Harkin 11cd4f46e1SRyan Harkin #ifndef __VEXPRESS_COMMON_H 12cd4f46e1SRyan Harkin #define __VEXPRESS_COMMON_H 13cd4f46e1SRyan Harkin 14cd4f46e1SRyan Harkin /* 15cd4f46e1SRyan Harkin * Definitions copied from linux kernel: 16cd4f46e1SRyan Harkin * arch/arm/mach-vexpress/include/mach/motherboard.h 17cd4f46e1SRyan Harkin */ 18cd4f46e1SRyan Harkin #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP 19cd4f46e1SRyan Harkin /* CS register bases for the original memory map. */ 20cd4f46e1SRyan Harkin #define V2M_PA_CS0 0x40000000 21cd4f46e1SRyan Harkin #define V2M_PA_CS1 0x44000000 22cd4f46e1SRyan Harkin #define V2M_PA_CS2 0x48000000 23cd4f46e1SRyan Harkin #define V2M_PA_CS3 0x4c000000 24cd4f46e1SRyan Harkin #define V2M_PA_CS7 0x10000000 25cd4f46e1SRyan Harkin 26cd4f46e1SRyan Harkin #define V2M_PERIPH_OFFSET(x) (x << 12) 27cd4f46e1SRyan Harkin #define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0)) 28cd4f46e1SRyan Harkin #define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) 29cd4f46e1SRyan Harkin #define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) 30cd4f46e1SRyan Harkin 31cd4f46e1SRyan Harkin #define V2M_BASE 0x60000000 32cd4f46e1SRyan Harkin #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) 33cd4f46e1SRyan Harkin /* CS register bases for the extended memory map. */ 34cd4f46e1SRyan Harkin #define V2M_PA_CS0 0x08000000 35cd4f46e1SRyan Harkin #define V2M_PA_CS1 0x0c000000 36cd4f46e1SRyan Harkin #define V2M_PA_CS2 0x14000000 37cd4f46e1SRyan Harkin #define V2M_PA_CS3 0x18000000 38cd4f46e1SRyan Harkin #define V2M_PA_CS7 0x1c000000 39cd4f46e1SRyan Harkin 40cd4f46e1SRyan Harkin #define V2M_PERIPH_OFFSET(x) (x << 16) 41cd4f46e1SRyan Harkin #define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) 42cd4f46e1SRyan Harkin #define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) 43cd4f46e1SRyan Harkin #define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3)) 44cd4f46e1SRyan Harkin 45cd4f46e1SRyan Harkin #define V2M_BASE 0x80000000 46cd4f46e1SRyan Harkin #endif 47cd4f46e1SRyan Harkin 48cd4f46e1SRyan Harkin /* 49cd4f46e1SRyan Harkin * Physical addresses, offset from V2M_PA_CS0-3 50cd4f46e1SRyan Harkin */ 51cd4f46e1SRyan Harkin #define V2M_NOR0 (V2M_PA_CS0) 52cd4f46e1SRyan Harkin #define V2M_NOR1 (V2M_PA_CS1) 53cd4f46e1SRyan Harkin #define V2M_SRAM (V2M_PA_CS2) 54cd4f46e1SRyan Harkin #define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) 55cd4f46e1SRyan Harkin #define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) 56cd4f46e1SRyan Harkin 57cd4f46e1SRyan Harkin /* Common peripherals relative to CS7. */ 58cd4f46e1SRyan Harkin #define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4)) 59cd4f46e1SRyan Harkin #define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5)) 60cd4f46e1SRyan Harkin #define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6)) 61cd4f46e1SRyan Harkin #define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7)) 62cd4f46e1SRyan Harkin 63cd4f46e1SRyan Harkin #define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9)) 64cd4f46e1SRyan Harkin #define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10)) 65cd4f46e1SRyan Harkin #define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11)) 66cd4f46e1SRyan Harkin #define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12)) 67cd4f46e1SRyan Harkin 68cd4f46e1SRyan Harkin #define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15)) 69cd4f46e1SRyan Harkin 70cd4f46e1SRyan Harkin #define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17)) 71cd4f46e1SRyan Harkin #define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18)) 72cd4f46e1SRyan Harkin 73cd4f46e1SRyan Harkin #define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22)) 74cd4f46e1SRyan Harkin #define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23)) 75cd4f46e1SRyan Harkin 76cd4f46e1SRyan Harkin #define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26)) 77cd4f46e1SRyan Harkin 78cd4f46e1SRyan Harkin #define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31)) 79cd4f46e1SRyan Harkin #define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32) 80cd4f46e1SRyan Harkin 81cd4f46e1SRyan Harkin /* System register offsets. */ 82cd4f46e1SRyan Harkin #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 83cd4f46e1SRyan Harkin #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 84cd4f46e1SRyan Harkin #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 85cd4f46e1SRyan Harkin 86cd4f46e1SRyan Harkin /* 87cd4f46e1SRyan Harkin * Configuration 88cd4f46e1SRyan Harkin */ 89cd4f46e1SRyan Harkin #define SYS_CFG_START (1 << 31) 90cd4f46e1SRyan Harkin #define SYS_CFG_WRITE (1 << 30) 91cd4f46e1SRyan Harkin #define SYS_CFG_OSC (1 << 20) 92cd4f46e1SRyan Harkin #define SYS_CFG_VOLT (2 << 20) 93cd4f46e1SRyan Harkin #define SYS_CFG_AMP (3 << 20) 94cd4f46e1SRyan Harkin #define SYS_CFG_TEMP (4 << 20) 95cd4f46e1SRyan Harkin #define SYS_CFG_RESET (5 << 20) 96cd4f46e1SRyan Harkin #define SYS_CFG_SCC (6 << 20) 97cd4f46e1SRyan Harkin #define SYS_CFG_MUXFPGA (7 << 20) 98cd4f46e1SRyan Harkin #define SYS_CFG_SHUTDOWN (8 << 20) 99cd4f46e1SRyan Harkin #define SYS_CFG_REBOOT (9 << 20) 100cd4f46e1SRyan Harkin #define SYS_CFG_DVIMODE (11 << 20) 101cd4f46e1SRyan Harkin #define SYS_CFG_POWER (12 << 20) 102cd4f46e1SRyan Harkin #define SYS_CFG_SITE_MB (0 << 16) 103cd4f46e1SRyan Harkin #define SYS_CFG_SITE_DB1 (1 << 16) 104cd4f46e1SRyan Harkin #define SYS_CFG_SITE_DB2 (2 << 16) 105cd4f46e1SRyan Harkin #define SYS_CFG_STACK(n) ((n) << 12) 106cd4f46e1SRyan Harkin 107cd4f46e1SRyan Harkin #define SYS_CFG_ERR (1 << 1) 108cd4f46e1SRyan Harkin #define SYS_CFG_COMPLETE (1 << 0) 1099b58a3f6SRyan Harkin 1109b58a3f6SRyan Harkin /* Board info register */ 111cd4f46e1SRyan Harkin #define SYS_ID V2M_SYSREGS 1129b58a3f6SRyan Harkin #define CONFIG_REVISION_TAG 1 1139b58a3f6SRyan Harkin 114cd4f46e1SRyan Harkin #define CONFIG_SYS_MEMTEST_START V2M_BASE 1159b58a3f6SRyan Harkin #define CONFIG_SYS_MEMTEST_END 0x20000000 1169b58a3f6SRyan Harkin 1179b58a3f6SRyan Harkin #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 1189b58a3f6SRyan Harkin #define CONFIG_SETUP_MEMORY_TAGS 1 1199b58a3f6SRyan Harkin #define CONFIG_SYS_L2CACHE_OFF 1 1209b58a3f6SRyan Harkin #define CONFIG_INITRD_TAG 1 1219b58a3f6SRyan Harkin 1229b58a3f6SRyan Harkin /* Size of malloc() pool */ 123*58fcca0cSOtavio Salvador #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */ 1249b58a3f6SRyan Harkin 125cd4f46e1SRyan Harkin #define SCTL_BASE V2M_SYSCTL 1269b58a3f6SRyan Harkin #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) 1279b58a3f6SRyan Harkin 128b3a7f22bSRob Herring #define CONFIG_SYS_TIMER_RATE 1000000 129cb7ee1b9SIan Campbell #define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) 130b3a7f22bSRob Herring #define CONFIG_SYS_TIMER_COUNTS_DOWN 131b3a7f22bSRob Herring 1329b58a3f6SRyan Harkin /* PL011 Serial Configuration */ 1339b58a3f6SRyan Harkin #define CONFIG_PL011_CLOCK 24000000 1349b58a3f6SRyan Harkin #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ 1359b58a3f6SRyan Harkin (void *)CONFIG_SYS_SERIAL1} 1369b58a3f6SRyan Harkin 137cd4f46e1SRyan Harkin #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 138cd4f46e1SRyan Harkin #define CONFIG_SYS_SERIAL0 V2M_UART0 139cd4f46e1SRyan Harkin #define CONFIG_SYS_SERIAL1 V2M_UART1 1409b58a3f6SRyan Harkin 1419b58a3f6SRyan Harkin #define CONFIG_ARM_PL180_MMCI 142cd4f46e1SRyan Harkin #define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI 1439b58a3f6SRyan Harkin #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 1449b58a3f6SRyan Harkin #define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 1459b58a3f6SRyan Harkin 1469b58a3f6SRyan Harkin /* BOOTP options */ 1479b58a3f6SRyan Harkin #define CONFIG_BOOTP_BOOTFILESIZE 1489b58a3f6SRyan Harkin 1499b58a3f6SRyan Harkin /* Miscellaneous configurable options */ 150cd4f46e1SRyan Harkin #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) 151cd4f46e1SRyan Harkin #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) 1529b58a3f6SRyan Harkin 1539b58a3f6SRyan Harkin /* Physical Memory Map */ 154cd4f46e1SRyan Harkin #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ 155cd4f46e1SRyan Harkin #define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \ 156cd4f46e1SRyan Harkin ((unsigned int)0x20000000)) 1579b58a3f6SRyan Harkin #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 1589b58a3f6SRyan Harkin #define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ 1599b58a3f6SRyan Harkin 1609b58a3f6SRyan Harkin /* additions for new relocation code */ 1619b58a3f6SRyan Harkin #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 1629b58a3f6SRyan Harkin #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 1639b58a3f6SRyan Harkin #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ 1649b58a3f6SRyan Harkin CONFIG_SYS_INIT_RAM_SIZE - \ 1659b58a3f6SRyan Harkin GENERATED_GBL_DATA_SIZE) 1669b58a3f6SRyan Harkin #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET 167acb5ff02SDennis Gilmore 1689b58a3f6SRyan Harkin /* Basic environment settings */ 169acb5ff02SDennis Gilmore #define BOOT_TARGET_DEVICES(func) \ 170acb5ff02SDennis Gilmore func(MMC, mmc, 1) \ 171acb5ff02SDennis Gilmore func(MMC, mmc, 0) \ 172acb5ff02SDennis Gilmore func(PXE, pxe, na) \ 173acb5ff02SDennis Gilmore func(DHCP, dhcp, na) 174acb5ff02SDennis Gilmore #include <config_distro_bootcmd.h> 175acb5ff02SDennis Gilmore 176cd4f46e1SRyan Harkin #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP 177cd4f46e1SRyan Harkin #define CONFIG_PLATFORM_ENV_SETTINGS \ 1789b58a3f6SRyan Harkin "loadaddr=0x80008000\0" \ 1799b58a3f6SRyan Harkin "ramdisk_addr_r=0x61000000\0" \ 1809b58a3f6SRyan Harkin "kernel_addr=0x44100000\0" \ 1819b58a3f6SRyan Harkin "ramdisk_addr=0x44800000\0" \ 1829b58a3f6SRyan Harkin "maxramdisk=0x1800000\0" \ 1839b58a3f6SRyan Harkin "pxefile_addr_r=0x88000000\0" \ 184acb5ff02SDennis Gilmore "scriptaddr=0x88000000\0" \ 185cd4f46e1SRyan Harkin "kernel_addr_r=0x80008000\0" 186cd4f46e1SRyan Harkin #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) 187cd4f46e1SRyan Harkin #define CONFIG_PLATFORM_ENV_SETTINGS \ 188cd4f46e1SRyan Harkin "loadaddr=0xa0008000\0" \ 189cd4f46e1SRyan Harkin "ramdisk_addr_r=0x81000000\0" \ 190cd4f46e1SRyan Harkin "kernel_addr=0x0c100000\0" \ 191cd4f46e1SRyan Harkin "ramdisk_addr=0x0c800000\0" \ 192cd4f46e1SRyan Harkin "maxramdisk=0x1800000\0" \ 193cd4f46e1SRyan Harkin "pxefile_addr_r=0xa8000000\0" \ 194acb5ff02SDennis Gilmore "scriptaddr=0xa8000000\0" \ 195cd4f46e1SRyan Harkin "kernel_addr_r=0xa0008000\0" 196cd4f46e1SRyan Harkin #endif 197cd4f46e1SRyan Harkin #define CONFIG_EXTRA_ENV_SETTINGS \ 198cd4f46e1SRyan Harkin CONFIG_PLATFORM_ENV_SETTINGS \ 199acb5ff02SDennis Gilmore BOOTENV \ 2009b58a3f6SRyan Harkin "console=ttyAMA0,38400n8\0" \ 2019b58a3f6SRyan Harkin "dram=1024M\0" \ 2029b58a3f6SRyan Harkin "root=/dev/sda1 rw\0" \ 2039b58a3f6SRyan Harkin "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \ 2049b58a3f6SRyan Harkin "24M@0x2000000(initrd)\0" \ 2059b58a3f6SRyan Harkin "flashargs=setenv bootargs root=${root} console=${console} " \ 2069b58a3f6SRyan Harkin "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \ 2079b58a3f6SRyan Harkin "devtmpfs.mount=0 vmalloc=256M\0" \ 2089b58a3f6SRyan Harkin "bootflash=run flashargs; " \ 2099b58a3f6SRyan Harkin "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \ 2109b58a3f6SRyan Harkin "bootm ${kernel_addr} ${ramdisk_addr_r}\0" 2119b58a3f6SRyan Harkin 2129b58a3f6SRyan Harkin /* FLASH and environment organization */ 2139b58a3f6SRyan Harkin #define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ 2149b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_SIZE 0x04000000 2159b58a3f6SRyan Harkin #define CONFIG_SYS_MAX_FLASH_BANKS 2 216cd4f46e1SRyan Harkin #define CONFIG_SYS_FLASH_BASE0 V2M_NOR0 217cd4f46e1SRyan Harkin #define CONFIG_SYS_FLASH_BASE1 V2M_NOR1 2189b58a3f6SRyan Harkin #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 2199b58a3f6SRyan Harkin 2209b58a3f6SRyan Harkin /* Timeout values in ticks */ 2219b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ 2229b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ 2239b58a3f6SRyan Harkin 2249b58a3f6SRyan Harkin /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ 2259b58a3f6SRyan Harkin #define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ 2269b58a3f6SRyan Harkin #define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ 2279b58a3f6SRyan Harkin 2289b58a3f6SRyan Harkin /* Room required on the stack for the environment data */ 2299b58a3f6SRyan Harkin #define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE 2309b58a3f6SRyan Harkin 2319b58a3f6SRyan Harkin /* 2329b58a3f6SRyan Harkin * Amount of flash used for environment: 2339b58a3f6SRyan Harkin * We don't know which end has the small erase blocks so we use the penultimate 2349b58a3f6SRyan Harkin * sector location for the environment 2359b58a3f6SRyan Harkin */ 2369b58a3f6SRyan Harkin #define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE 2379b58a3f6SRyan Harkin #define CONFIG_ENV_OVERWRITE 1 2389b58a3f6SRyan Harkin 2399b58a3f6SRyan Harkin /* Store environment at top of flash */ 2409b58a3f6SRyan Harkin #define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \ 2419b58a3f6SRyan Harkin (2 * CONFIG_ENV_SECT_SIZE)) 2429b58a3f6SRyan Harkin #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \ 2439b58a3f6SRyan Harkin CONFIG_ENV_OFFSET) 2449b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 2459b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \ 2469b58a3f6SRyan Harkin CONFIG_SYS_FLASH_BASE1 } 2479b58a3f6SRyan Harkin 2489b58a3f6SRyan Harkin /* Monitor Command Prompt */ 2499b58a3f6SRyan Harkin #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 2509b58a3f6SRyan Harkin 251cd4f46e1SRyan Harkin #endif /* VEXPRESS_COMMON_H */ 252