xref: /openbmc/linux/arch/arm/boot/dts/ti/omap/am33xx.dtsi (revision 1937e408)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for AM33XX SoC
4 *
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/pinctrl/am33xx.h>
11#include <dt-bindings/clock/am3.h>
12
13/ {
14	compatible = "ti,am33xx";
15	interrupt-parent = <&intc>;
16	#address-cells = <1>;
17	#size-cells = <1>;
18	chosen { };
19
20	aliases {
21		i2c0 = &i2c0;
22		i2c1 = &i2c1;
23		i2c2 = &i2c2;
24		serial0 = &uart0;
25		serial1 = &uart1;
26		serial2 = &uart2;
27		serial3 = &uart3;
28		serial4 = &uart4;
29		serial5 = &uart5;
30		d-can0 = &dcan0;
31		d-can1 = &dcan1;
32		usb0 = &usb0;
33		usb1 = &usb1;
34		phy0 = &usb0_phy;
35		phy1 = &usb1_phy;
36		ethernet0 = &cpsw_port1;
37		ethernet1 = &cpsw_port2;
38		spi0 = &spi0;
39		spi1 = &spi1;
40		mmc0 = &mmc1;
41		mmc1 = &mmc2;
42		mmc2 = &mmc3;
43	};
44
45	cpus {
46		#address-cells = <1>;
47		#size-cells = <0>;
48		cpu@0 {
49			compatible = "arm,cortex-a8";
50			enable-method = "ti,am3352";
51			device_type = "cpu";
52			reg = <0>;
53
54			operating-points-v2 = <&cpu0_opp_table>;
55
56			clocks = <&dpll_mpu_ck>;
57			clock-names = "cpu";
58
59			clock-latency = <300000>; /* From omap-cpufreq driver */
60			cpu-idle-states = <&mpu_gate>;
61		};
62
63		idle-states {
64			mpu_gate: mpu_gate {
65				compatible = "arm,idle-state";
66				entry-latency-us = <40>;
67				exit-latency-us = <90>;
68				min-residency-us = <300>;
69				ti,idle-wkup-m3;
70			};
71		};
72	};
73
74	cpu0_opp_table: opp-table {
75		compatible = "operating-points-v2-ti-cpu";
76		syscon = <&scm_conf>;
77
78		/*
79		 * The three following nodes are marked with opp-suspend
80		 * because the can not be enabled simultaneously on a
81		 * single SoC.
82		 */
83		opp-50-300000000{
84			/* OPP50 */
85			opp-hz = /bits/ 64 <300000000>;
86			opp-microvolt = <950000 931000 969000>;
87			opp-supported-hw = <0x06 0x0010>;
88			opp-suspend;
89		};
90
91		opp-100-275000000{
92			/* OPP100-1 */
93			opp-hz = /bits/ 64 <275000000>;
94			opp-microvolt = <1100000 1078000 1122000>;
95			opp-supported-hw = <0x01 0x00FF>;
96			opp-suspend;
97		};
98
99		opp-100-300000000{
100			/* OPP100-2 */
101			opp-hz = /bits/ 64 <300000000>;
102			opp-microvolt = <1100000 1078000 1122000>;
103			opp-supported-hw = <0x06 0x0020>;
104			opp-suspend;
105		};
106
107		opp-100-500000000{
108			/* OPP100-3 */
109			opp-hz = /bits/ 64 <500000000>;
110			opp-microvolt = <1100000 1078000 1122000>;
111			opp-supported-hw = <0x01 0xFFFF>;
112		};
113
114		opp-100-600000000 {
115			/* OPP100-4 */
116			opp-hz = /bits/ 64 <600000000>;
117			opp-microvolt = <1100000 1078000 1122000>;
118			opp-supported-hw = <0x06 0x0040>;
119		};
120
121		opp-120-600000000 {
122			/* OPP120-1 */
123			opp-hz = /bits/ 64 <600000000>;
124			opp-microvolt = <1200000 1176000 1224000>;
125			opp-supported-hw = <0x01 0xFFFF>;
126		};
127
128		opp-120-720000000 {
129			/* OPP120-2 */
130			opp-hz = /bits/ 64 <720000000>;
131			opp-microvolt = <1200000 1176000 1224000>;
132			opp-supported-hw = <0x06 0x0080>;
133		};
134
135		opp-720000000 {
136			/* OPP Turbo-1 */
137			opp-hz = /bits/ 64 <720000000>;
138			opp-microvolt = <1260000 1234800 1285200>;
139			opp-supported-hw = <0x01 0xFFFF>;
140		};
141
142		opp-800000000 {
143			/* OPP Turbo-2 */
144			opp-hz = /bits/ 64 <800000000>;
145			opp-microvolt = <1260000 1234800 1285200>;
146			opp-supported-hw = <0x06 0x0100>;
147		};
148
149		opp-1000000000 {
150			/* OPP Nitro */
151			opp-hz = /bits/ 64 <1000000000>;
152			opp-microvolt = <1325000 1298500 1351500>;
153			opp-supported-hw = <0x04 0x0200>;
154		};
155	};
156
157	target-module@4b000000 {
158		compatible = "ti,sysc-omap4-simple", "ti,sysc";
159		clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
160		clock-names = "fck";
161		ti,no-idle;
162		#address-cells = <1>;
163		#size-cells = <1>;
164		ranges = <0x0 0x4b000000 0x1000000>;
165
166		target-module@140000 {
167			compatible = "ti,sysc-omap4-simple", "ti,sysc";
168			clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
169			clock-names = "fck";
170			#address-cells = <1>;
171			#size-cells = <1>;
172			ranges = <0x0 0x140000 0xec0000>;
173
174			pmu@0 {
175				compatible = "arm,cortex-a8-pmu";
176				interrupts = <3>;
177			};
178		};
179	};
180
181	/*
182	 * The soc node represents the soc top level view. It is used for IPs
183	 * that are not memory mapped in the MPU view or for the MPU itself.
184	 */
185	soc {
186		compatible = "ti,omap-infra";
187	};
188
189	/*
190	 * XXX: Use a flat representation of the AM33XX interconnect.
191	 * The real AM33XX interconnect network is quite complex. Since
192	 * it will not bring real advantage to represent that in DT
193	 * for the moment, just use a fake OCP bus entry to represent
194	 * the whole bus hierarchy.
195	 */
196	ocp: ocp {
197		compatible = "simple-pm-bus";
198		power-domains = <&prm_per>;
199		clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
200		clock-names = "fck";
201		#address-cells = <1>;
202		#size-cells = <1>;
203		ranges;
204
205		l4_wkup: interconnect@44c00000 {
206		};
207		l4_per: interconnect@48000000 {
208		};
209		l4_fw: interconnect@47c00000 {
210		};
211		l4_fast: interconnect@4a000000 {
212		};
213		l4_mpuss: interconnect@4b140000 {
214		};
215
216		intc: interrupt-controller@48200000 {
217			compatible = "ti,am33xx-intc";
218			interrupt-controller;
219			#interrupt-cells = <1>;
220			reg = <0x48200000 0x1000>;
221		};
222
223		target-module@49000000 {
224			compatible = "ti,sysc-omap4", "ti,sysc";
225			reg = <0x49000000 0x4>;
226			reg-names = "rev";
227			clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
228			clock-names = "fck";
229			#address-cells = <1>;
230			#size-cells = <1>;
231			ranges = <0x0 0x49000000 0x10000>;
232
233			edma: dma@0 {
234				compatible = "ti,edma3-tpcc";
235				reg = <0 0x10000>;
236				reg-names = "edma3_cc";
237				interrupts = <12 13 14>;
238				interrupt-names = "edma3_ccint", "edma3_mperr",
239						  "edma3_ccerrint";
240				dma-requests = <64>;
241				#dma-cells = <2>;
242
243				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
244					   <&edma_tptc2 0>;
245
246				ti,edma-memcpy-channels = <20 21>;
247			};
248		};
249
250		target-module@49800000 {
251			compatible = "ti,sysc-omap4", "ti,sysc";
252			reg = <0x49800000 0x4>,
253			      <0x49800010 0x4>;
254			reg-names = "rev", "sysc";
255			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
256			ti,sysc-midle = <SYSC_IDLE_FORCE>;
257			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
258					<SYSC_IDLE_SMART>;
259			clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
260			clock-names = "fck";
261			#address-cells = <1>;
262			#size-cells = <1>;
263			ranges = <0x0 0x49800000 0x100000>;
264
265			edma_tptc0: dma@0 {
266				compatible = "ti,edma3-tptc";
267				reg = <0 0x100000>;
268				interrupts = <112>;
269				interrupt-names = "edma3_tcerrint";
270			};
271		};
272
273		target-module@49900000 {
274			compatible = "ti,sysc-omap4", "ti,sysc";
275			reg = <0x49900000 0x4>,
276			      <0x49900010 0x4>;
277			reg-names = "rev", "sysc";
278			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
279			ti,sysc-midle = <SYSC_IDLE_FORCE>;
280			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
281					<SYSC_IDLE_SMART>;
282			clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
283			clock-names = "fck";
284			#address-cells = <1>;
285			#size-cells = <1>;
286			ranges = <0x0 0x49900000 0x100000>;
287
288			edma_tptc1: dma@0 {
289				compatible = "ti,edma3-tptc";
290				reg = <0 0x100000>;
291				interrupts = <113>;
292				interrupt-names = "edma3_tcerrint";
293			};
294		};
295
296		target-module@49a00000 {
297			compatible = "ti,sysc-omap4", "ti,sysc";
298			reg = <0x49a00000 0x4>,
299			      <0x49a00010 0x4>;
300			reg-names = "rev", "sysc";
301			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
302			ti,sysc-midle = <SYSC_IDLE_FORCE>;
303			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
304					<SYSC_IDLE_SMART>;
305			clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
306			clock-names = "fck";
307			#address-cells = <1>;
308			#size-cells = <1>;
309			ranges = <0x0 0x49a00000 0x100000>;
310
311			edma_tptc2: dma@0 {
312				compatible = "ti,edma3-tptc";
313				reg = <0 0x100000>;
314				interrupts = <114>;
315				interrupt-names = "edma3_tcerrint";
316			};
317		};
318
319		target-module@47810000 {
320			compatible = "ti,sysc-omap2", "ti,sysc";
321			reg = <0x478102fc 0x4>,
322			      <0x47810110 0x4>,
323			      <0x47810114 0x4>;
324			reg-names = "rev", "sysc", "syss";
325			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
326					 SYSC_OMAP2_ENAWAKEUP |
327					 SYSC_OMAP2_SOFTRESET |
328					 SYSC_OMAP2_AUTOIDLE)>;
329			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
330					<SYSC_IDLE_NO>,
331					<SYSC_IDLE_SMART>;
332			ti,syss-mask = <1>;
333			clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
334			clock-names = "fck";
335			#address-cells = <1>;
336			#size-cells = <1>;
337			ranges = <0x0 0x47810000 0x1000>;
338
339			mmc3: mmc@0 {
340				compatible = "ti,am335-sdhci";
341				ti,needs-special-reset;
342				interrupts = <29>;
343				reg = <0x0 0x1000>;
344				status = "disabled";
345			};
346		};
347
348		usb: target-module@47400000 {
349			compatible = "ti,sysc-omap4", "ti,sysc";
350			reg = <0x47400000 0x4>,
351			      <0x47400010 0x4>;
352			reg-names = "rev", "sysc";
353			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
354					 SYSC_OMAP4_SOFTRESET)>;
355			ti,sysc-midle = <SYSC_IDLE_FORCE>,
356					<SYSC_IDLE_NO>,
357					<SYSC_IDLE_SMART>;
358			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
359					<SYSC_IDLE_NO>,
360					<SYSC_IDLE_SMART>,
361					<SYSC_IDLE_SMART_WKUP>;
362			ti,sysc-delay-us = <2>;
363			clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
364			clock-names = "fck";
365			#address-cells = <1>;
366			#size-cells = <1>;
367			ranges = <0x0 0x47400000 0x8000>;
368
369			usb0_phy: usb-phy@1300 {
370				compatible = "ti,am335x-usb-phy";
371				reg = <0x1300 0x100>;
372				reg-names = "phy";
373				ti,ctrl_mod = <&usb_ctrl_mod>;
374				#phy-cells = <0>;
375			};
376
377			usb0: usb@1400 {
378				compatible = "ti,musb-am33xx";
379				reg = <0x1400 0x400>,
380				      <0x1000 0x200>;
381				reg-names = "mc", "control";
382
383				interrupts = <18>;
384				interrupt-names = "mc";
385				dr_mode = "otg";
386				mentor,multipoint = <1>;
387				mentor,num-eps = <16>;
388				mentor,ram-bits = <12>;
389				mentor,power = <500>;
390				phys = <&usb0_phy>;
391
392				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
393					&cppi41dma  2 0 &cppi41dma  3 0
394					&cppi41dma  4 0 &cppi41dma  5 0
395					&cppi41dma  6 0 &cppi41dma  7 0
396					&cppi41dma  8 0 &cppi41dma  9 0
397					&cppi41dma 10 0 &cppi41dma 11 0
398					&cppi41dma 12 0 &cppi41dma 13 0
399					&cppi41dma 14 0 &cppi41dma  0 1
400					&cppi41dma  1 1 &cppi41dma  2 1
401					&cppi41dma  3 1 &cppi41dma  4 1
402					&cppi41dma  5 1 &cppi41dma  6 1
403					&cppi41dma  7 1 &cppi41dma  8 1
404					&cppi41dma  9 1 &cppi41dma 10 1
405					&cppi41dma 11 1 &cppi41dma 12 1
406					&cppi41dma 13 1 &cppi41dma 14 1>;
407				dma-names =
408					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
409					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
410					"rx14", "rx15",
411					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
412					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
413					"tx14", "tx15";
414			};
415
416			usb1_phy: usb-phy@1b00 {
417				compatible = "ti,am335x-usb-phy";
418				reg = <0x1b00 0x100>;
419				reg-names = "phy";
420				ti,ctrl_mod = <&usb_ctrl_mod>;
421				#phy-cells = <0>;
422			};
423
424			usb1: usb@1800 {
425				compatible = "ti,musb-am33xx";
426				reg = <0x1c00 0x400>,
427				      <0x1800 0x200>;
428				reg-names = "mc", "control";
429				interrupts = <19>;
430				interrupt-names = "mc";
431				dr_mode = "otg";
432				mentor,multipoint = <1>;
433				mentor,num-eps = <16>;
434				mentor,ram-bits = <12>;
435				mentor,power = <500>;
436				phys = <&usb1_phy>;
437
438				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
439					&cppi41dma 17 0 &cppi41dma 18 0
440					&cppi41dma 19 0 &cppi41dma 20 0
441					&cppi41dma 21 0 &cppi41dma 22 0
442					&cppi41dma 23 0 &cppi41dma 24 0
443					&cppi41dma 25 0 &cppi41dma 26 0
444					&cppi41dma 27 0 &cppi41dma 28 0
445					&cppi41dma 29 0 &cppi41dma 15 1
446					&cppi41dma 16 1 &cppi41dma 17 1
447					&cppi41dma 18 1 &cppi41dma 19 1
448					&cppi41dma 20 1 &cppi41dma 21 1
449					&cppi41dma 22 1 &cppi41dma 23 1
450					&cppi41dma 24 1 &cppi41dma 25 1
451					&cppi41dma 26 1 &cppi41dma 27 1
452					&cppi41dma 28 1 &cppi41dma 29 1>;
453				dma-names =
454					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
455					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
456					"rx14", "rx15",
457					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
458					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
459					"tx14", "tx15";
460			};
461
462			cppi41dma: dma-controller@2000 {
463				compatible = "ti,am3359-cppi41";
464				reg =  <0x0000 0x1000>,
465				       <0x2000 0x1000>,
466				       <0x3000 0x1000>,
467				       <0x4000 0x4000>;
468				reg-names = "glue", "controller", "scheduler", "queuemgr";
469				interrupts = <17>;
470				interrupt-names = "glue";
471				#dma-cells = <2>;
472				/* For backwards compatibility: */
473				#dma-channels = <30>;
474				dma-channels = <30>;
475				#dma-requests = <256>;
476				dma-requests = <256>;
477			};
478		};
479
480		target-module@40300000 {
481			compatible = "ti,sysc-omap4-simple", "ti,sysc";
482			clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
483			clock-names = "fck";
484			ti,no-idle;
485			#address-cells = <1>;
486			#size-cells = <1>;
487			ranges = <0 0x40300000 0x10000>;
488
489			ocmcram: sram@0 {
490				compatible = "mmio-sram";
491				reg = <0 0x10000>; /* 64k */
492				ranges = <0 0 0x10000>;
493				#address-cells = <1>;
494				#size-cells = <1>;
495
496				pm_sram_code: pm-code-sram@0 {
497					compatible = "ti,sram";
498					reg = <0x0 0x1000>;
499					protect-exec;
500				};
501
502				pm_sram_data: pm-data-sram@1000 {
503					compatible = "ti,sram";
504					reg = <0x1000 0x1000>;
505					pool;
506				};
507			};
508		};
509
510		target-module@4c000000 {
511			compatible = "ti,sysc-omap4-simple", "ti,sysc";
512			reg = <0x4c000000 0x4>;
513			reg-names = "rev";
514			clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
515			clock-names = "fck";
516			ti,no-idle;
517			#address-cells = <1>;
518			#size-cells = <1>;
519			ranges = <0x0 0x4c000000 0x1000000>;
520
521			emif: emif@0 {
522				compatible = "ti,emif-am3352";
523				reg = <0 0x1000000>;
524				interrupts = <101>;
525				sram = <&pm_sram_code
526					&pm_sram_data>;
527			};
528		};
529
530		target-module@50000000 {
531			compatible = "ti,sysc-omap2", "ti,sysc";
532			reg = <0x50000000 4>,
533			      <0x50000010 4>,
534			      <0x50000014 4>;
535			reg-names = "rev", "sysc", "syss";
536			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
537					<SYSC_IDLE_NO>,
538					<SYSC_IDLE_SMART>;
539			ti,syss-mask = <1>;
540			clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
541			clock-names = "fck";
542			#address-cells = <1>;
543			#size-cells = <1>;
544			ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
545				 <0x00000000 0x00000000 0x40000000>; /* data */
546
547			gpmc: gpmc@50000000 {
548				compatible = "ti,am3352-gpmc";
549				reg = <0x50000000 0x2000>;
550				interrupts = <100>;
551				dmas = <&edma 52 0>;
552				dma-names = "rxtx";
553				gpmc,num-cs = <7>;
554				gpmc,num-waitpins = <2>;
555				#address-cells = <2>;
556				#size-cells = <1>;
557				interrupt-controller;
558				#interrupt-cells = <2>;
559				gpio-controller;
560				#gpio-cells = <2>;
561				status = "disabled";
562			};
563		};
564
565		sham_target: target-module@53100000 {
566			compatible = "ti,sysc-omap3-sham", "ti,sysc";
567			reg = <0x53100100 0x4>,
568			      <0x53100110 0x4>,
569			      <0x53100114 0x4>;
570			reg-names = "rev", "sysc", "syss";
571			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
572					 SYSC_OMAP2_AUTOIDLE)>;
573			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
574					<SYSC_IDLE_NO>,
575					<SYSC_IDLE_SMART>;
576			ti,syss-mask = <1>;
577			/* Domains (P, C): per_pwrdm, l3_clkdm */
578			clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
579			clock-names = "fck";
580			#address-cells = <1>;
581			#size-cells = <1>;
582			ranges = <0x0 0x53100000 0x1000>;
583
584			sham: sham@0 {
585				compatible = "ti,omap4-sham";
586				reg = <0 0x200>;
587				interrupts = <109>;
588				dmas = <&edma 36 0>;
589				dma-names = "rx";
590			};
591		};
592
593		aes_target: target-module@53500000 {
594			compatible = "ti,sysc-omap2", "ti,sysc";
595			reg = <0x53500080 0x4>,
596			      <0x53500084 0x4>,
597			      <0x53500088 0x4>;
598			reg-names = "rev", "sysc", "syss";
599			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
600					 SYSC_OMAP2_AUTOIDLE)>;
601			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
602					<SYSC_IDLE_NO>,
603					<SYSC_IDLE_SMART>,
604					<SYSC_IDLE_SMART_WKUP>;
605			ti,syss-mask = <1>;
606			/* Domains (P, C): per_pwrdm, l3_clkdm */
607			clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
608			clock-names = "fck";
609			#address-cells = <1>;
610			#size-cells = <1>;
611			ranges = <0x0 0x53500000 0x1000>;
612
613			aes: aes@0 {
614				compatible = "ti,omap4-aes";
615				reg = <0 0xa0>;
616				interrupts = <103>;
617				dmas = <&edma 6 0>,
618				       <&edma 5 0>;
619				dma-names = "tx", "rx";
620			};
621		};
622
623		target-module@56000000 {
624			compatible = "ti,sysc-omap4", "ti,sysc";
625			reg = <0x5600fe00 0x4>,
626			      <0x5600fe10 0x4>;
627			reg-names = "rev", "sysc";
628			ti,sysc-midle = <SYSC_IDLE_FORCE>,
629					<SYSC_IDLE_NO>,
630					<SYSC_IDLE_SMART>;
631			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
632					<SYSC_IDLE_NO>,
633					<SYSC_IDLE_SMART>;
634			clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
635			clock-names = "fck";
636			power-domains = <&prm_gfx>;
637			resets = <&prm_gfx 0>;
638			reset-names = "rstctrl";
639			#address-cells = <1>;
640			#size-cells = <1>;
641			ranges = <0 0x56000000 0x1000000>;
642
643			/*
644			 * Closed source PowerVR driver, no child device
645			 * binding or driver in mainline
646			 */
647		};
648	};
649};
650
651#include "am33xx-l4.dtsi"
652#include "am33xx-clocks.dtsi"
653
654&prcm {
655	prm_per: prm@c00 {
656		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
657		reg = <0xc00 0x100>;
658		#reset-cells = <1>;
659		#power-domain-cells = <0>;
660	};
661
662	prm_wkup: prm@d00 {
663		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
664		reg = <0xd00 0x100>;
665		#reset-cells = <1>;
666		#power-domain-cells = <0>;
667	};
668
669	prm_mpu: prm@e00 {
670		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
671		reg = <0xe00 0x100>;
672		#power-domain-cells = <0>;
673	};
674
675	prm_device: prm@f00 {
676		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
677		reg = <0xf00 0x100>;
678		#reset-cells = <1>;
679	};
680
681	prm_rtc: prm@1000 {
682		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
683		reg = <0x1000 0x100>;
684		#power-domain-cells = <0>;
685	};
686
687	prm_gfx: prm@1100 {
688		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
689		reg = <0x1100 0x100>;
690		#power-domain-cells = <0>;
691		#reset-cells = <1>;
692	};
693
694	prm_cefuse: prm@1200 {
695		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
696		reg = <0x1200 0x100>;
697		#power-domain-cells = <0>;
698	};
699};
700
701/* Preferred always-on timer for clocksource */
702&timer1_target {
703	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
704		 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
705	clock-names = "fck", "ick";
706	ti,no-reset-on-init;
707	ti,no-idle;
708	timer@0 {
709		assigned-clocks = <&timer1_fck>;
710		assigned-clock-parents = <&sys_clkin_ck>;
711	};
712};
713
714/* Preferred timer for clockevent */
715&timer2_target {
716	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
717		 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
718	clock-names = "fck", "ick";
719	ti,no-reset-on-init;
720	ti,no-idle;
721	timer@0 {
722		assigned-clocks = <&timer2_fck>;
723		assigned-clock-parents = <&sys_clkin_ck>;
724	};
725};
726