1*ace5219fSLinus Walleij# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*ace5219fSLinus Walleij%YAML 1.2
3*ace5219fSLinus Walleij---
4*ace5219fSLinus Walleij$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
5*ace5219fSLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml#
6*ace5219fSLinus Walleij
7*ace5219fSLinus Walleijtitle: Intel IXP4xx PCI controller
8*ace5219fSLinus Walleij
9*ace5219fSLinus Walleijmaintainers:
10*ace5219fSLinus Walleij  - Linus Walleij <linus.walleij@linaro.org>
11*ace5219fSLinus Walleij
12*ace5219fSLinus Walleijdescription: PCI host controller found in the Intel IXP4xx SoC series.
13*ace5219fSLinus Walleij
14*ace5219fSLinus WalleijallOf:
15*ace5219fSLinus Walleij  - $ref: /schemas/pci/pci-bus.yaml#
16*ace5219fSLinus Walleij
17*ace5219fSLinus Walleijproperties:
18*ace5219fSLinus Walleij  compatible:
19*ace5219fSLinus Walleij    items:
20*ace5219fSLinus Walleij      - enum:
21*ace5219fSLinus Walleij          - intel,ixp42x-pci
22*ace5219fSLinus Walleij          - intel,ixp43x-pci
23*ace5219fSLinus Walleij    description: The two supported variants are ixp42x and ixp43x,
24*ace5219fSLinus Walleij      though more variants may exist.
25*ace5219fSLinus Walleij
26*ace5219fSLinus Walleij  reg:
27*ace5219fSLinus Walleij    items:
28*ace5219fSLinus Walleij      - description: IXP4xx-specific registers
29*ace5219fSLinus Walleij
30*ace5219fSLinus Walleij  interrupts:
31*ace5219fSLinus Walleij    items:
32*ace5219fSLinus Walleij      - description: Main PCI interrupt
33*ace5219fSLinus Walleij      - description: PCI DMA interrupt 1
34*ace5219fSLinus Walleij      - description: PCI DMA interrupt 2
35*ace5219fSLinus Walleij
36*ace5219fSLinus Walleij  ranges:
37*ace5219fSLinus Walleij    maxItems: 2
38*ace5219fSLinus Walleij    description: Typically one memory range of 64MB and one IO
39*ace5219fSLinus Walleij      space range of 64KB.
40*ace5219fSLinus Walleij
41*ace5219fSLinus Walleij  dma-ranges:
42*ace5219fSLinus Walleij    maxItems: 1
43*ace5219fSLinus Walleij    description: The DMA range tells the PCI host which addresses
44*ace5219fSLinus Walleij      the RAM is at. It can map only 64MB so if the RAM is bigger
45*ace5219fSLinus Walleij      than 64MB the DMA access has to be restricted to these
46*ace5219fSLinus Walleij      addresses.
47*ace5219fSLinus Walleij
48*ace5219fSLinus Walleij  "#interrupt-cells": true
49*ace5219fSLinus Walleij
50*ace5219fSLinus Walleij  interrupt-map: true
51*ace5219fSLinus Walleij
52*ace5219fSLinus Walleij  interrupt-map-mask:
53*ace5219fSLinus Walleij    items:
54*ace5219fSLinus Walleij      - const: 0xf800
55*ace5219fSLinus Walleij      - const: 0
56*ace5219fSLinus Walleij      - const: 0
57*ace5219fSLinus Walleij      - const: 7
58*ace5219fSLinus Walleij
59*ace5219fSLinus Walleijrequired:
60*ace5219fSLinus Walleij  - compatible
61*ace5219fSLinus Walleij  - reg
62*ace5219fSLinus Walleij  - dma-ranges
63*ace5219fSLinus Walleij  - "#interrupt-cells"
64*ace5219fSLinus Walleij  - interrupt-map
65*ace5219fSLinus Walleij  - interrupt-map-mask
66*ace5219fSLinus Walleij
67*ace5219fSLinus WalleijunevaluatedProperties: false
68*ace5219fSLinus Walleij
69*ace5219fSLinus Walleijexamples:
70*ace5219fSLinus Walleij  - |
71*ace5219fSLinus Walleij    pci@c0000000 {
72*ace5219fSLinus Walleij      compatible = "intel,ixp43x-pci";
73*ace5219fSLinus Walleij      reg = <0xc0000000 0x1000>;
74*ace5219fSLinus Walleij      #address-cells = <3>;
75*ace5219fSLinus Walleij      #size-cells = <2>;
76*ace5219fSLinus Walleij      device_type = "pci";
77*ace5219fSLinus Walleij      bus-range = <0x00 0xff>;
78*ace5219fSLinus Walleij
79*ace5219fSLinus Walleij      ranges =
80*ace5219fSLinus Walleij        <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
81*ace5219fSLinus Walleij        <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
82*ace5219fSLinus Walleij      dma-ranges =
83*ace5219fSLinus Walleij        <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
84*ace5219fSLinus Walleij
85*ace5219fSLinus Walleij      #interrupt-cells = <1>;
86*ace5219fSLinus Walleij      interrupt-map-mask = <0xf800 0 0 7>;
87*ace5219fSLinus Walleij      interrupt-map =
88*ace5219fSLinus Walleij        <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
89*ace5219fSLinus Walleij        <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
90*ace5219fSLinus Walleij        <0x0800 0 0 3 &gpio0 9  3>, /* INT C on slot 1 is irq 9 */
91*ace5219fSLinus Walleij        <0x0800 0 0 4 &gpio0 8  3>, /* INT D on slot 1 is irq 8 */
92*ace5219fSLinus Walleij        <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
93*ace5219fSLinus Walleij        <0x1000 0 0 2 &gpio0 9  3>, /* INT B on slot 2 is irq 9 */
94*ace5219fSLinus Walleij        <0x1000 0 0 3 &gpio0 8  3>, /* INT C on slot 2 is irq 8 */
95*ace5219fSLinus Walleij        <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
96*ace5219fSLinus Walleij        <0x1800 0 0 1 &gpio0 9  3>, /* INT A on slot 3 is irq 9 */
97*ace5219fSLinus Walleij        <0x1800 0 0 2 &gpio0 8  3>, /* INT B on slot 3 is irq 8 */
98*ace5219fSLinus Walleij        <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
99*ace5219fSLinus Walleij        <0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */
100*ace5219fSLinus Walleij    };
101