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12

/openbmc/u-boot/arch/arm/mach-bcm283x/include/mach/
H A Dwdog.h10 #define BCM2835_WDOG_PHYSADDR 0x3f100000
12 #define BCM2835_WDOG_PHYSADDR 0x20100000
22 #define BCM2835_WDOG_PASSWORD 0x5a000000
24 #define BCM2835_WDOG_RSTC_WRCFG_MASK 0x00000030
25 #define BCM2835_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020
27 #define BCM2835_WDOG_WDOG_TIMEOUT_MASK 0x0000ffff
/openbmc/linux/drivers/mfd/
H A Drsmu.h13 #define RSMU_CM_SCSR_BASE 0x20100000
/openbmc/u-boot/configs/
H A Dat91rm9200ek_ram_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
H A Dls1088aqds_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
15 …RGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 d…
H A Dls2081ardb_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
15 …RGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 d…
H A Dls1088aqds_qspi_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
16 …RGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 d…
H A Dls1088ardb_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
15 …RGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 d…
H A Dls2088ardb_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
15 …RGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 d…
H A Dls2080aqds_qspi_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
14 …RGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 d…
H A Dls2088ardb_qspi_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
H A Dls1088ardb_qspi_SECURE_BOOT_defconfig3 CONFIG_SYS_TEXT_BASE=0x20100000
16 …RGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 d…
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsprd-dma.txt23 reg = <0x20100000 0x4000>;
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-stm.yaml90 reg = <0x20100000 0x1000>,
91 <0x28000000 0x180000>;
/openbmc/u-boot/include/configs/
H A Dat91rm9200ek.h21 * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0
22 * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
57 #define CONFIG_SYS_SDRAM_BASE 0x20000000
70 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
71 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
74 #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
75 #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
77 #define CONFIG_SYS_MCKR_VAL 0x00000202
80 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
81 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi24 reg = <0 0x20210000 0 0x10000>;
29 reg = <0 0x402b0000 0 0x10000>;
34 reg = <0 0x402e0000 0 0x10000>;
39 reg = <0 0x40400000 0 0x10000>;
44 reg = <0 0x415e0000 0 0x1000000>;
49 reg = <0 0x61100000 0 0x10000>;
54 reg = <0 0x62100000 0 0x10000>;
59 reg = <0 0x63100000 0 0x10000>;
64 reg = <0 0x70b00000 0 0x40000>;
71 ranges = <0 0x0 0x70000000 0x10000000>;
[all …]
H A Dums512.dtsi18 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
60 reg = <0x0 0x100>;
68 reg = <0x0 0x200>;
76 reg = <0x0 0x300>;
84 reg = <0x0 0x400>;
92 reg = <0x0 0x500>;
100 reg = <0x0 0x600>;
108 reg = <0x0 0x700>;
[all …]
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
23 reg = <0>;
173 #clock-cells = <0>;
178 mboxes = <&mbox 0>;
189 reg = <0x0 0x2010000 0x0 0x1000>;
201 reg = <0x0 0x2000000 0x0 0xC000>;
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
211 reg = <0x0 0xc000000 0x0 0x4000000>;
212 #address-cells = <0>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgf110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dipq6018.dtsi22 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 CPU0: cpu@0 {
39 reg = <0x0>;
52 reg = <0x1>;
64 reg = <0x2>;
76 reg = <0x3>;
94 qcom,dload-mode = <&tcsr 0x6100>;
156 mboxes = <&apcs_glb 0>;
[all …]
H A Dipq8074.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
[all …]
/openbmc/qemu/hw/riscv/
H A Dmicrochip_pfsoc.c11 * 0) CLINT (Core Level Interruptor)
62 #define RESET_VECTOR 0x20220000
68 #define GEM_REVISION 0x0107010c
89 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
90 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
91 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
92 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
93 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
94 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
95 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
[all …]
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
16 ranges = <0 0x0 0x2a820000 0x20000>;
21 reg = <0x10000 0x10000>;
27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
38 reg = <0x0 0x2b400000 0x0 0x10000>;
50 reg = <0x0 0x2b500000 0x0 0x10000>;
61 reg = <0x0 0x2b600000 0x0 0x10000>;
67 power-domains = <&scpi_devpd 0>;
72 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
22 <0x01 0x00000000 0x00 0x2000>, /* GICC */
23 <0x01 0x00010000 0x00 0x1000>, /* GICH */
24 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
H A Dk3-am62-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]

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