Lines Matching +full:0 +full:x20100000
22 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 CPU0: cpu@0 {
39 reg = <0x0>;
52 reg = <0x1>;
64 reg = <0x2>;
76 reg = <0x3>;
94 qcom,dload-mode = <&tcsr 0x6100>;
156 mboxes = <&apcs_glb 0>;
181 reg = <0x0 0x00060000 0x0 0x6000>;
186 reg = <0x0 0x4a100000 0x0 0x400000>;
191 reg = <0x0 0x4a500000 0x0 0x100000>;
196 reg = <0x0 0x4a600000 0x0 0x400000>;
201 reg = <0x0 0x4aa00000 0x0 0x100000>;
206 reg = <0x0 0x4ab00000 0x0 0x5500000>;
217 soc: soc@0 {
220 ranges = <0 0 0 0 0x0 0xffffffff>;
226 reg = <0x0 0x00059000 0x0 0x180>;
227 #phy-cells = <0>;
239 reg = <0x0 0x00078000 0x0 0x1c4>;
254 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
255 <0x0 0x00078400 0x0 0x200>, /* Rx */
256 <0x0 0x00078800 0x0 0x1f8>, /* PCS */
257 <0x0 0x00078600 0x0 0x044>; /* PCS misc */
258 #phy-cells = <0>;
259 #clock-cells = <0>;
268 reg = <0x0 0x00079000 0x0 0x180>;
269 #phy-cells = <0>;
281 reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
297 reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
298 <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
299 <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
300 <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
301 #phy-cells = <0>;
306 #clock-cells = <0>;
312 #size-cells = <0>;
314 reg = <0x0 0x00090000 0x0 0x64>;
322 reg = <0x0 0x000a4000 0x0 0x2000>;
329 reg = <0x0 0x000e3000 0x0 0x1000>;
336 reg = <0x0 0x00704000 0x0 0x20000>;
347 reg = <0x0 0x0073a000 0x0 0x6000>;
358 reg = <0x0 0x01000000 0x0 0x300000>;
362 gpio-ranges = <&tlmm 0 0 80>;
387 reg = <0x0 0x01800000 0x0 0x80000>;
396 reg = <0x0 0x01905000 0x0 0x20000>;
402 reg = <0x0 0x01937000 0x0 0x21000>;
407 reg = <0x0 0x070f8800 0x0 0x400>;
427 reg = <0x0 0x07000000 0x0 0xcd00>;
433 snps,hird-threshold = /bits/ 8 <0x0>;
442 reg = <0x0 0x07884000 0x0 0x2b000>;
447 qcom,ee = <0>;
452 reg = <0x0 0x078b1000 0x0 0x200>;
463 #size-cells = <0>;
464 reg = <0x0 0x078b5000 0x0 0x600>;
477 #size-cells = <0>;
478 reg = <0x0 0x078b6000 0x0 0x600>;
491 #size-cells = <0>;
492 reg = <0x0 0x078b6000 0x0 0x600>;
506 #size-cells = <0>;
507 reg = <0x0 0x078b7000 0x0 0x600>;
520 reg = <0x0 0x07984000 0x0 0x1a000>;
525 qcom,ee = <0>;
531 reg = <0x0 0x079b0000 0x0 0x10000>;
533 #size-cells = <0>;
538 dmas = <&qpic_bam 0>,
542 pinctrl-0 = <&qpic_pins>;
549 reg = <0x0 0x08af8800 0x0 0x400>;
575 reg = <0x0 0x08a00000 0x0 0xcd00>;
584 snps,hird-threshold = /bits/ 8 <0x0>;
597 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
598 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/
599 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/
600 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/
602 ranges = <0 0 0 0xb00a000 0 0xffd>;
604 v2m@0 {
607 reg = <0x0 0x0 0x0 0xffd>;
614 reg = <0x0 0x0b017000 0x0 0x40>;
621 reg = <0x0 0x0b111000 0x0 0x1000>;
630 reg = <0x0 0x0b116000 0x0 0x40>;
631 #clock-cells = <0>;
639 ranges = <0 0 0 0x10000000>;
641 reg = <0x0 0x0b120000 0x0 0x1000>;
644 frame-number = <0>;
647 reg = <0x0b121000 0x1000>,
648 <0x0b122000 0x1000>;
654 reg = <0x0b123000 0x1000>;
661 reg = <0x0b124000 0x1000>;
668 reg = <0x0b125000 0x1000>;
675 reg = <0x0b126000 0x1000>;
682 reg = <0x0b127000 0x1000>;
689 reg = <0x0b128000 0x1000>;
696 reg = <0x0 0x0cd00000 0x0 0x4040>,
697 <0x0 0x004ab000 0x0 0x20>;
701 <&wcss_smp2p_in 0 0>,
702 <&wcss_smp2p_in 1 0>,
703 <&wcss_smp2p_in 2 0>,
704 <&wcss_smp2p_in 3 0>;
722 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
724 qcom,smem-states = <&wcss_smp2p_out 0>,
745 reg = <0x0 0x20000000 0x0 0xf1d>,
746 <0x0 0x20000f20 0x0 0xa8>,
747 <0x0 0x20001000 0x0 0x1000>,
748 <0x0 0x80000 0x0 0x4000>,
749 <0x0 0x20100000 0x0 0x1000>;
753 linux,pci-domain = <0>;
754 bus-range = <0x00 0xff>;
763 ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
764 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
770 interrupt-map-mask = <0 0 0 0x7>;
771 interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
772 <0 0 0 2 &intc 0 0 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
773 <0 0 0 3 &intc 0 0 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
774 <0 0 0 4 &intc 0 0 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
825 qcom,local-pid = <0>;