arm64: dts: ti: k3-am62a-main: Fix GPIO pin count in DT nodes

[ Upstream commit 7dc4af358cc382c5d20bd5b726e53ef0f526eb6d ]

Fix number of gpio pins in main_gpio0 & main_gpio1 DT nodes according
to A

arm64: dts: ti: k3-am62a-main: Fix GPIO pin count in DT nodes

[ Upstream commit 7dc4af358cc382c5d20bd5b726e53ef0f526eb6d ]

Fix number of gpio pins in main_gpio0 & main_gpio1 DT nodes according
to AM62A7 datasheet[0].

[0] https://www.ti.com/lit/gpn/am62a3 Section: 6.3.10 GPIO (Page No. 52-55)
Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs")
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Link: https://lore.kernel.org/r/20231027065930.1187405-1-n-yadav@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: ti: k3-am62a: Remove syscon compatible from epwm_tbclk

The other instances have been fixed, but AM62a seems to have been missed,
fix this here.

Signed-off-by: Andrew Davis <afd@ti.com>

arm64: dts: ti: k3-am62a: Remove syscon compatible from epwm_tbclk

The other instances have been fixed, but AM62a seems to have been missed,
fix this here.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230802174521.236255-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: minor whitespace cleanup around '='

The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org

arm64: dts: ti: minor whitespace cleanup around '='

The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230702185221.44319-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62a-main: Add sa3_secproxy

Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with

arm64: dts: ti: k3-am62a-main: Add sa3_secproxy

Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. This is in addition to the one in the main domain DMSS
subsystem that is used for general purpose communication.

Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.

Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62a: Add watchdog nodes

Add nodes for watchdogs:
- 5 in main domain
- 1 in MCU domain
- 1 in wakeup domain

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren

arm64: dts: ti: k3-am62a: Add watchdog nodes

Add nodes for watchdogs:
- 5 in main domain
- 1 in MCU domain
- 1 in wakeup domain

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230418012717.1230882-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62a: Add general purpose timers

Similar to commit 3308a31c507c ("arm64: dts: ti: k3-am62: Add general
purpose timers for am62"), there are 12 general purpose timers on am62a7
sp

arm64: dts: ti: k3-am62a: Add general purpose timers

Similar to commit 3308a31c507c ("arm64: dts: ti: k3-am62: Add general
purpose timers for am62"), there are 12 general purpose timers on am62a7
split between 8 in main and 4 in mcu domains. The 4 in mcu domain do not
have interrupts that are routable to a53.

We configure the timers with the 25 MHz input clock by default as the
32.768 kHz clock may not be wired on the device. We leave the MCU domain
timers clock mux unconfigured, and mark the MCU domain timers reserved.
The MCU domain timers are likely reserved by the software for the ESM
module.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230418012717.1230882-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62a-main: Add more peripheral nodes

Add DT nodes for main domain SPI, PWM, DMA, CPSW (ethernet), mailbox,
spinlock, USB and CAN.

Co-developed-by: Bryan Brattlof <bb@ti.com>
Sig

arm64: dts: ti: k3-am62a-main: Add more peripheral nodes

Add DT nodes for main domain SPI, PWM, DMA, CPSW (ethernet), mailbox,
spinlock, USB and CAN.

Co-developed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230103042110.1092122-3-vigneshr@ti.com

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arm64: dts: ti: Introduce AM62A7 family of SoCs

The AM62A SoC belongs to the K3 Multicore SoC architecture platform that
can run edge AI applications with Video/Vision processing. This provides
adva

arm64: dts: ti: Introduce AM62A7 family of SoCs

The AM62A SoC belongs to the K3 Multicore SoC architecture platform that
can run edge AI applications with Video/Vision processing. This provides
advanced system integration with high security support to enable a broad
set of applications in industrial/automotive markets such as, driver
monitoring, machine vision, smart camera, eMirror, front camera,
robotics, and building automation.

Some highlights of AM62A SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
core variants are provided in the same package to allow HW compatible
designs.
* One Device manager Cortex-R5F for system power and resource management, and
one Cortex-R5F for Functional Safety or general-purpose usage.
* One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier
accelerator (MMA) for Deep Learning usage.
* VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to
315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging
and vision image processing.
* H.264/H.265 Video Encode/Decode. + Motion JPEG encode
* Display support, providing 24-bit RBG parallel interface up to 200MHz pixel
clock support for 2K display resolution.
* Integrated Giga-bit Ethernet switch supporting up to a total of two external
ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA
connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for
Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure boot,
debug security and crypto acceleration and trusted execution environment
* One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling
battery powered system design.

More details about the SoCs can be found in the Technical Reference Manual:
https://www.ti.com/lit/zip/spruj16

Co-developed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com

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