Lines Matching +full:0 +full:x20100000
11 * 0) CLINT (Core Level Interruptor)
62 #define RESET_VECTOR 0x20220000
68 #define GEM_REVISION 0x0107010c
89 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
90 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
91 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
92 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
93 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
94 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
95 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
96 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
97 [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
98 [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
99 [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
100 [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
101 [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
102 [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
103 [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
104 [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
105 [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 },
106 [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
107 [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 },
108 [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
109 [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
110 [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
111 [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
112 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
113 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
114 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
115 [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 },
116 [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 },
117 [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 },
118 [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 },
119 [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
120 [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
121 [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 },
122 [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
123 [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 },
124 [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 },
125 [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
126 [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
127 [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
128 [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
129 [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
130 [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 },
131 [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
132 [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
133 [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 },
134 [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
135 [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
136 [MICROCHIP_PFSOC_FABRIC_FIC0] = { 0x2000000000, 0x1000000000 },
137 [MICROCHIP_PFSOC_FABRIC_FIC1] = { 0x3000000000, 0x1000000000 },
138 [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 },
139 [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
140 [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
141 [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
142 [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
152 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); in microchip_pfsoc_soc_instance_init()
157 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); in microchip_pfsoc_soc_instance_init()
218 /* Reserved Memory at address 0 */ in microchip_pfsoc_soc_realize()
251 0, ms->smp.cpus, false); in microchip_pfsoc_soc_realize()
254 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, in microchip_pfsoc_soc_realize()
282 plic_hart_config, ms->smp.cpus, 0, in microchip_pfsoc_soc_realize()
296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, in microchip_pfsoc_soc_realize()
298 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { in microchip_pfsoc_soc_realize()
306 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, in microchip_pfsoc_soc_realize()
308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0, in microchip_pfsoc_soc_realize()
329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, in microchip_pfsoc_soc_realize()
334 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, in microchip_pfsoc_soc_realize()
339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, in microchip_pfsoc_soc_realize()
341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, in microchip_pfsoc_soc_realize()
348 serial_hd(0)); in microchip_pfsoc_soc_realize()
419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, in microchip_pfsoc_soc_realize()
421 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, in microchip_pfsoc_soc_realize()
427 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, in microchip_pfsoc_soc_realize()
429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, in microchip_pfsoc_soc_realize()
453 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, in microchip_pfsoc_soc_realize()
455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0, in microchip_pfsoc_soc_realize()
523 DriveInfo *dinfo = drive_get(IF_SD, 0, 0); in type_init()
543 0, mem_low_size); in type_init()
559 mem_low, 0, mem_low_size); in type_init()
565 mem_high, 0, mem_high_size); in type_init()