Lines Matching +full:0 +full:x20100000
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
47 reg = <0x00 0x00100000 0x00 0x20000>;
50 ranges = <0x0 0x00 0x00100000 0x20000>;
54 reg = <0x4044 0x8>;
60 reg = <0x4130 0x4>;
66 reg = <0x82e0 0x4>;
67 clocks = <&k3_clks 157 0>;
68 assigned-clocks = <&k3_clks 157 0>;
70 #clock-cells = <0>;
75 reg = <0x82e4 0x4>;
79 #clock-cells = <0>;
88 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
96 reg = <0x00 0x4d000000 0x00 0x80000>,
97 <0x00 0x4a600000 0x00 0x80000>,
98 <0x00 0x4a400000 0x00 0x80000>;
105 reg = <0x00 0x48000000 0x00 0x100000>;
106 #interrupt-cells = <0>;
118 reg = <0x00 0x485c0100 0x00 0x100>,
119 <0x00 0x4c000000 0x00 0x20000>,
120 <0x00 0x4a820000 0x00 0x20000>,
121 <0x00 0x4aa40000 0x00 0x20000>,
122 <0x00 0x4bc00000 0x00 0x100000>;
129 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
130 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
131 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
136 reg = <0x00 0x485c0000 0x00 0x100>,
137 <0x00 0x4a800000 0x00 0x20000>,
138 <0x00 0x4aa00000 0x00 0x40000>,
139 <0x00 0x4b800000 0x00 0x400000>;
146 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
147 <0x24>, /* CPSW_TX_CHAN */
148 <0x25>, /* SAUL_TX_0_CHAN */
149 <0x26>; /* SAUL_TX_1_CHAN */
150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
151 <0x11>, /* RING_CPSW_TX_CHAN */
152 <0x12>, /* RING_SAUL_TX_0_CHAN */
153 <0x13>; /* RING_SAUL_TX_1_CHAN */
154 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
155 <0x2b>, /* CPSW_RX_CHAN */
156 <0x2d>, /* SAUL_RX_0_CHAN */
157 <0x2f>, /* SAUL_RX_1_CHAN */
158 <0x31>, /* SAUL_RX_2_CHAN */
159 <0x33>; /* SAUL_RX_3_CHAN */
160 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
161 <0x2c>, /* FLOW_CPSW_RX_CHAN */
162 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
163 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
174 reg = <0x00 0x44043000 0x00 0xfe0>;
194 reg = <0x00 0x40900000 0x00 0x1200>;
197 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
199 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
200 <&main_pktdma 0x7507 0>;
208 reg = <0x00 0x43600000 0x00 0x10000>,
209 <0x00 0x44880000 0x00 0x20000>,
210 <0x00 0x44860000 0x00 0x20000>;
221 reg = <0x00 0xf4000 0x00 0x2ac>;
224 pinctrl-single,function-mask = <0xffffffff>;
229 reg = <0x00 0x420000 0x00 0x1000>;
235 reg = <0x00 0x2400000 0x00 0x400>;
247 reg = <0x00 0x2410000 0x00 0x400>;
259 reg = <0x00 0x2420000 0x00 0x400>;
271 reg = <0x00 0x2430000 0x00 0x400>;
283 reg = <0x00 0x2440000 0x00 0x400>;
295 reg = <0x00 0x2450000 0x00 0x400>;
307 reg = <0x00 0x2460000 0x00 0x400>;
319 reg = <0x00 0x2470000 0x00 0x400>;
331 reg = <0x00 0x02800000 0x00 0x100>;
334 clocks = <&k3_clks 146 0>;
341 reg = <0x00 0x02810000 0x00 0x100>;
344 clocks = <&k3_clks 152 0>;
351 reg = <0x00 0x02820000 0x00 0x100>;
354 clocks = <&k3_clks 153 0>;
361 reg = <0x00 0x02830000 0x00 0x100>;
364 clocks = <&k3_clks 154 0>;
371 reg = <0x00 0x02840000 0x00 0x100>;
374 clocks = <&k3_clks 155 0>;
381 reg = <0x00 0x02850000 0x00 0x100>;
384 clocks = <&k3_clks 156 0>;
391 reg = <0x00 0x02860000 0x00 0x100>;
394 clocks = <&k3_clks 158 0>;
401 reg = <0x00 0x20000000 0x00 0x100>;
404 #size-cells = <0>;
413 reg = <0x00 0x20010000 0x00 0x100>;
416 #size-cells = <0>;
425 reg = <0x00 0x20020000 0x00 0x100>;
428 #size-cells = <0>;
437 reg = <0x00 0x20030000 0x00 0x100>;
440 #size-cells = <0>;
449 reg = <0x00 0x20100000 0x00 0x400>;
452 #size-cells = <0>;
454 clocks = <&k3_clks 141 0>;
460 reg = <0x00 0x20110000 0x00 0x400>;
463 #size-cells = <0>;
465 clocks = <&k3_clks 142 0>;
471 reg = <0x00 0x20120000 0x00 0x400>;
474 #size-cells = <0>;
476 clocks = <&k3_clks 143 0>;
482 reg = <0x00 0x00a00000 0x00 0x800>;
489 ti,interrupt-ranges = <0 32 16>;
494 reg = <0x0 0x00600000 0x0 0x100>;
503 ti,davinci-gpio-unbanked = <0>;
505 clocks = <&k3_clks 77 0>;
511 reg = <0x0 0x00601000 0x0 0x100>;
520 ti,davinci-gpio-unbanked = <0>;
522 clocks = <&k3_clks 78 0>;
528 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
537 ti,trm-icp = <0x2>;
539 ti,clkbuf-sel = <0x7>;
540 ti,otap-del-sel-legacy = <0x0>;
541 ti,otap-del-sel-mmc-hs = <0x0>;
542 ti,otap-del-sel-ddr52 = <0x5>;
543 ti,otap-del-sel-hs200 = <0x5>;
544 ti,itap-del-sel-legacy = <0xa>;
545 ti,itap-del-sel-mmc-hs = <0x1>;
551 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
556 ti,trm-icp = <0x2>;
557 ti,otap-del-sel-legacy = <0x8>;
558 ti,otap-del-sel-sd-hs = <0x0>;
559 ti,otap-del-sel-sdr12 = <0x0>;
560 ti,otap-del-sel-sdr25 = <0x0>;
561 ti,otap-del-sel-sdr50 = <0x8>;
562 ti,otap-del-sel-sdr104 = <0x7>;
563 ti,otap-del-sel-ddr50 = <0x4>;
564 ti,itap-del-sel-legacy = <0xa>;
565 ti,itap-del-sel-sd-hs = <0x1>;
566 ti,itap-del-sel-sdr12 = <0xa>;
567 ti,itap-del-sel-sdr25 = <0x1>;
568 ti,clkbuf-sel = <0x7>;
575 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
580 ti,trm-icp = <0x2>;
581 ti,otap-del-sel-legacy = <0x8>;
582 ti,otap-del-sel-sd-hs = <0x0>;
583 ti,otap-del-sel-sdr12 = <0x0>;
584 ti,otap-del-sel-sdr25 = <0x0>;
585 ti,otap-del-sel-sdr50 = <0x8>;
586 ti,otap-del-sel-sdr104 = <0x7>;
587 ti,otap-del-sel-ddr50 = <0x8>;
588 ti,itap-del-sel-legacy = <0xa>;
589 ti,itap-del-sel-sd-hs = <0xa>;
590 ti,itap-del-sel-sdr12 = <0xa>;
591 ti,itap-del-sel-sdr25 = <0x1>;
592 ti,clkbuf-sel = <0x7>;
598 reg = <0x00 0x0f900000 0x00 0x800>;
601 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
610 reg = <0x00 0x31000000 0x00 0x50000>;
611 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
612 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
623 reg = <0x00 0x0f910000 0x00 0x800>;
626 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
635 reg = <0x00 0x31100000 0x00 0x50000>;
636 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
637 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
648 reg = <0x00 0x0fc00000 0x00 0x70000>;
655 reg = <0x00 0x0fc40000 0x00 0x100>,
656 <0x05 0x00000000 0x01 0x00000000>;
660 cdns,trigger-address = <0x0>;
667 #size-cells = <0>;
676 reg = <0x00 0x08000000 0x00 0x200000>;
678 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
679 clocks = <&k3_clks 13 0>;
685 dmas = <&main_pktdma 0xc600 15>,
686 <&main_pktdma 0xc601 15>,
687 <&main_pktdma 0xc602 15>,
688 <&main_pktdma 0xc603 15>,
689 <&main_pktdma 0xc604 15>,
690 <&main_pktdma 0xc605 15>,
691 <&main_pktdma 0xc606 15>,
692 <&main_pktdma 0xc607 15>,
693 <&main_pktdma 0x4600 15>;
699 #size-cells = <0>;
707 ti,syscon-efuse = <&wkup_conf 0x200>;
721 reg = <0x00 0xf00 0x00 0x100>;
723 #size-cells = <0>;
724 clocks = <&k3_clks 13 0>;
732 reg = <0x00 0x3d000 0x00 0x400>;
744 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
745 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
746 <0x00 0x30206000 0x00 0x1000>, /* vid */
747 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
748 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
749 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
750 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
751 <0x00 0x30201000 0x00 0x1000>; /* common1 */
764 #size-cells = <0>;
770 reg = <0x00 0x2a000000 0x00 0x1000>;
776 reg = <0x00 0x29000000 0x00 0x200>;
787 reg = <0x00 0x23100000 0x00 0x100>;
789 clocks = <&k3_clks 51 0>;
797 reg = <0x00 0x23110000 0x00 0x100>;
799 clocks = <&k3_clks 52 0>;
807 reg = <0x00 0x23120000 0x00 0x100>;
809 clocks = <&k3_clks 53 0>;
816 reg = <0x00 0x20701000 0x00 0x200>,
817 <0x00 0x20708000 0x00 0x8000>;
825 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
831 reg = <0x00 0x0e000000 0x00 0x100>;
832 clocks = <&k3_clks 125 0>;
834 assigned-clocks = <&k3_clks 125 0>;
840 reg = <0x00 0x0e010000 0x00 0x100>;
841 clocks = <&k3_clks 126 0>;
843 assigned-clocks = <&k3_clks 126 0>;
849 reg = <0x00 0x0e020000 0x00 0x100>;
850 clocks = <&k3_clks 127 0>;
852 assigned-clocks = <&k3_clks 127 0>;
858 reg = <0x00 0x0e030000 0x00 0x100>;
859 clocks = <&k3_clks 128 0>;
861 assigned-clocks = <&k3_clks 128 0>;
867 reg = <0x00 0x0e0f0000 0x00 0x100>;
868 clocks = <&k3_clks 130 0>;
870 assigned-clocks = <&k3_clks 130 0>;
877 reg = <0x00 0x23000000 0x00 0x100>;
879 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
887 reg = <0x00 0x23010000 0x00 0x100>;
889 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
897 reg = <0x00 0x23020000 0x00 0x100>;
899 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
906 reg = <0x00 0x02b00000 0x00 0x2000>,
907 <0x00 0x02b08000 0x00 0x400>;
913 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
916 clocks = <&k3_clks 190 0>;
918 assigned-clocks = <&k3_clks 190 0>;
926 reg = <0x00 0x02b10000 0x00 0x2000>,
927 <0x00 0x02b18000 0x00 0x400>;
933 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
936 clocks = <&k3_clks 191 0>;
938 assigned-clocks = <&k3_clks 191 0>;
946 reg = <0x00 0x02b20000 0x00 0x2000>,
947 <0x00 0x02b28000 0x00 0x400>;
953 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
956 clocks = <&k3_clks 192 0>;
958 assigned-clocks = <&k3_clks 192 0>;