Lines Matching +full:0 +full:x20100000

21  * at91rm9200ek_config     -> boot from 0x0 in NOR Flash at CS0
22  * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
57 #define CONFIG_SYS_SDRAM_BASE		0x20000000
70 #define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
71 #define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
74 #define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
75 #define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
77 #define CONFIG_SYS_MCKR_VAL	0x00000202
80 #define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
81 #define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
82 #define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
83 #define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
84 #define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
86 #define CONFIG_SYS_SDRAM1	(CONFIG_SYS_SDRAM_BASE+0x80)
87 #define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
88 #define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
89 #define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
90 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
91 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
92 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
105 #define CONFIG_USART_ID		0/* ignored in arm */
121 #define CONFIG_SYS_FLASH_BASE		0x10000000