1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <32000>; 22 #clock-cells = <0>; 23 }; 24 25 xo: xo { 26 compatible = "fixed-clock"; 27 clock-frequency = <24000000>; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq6018_s2>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 next-level-cache = <&L2_0>; 54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 55 clock-names = "cpu"; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-supply = <&ipq6018_s2>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x2>; 65 next-level-cache = <&L2_0>; 66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu_opp_table>; 69 cpu-supply = <&ipq6018_s2>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x3>; 77 next-level-cache = <&L2_0>; 78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 79 clock-names = "cpu"; 80 operating-points-v2 = <&cpu_opp_table>; 81 cpu-supply = <&ipq6018_s2>; 82 }; 83 84 L2_0: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 cache-unified; 88 }; 89 }; 90 91 firmware { 92 scm { 93 compatible = "qcom,scm-ipq6018", "qcom,scm"; 94 qcom,dload-mode = <&tcsr 0x6100>; 95 }; 96 }; 97 98 cpu_opp_table: opp-table-cpu { 99 compatible = "operating-points-v2"; 100 opp-shared; 101 102 opp-864000000 { 103 opp-hz = /bits/ 64 <864000000>; 104 opp-microvolt = <725000>; 105 clock-latency-ns = <200000>; 106 }; 107 108 opp-1056000000 { 109 opp-hz = /bits/ 64 <1056000000>; 110 opp-microvolt = <787500>; 111 clock-latency-ns = <200000>; 112 }; 113 114 opp-1320000000 { 115 opp-hz = /bits/ 64 <1320000000>; 116 opp-microvolt = <862500>; 117 clock-latency-ns = <200000>; 118 }; 119 120 opp-1440000000 { 121 opp-hz = /bits/ 64 <1440000000>; 122 opp-microvolt = <925000>; 123 clock-latency-ns = <200000>; 124 }; 125 126 opp-1608000000 { 127 opp-hz = /bits/ 64 <1608000000>; 128 opp-microvolt = <987500>; 129 clock-latency-ns = <200000>; 130 }; 131 132 opp-1800000000 { 133 opp-hz = /bits/ 64 <1800000000>; 134 opp-microvolt = <1062500>; 135 clock-latency-ns = <200000>; 136 }; 137 }; 138 139 pmuv8: pmu { 140 compatible = "arm,cortex-a53-pmu"; 141 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 142 }; 143 144 psci: psci { 145 compatible = "arm,psci-1.0"; 146 method = "smc"; 147 }; 148 149 rpm: remoteproc { 150 compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc"; 151 152 glink-edge { 153 compatible = "qcom,glink-rpm"; 154 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 155 qcom,rpm-msg-ram = <&rpm_msg_ram>; 156 mboxes = <&apcs_glb 0>; 157 158 rpm_requests: rpm-requests { 159 compatible = "qcom,rpm-ipq6018"; 160 qcom,glink-channels = "rpm_requests"; 161 162 regulators { 163 compatible = "qcom,rpm-mp5496-regulators"; 164 165 ipq6018_s2: s2 { 166 regulator-min-microvolt = <725000>; 167 regulator-max-microvolt = <1062500>; 168 regulator-always-on; 169 }; 170 }; 171 }; 172 }; 173 }; 174 175 reserved-memory { 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges; 179 180 rpm_msg_ram: memory@60000 { 181 reg = <0x0 0x00060000 0x0 0x6000>; 182 no-map; 183 }; 184 185 bootloader@4a100000 { 186 reg = <0x0 0x4a100000 0x0 0x400000>; 187 no-map; 188 }; 189 190 sbl@4a500000 { 191 reg = <0x0 0x4a500000 0x0 0x100000>; 192 no-map; 193 }; 194 195 tz: memory@4a600000 { 196 reg = <0x0 0x4a600000 0x0 0x400000>; 197 no-map; 198 }; 199 200 smem_region: memory@4aa00000 { 201 reg = <0x0 0x4aa00000 0x0 0x100000>; 202 no-map; 203 }; 204 205 q6_region: memory@4ab00000 { 206 reg = <0x0 0x4ab00000 0x0 0x5500000>; 207 no-map; 208 }; 209 }; 210 211 smem { 212 compatible = "qcom,smem"; 213 memory-region = <&smem_region>; 214 hwlocks = <&tcsr_mutex 3>; 215 }; 216 217 soc: soc@0 { 218 #address-cells = <2>; 219 #size-cells = <2>; 220 ranges = <0 0 0 0 0x0 0xffffffff>; 221 dma-ranges; 222 compatible = "simple-bus"; 223 224 qusb_phy_1: qusb@59000 { 225 compatible = "qcom,ipq6018-qusb2-phy"; 226 reg = <0x0 0x00059000 0x0 0x180>; 227 #phy-cells = <0>; 228 229 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 230 <&xo>; 231 clock-names = "cfg_ahb", "ref"; 232 233 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 234 status = "disabled"; 235 }; 236 237 ssphy_0: ssphy@78000 { 238 compatible = "qcom,ipq6018-qmp-usb3-phy"; 239 reg = <0x0 0x00078000 0x0 0x1c4>; 240 #address-cells = <2>; 241 #size-cells = <2>; 242 ranges; 243 244 clocks = <&gcc GCC_USB0_AUX_CLK>, 245 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; 246 clock-names = "aux", "cfg_ahb", "ref"; 247 248 resets = <&gcc GCC_USB0_PHY_BCR>, 249 <&gcc GCC_USB3PHY_0_PHY_BCR>; 250 reset-names = "phy","common"; 251 status = "disabled"; 252 253 usb0_ssphy: phy@78200 { 254 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ 255 <0x0 0x00078400 0x0 0x200>, /* Rx */ 256 <0x0 0x00078800 0x0 0x1f8>, /* PCS */ 257 <0x0 0x00078600 0x0 0x044>; /* PCS misc */ 258 #phy-cells = <0>; 259 #clock-cells = <0>; 260 clocks = <&gcc GCC_USB0_PIPE_CLK>; 261 clock-names = "pipe0"; 262 clock-output-names = "gcc_usb0_pipe_clk_src"; 263 }; 264 }; 265 266 qusb_phy_0: qusb@79000 { 267 compatible = "qcom,ipq6018-qusb2-phy"; 268 reg = <0x0 0x00079000 0x0 0x180>; 269 #phy-cells = <0>; 270 271 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 272 <&xo>; 273 clock-names = "cfg_ahb", "ref"; 274 275 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 276 status = "disabled"; 277 }; 278 279 pcie_phy: phy@84000 { 280 compatible = "qcom,ipq6018-qmp-pcie-phy"; 281 reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ 282 status = "disabled"; 283 #address-cells = <2>; 284 #size-cells = <2>; 285 ranges; 286 287 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 288 <&gcc GCC_PCIE0_AHB_CLK>; 289 clock-names = "aux", "cfg_ahb"; 290 291 resets = <&gcc GCC_PCIE0_PHY_BCR>, 292 <&gcc GCC_PCIE0PHY_PHY_BCR>; 293 reset-names = "phy", 294 "common"; 295 296 pcie_phy0: phy@84200 { 297 reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ 298 <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ 299 <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ 300 <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ 301 #phy-cells = <0>; 302 303 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 304 clock-names = "pipe0"; 305 clock-output-names = "gcc_pcie0_pipe_clk_src"; 306 #clock-cells = <0>; 307 }; 308 }; 309 310 mdio: mdio@90000 { 311 #address-cells = <1>; 312 #size-cells = <0>; 313 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; 314 reg = <0x0 0x00090000 0x0 0x64>; 315 clocks = <&gcc GCC_MDIO_AHB_CLK>; 316 clock-names = "gcc_mdio_ahb_clk"; 317 status = "disabled"; 318 }; 319 320 qfprom: efuse@a4000 { 321 compatible = "qcom,ipq6018-qfprom", "qcom,qfprom"; 322 reg = <0x0 0x000a4000 0x0 0x2000>; 323 #address-cells = <1>; 324 #size-cells = <1>; 325 }; 326 327 prng: qrng@e3000 { 328 compatible = "qcom,prng-ee"; 329 reg = <0x0 0x000e3000 0x0 0x1000>; 330 clocks = <&gcc GCC_PRNG_AHB_CLK>; 331 clock-names = "core"; 332 }; 333 334 cryptobam: dma-controller@704000 { 335 compatible = "qcom,bam-v1.7.0"; 336 reg = <0x0 0x00704000 0x0 0x20000>; 337 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 339 clock-names = "bam_clk"; 340 #dma-cells = <1>; 341 qcom,ee = <1>; 342 qcom,controlled-remotely; 343 }; 344 345 crypto: crypto@73a000 { 346 compatible = "qcom,crypto-v5.1"; 347 reg = <0x0 0x0073a000 0x0 0x6000>; 348 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 349 <&gcc GCC_CRYPTO_AXI_CLK>, 350 <&gcc GCC_CRYPTO_CLK>; 351 clock-names = "iface", "bus", "core"; 352 dmas = <&cryptobam 2>, <&cryptobam 3>; 353 dma-names = "rx", "tx"; 354 }; 355 356 tlmm: pinctrl@1000000 { 357 compatible = "qcom,ipq6018-pinctrl"; 358 reg = <0x0 0x01000000 0x0 0x300000>; 359 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 360 gpio-controller; 361 #gpio-cells = <2>; 362 gpio-ranges = <&tlmm 0 0 80>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 366 serial_3_pins: serial3-state { 367 pins = "gpio44", "gpio45"; 368 function = "blsp2_uart"; 369 drive-strength = <8>; 370 bias-pull-down; 371 }; 372 373 qpic_pins: qpic-state { 374 pins = "gpio1", "gpio3", "gpio4", 375 "gpio5", "gpio6", "gpio7", 376 "gpio8", "gpio10", "gpio11", 377 "gpio12", "gpio13", "gpio14", 378 "gpio15", "gpio17"; 379 function = "qpic_pad"; 380 drive-strength = <8>; 381 bias-disable; 382 }; 383 }; 384 385 gcc: gcc@1800000 { 386 compatible = "qcom,gcc-ipq6018"; 387 reg = <0x0 0x01800000 0x0 0x80000>; 388 clocks = <&xo>, <&sleep_clk>; 389 clock-names = "xo", "sleep_clk"; 390 #clock-cells = <1>; 391 #reset-cells = <1>; 392 }; 393 394 tcsr_mutex: hwlock@1905000 { 395 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; 396 reg = <0x0 0x01905000 0x0 0x20000>; 397 #hwlock-cells = <1>; 398 }; 399 400 tcsr: syscon@1937000 { 401 compatible = "qcom,tcsr-ipq6018", "syscon"; 402 reg = <0x0 0x01937000 0x0 0x21000>; 403 }; 404 405 usb2: usb@70f8800 { 406 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 407 reg = <0x0 0x070f8800 0x0 0x400>; 408 #address-cells = <2>; 409 #size-cells = <2>; 410 ranges; 411 clocks = <&gcc GCC_USB1_MASTER_CLK>, 412 <&gcc GCC_USB1_SLEEP_CLK>, 413 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 414 clock-names = "core", 415 "sleep", 416 "mock_utmi"; 417 418 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 419 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 420 assigned-clock-rates = <133330000>, 421 <24000000>; 422 resets = <&gcc GCC_USB1_BCR>; 423 status = "disabled"; 424 425 dwc_1: usb@7000000 { 426 compatible = "snps,dwc3"; 427 reg = <0x0 0x07000000 0x0 0xcd00>; 428 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 429 phys = <&qusb_phy_1>; 430 phy-names = "usb2-phy"; 431 tx-fifo-resize; 432 snps,is-utmi-l1-suspend; 433 snps,hird-threshold = /bits/ 8 <0x0>; 434 snps,dis_u2_susphy_quirk; 435 snps,dis_u3_susphy_quirk; 436 dr_mode = "host"; 437 }; 438 }; 439 440 blsp_dma: dma-controller@7884000 { 441 compatible = "qcom,bam-v1.7.0"; 442 reg = <0x0 0x07884000 0x0 0x2b000>; 443 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 445 clock-names = "bam_clk"; 446 #dma-cells = <1>; 447 qcom,ee = <0>; 448 }; 449 450 blsp1_uart3: serial@78b1000 { 451 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 452 reg = <0x0 0x078b1000 0x0 0x200>; 453 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 455 <&gcc GCC_BLSP1_AHB_CLK>; 456 clock-names = "core", "iface"; 457 status = "disabled"; 458 }; 459 460 blsp1_spi1: spi@78b5000 { 461 compatible = "qcom,spi-qup-v2.2.1"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 reg = <0x0 0x078b5000 0x0 0x600>; 465 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 467 <&gcc GCC_BLSP1_AHB_CLK>; 468 clock-names = "core", "iface"; 469 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 470 dma-names = "tx", "rx"; 471 status = "disabled"; 472 }; 473 474 blsp1_spi2: spi@78b6000 { 475 compatible = "qcom,spi-qup-v2.2.1"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 reg = <0x0 0x078b6000 0x0 0x600>; 479 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 481 <&gcc GCC_BLSP1_AHB_CLK>; 482 clock-names = "core", "iface"; 483 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 484 dma-names = "tx", "rx"; 485 status = "disabled"; 486 }; 487 488 blsp1_i2c2: i2c@78b6000 { 489 compatible = "qcom,i2c-qup-v2.2.1"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <0x0 0x078b6000 0x0 0x600>; 493 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 495 <&gcc GCC_BLSP1_AHB_CLK>; 496 clock-names = "core", "iface"; 497 clock-frequency = <400000>; 498 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 499 dma-names = "tx", "rx"; 500 status = "disabled"; 501 }; 502 503 blsp1_i2c3: i2c@78b7000 { 504 compatible = "qcom,i2c-qup-v2.2.1"; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 reg = <0x0 0x078b7000 0x0 0x600>; 508 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 510 <&gcc GCC_BLSP1_AHB_CLK>; 511 clock-names = "core", "iface"; 512 clock-frequency = <400000>; 513 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 514 dma-names = "tx", "rx"; 515 status = "disabled"; 516 }; 517 518 qpic_bam: dma-controller@7984000 { 519 compatible = "qcom,bam-v1.7.0"; 520 reg = <0x0 0x07984000 0x0 0x1a000>; 521 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&gcc GCC_QPIC_AHB_CLK>; 523 clock-names = "bam_clk"; 524 #dma-cells = <1>; 525 qcom,ee = <0>; 526 status = "disabled"; 527 }; 528 529 qpic_nand: nand-controller@79b0000 { 530 compatible = "qcom,ipq6018-nand"; 531 reg = <0x0 0x079b0000 0x0 0x10000>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 clocks = <&gcc GCC_QPIC_CLK>, 535 <&gcc GCC_QPIC_AHB_CLK>; 536 clock-names = "core", "aon"; 537 538 dmas = <&qpic_bam 0>, 539 <&qpic_bam 1>, 540 <&qpic_bam 2>; 541 dma-names = "tx", "rx", "cmd"; 542 pinctrl-0 = <&qpic_pins>; 543 pinctrl-names = "default"; 544 status = "disabled"; 545 }; 546 547 usb3: usb@8af8800 { 548 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 549 reg = <0x0 0x08af8800 0x0 0x400>; 550 #address-cells = <2>; 551 #size-cells = <2>; 552 ranges; 553 554 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 555 <&gcc GCC_USB0_MASTER_CLK>, 556 <&gcc GCC_USB0_SLEEP_CLK>, 557 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 558 clock-names = "cfg_noc", 559 "core", 560 "sleep", 561 "mock_utmi"; 562 563 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 564 <&gcc GCC_USB0_MASTER_CLK>, 565 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 566 assigned-clock-rates = <133330000>, 567 <133330000>, 568 <24000000>; 569 570 resets = <&gcc GCC_USB0_BCR>; 571 status = "disabled"; 572 573 dwc_0: usb@8a00000 { 574 compatible = "snps,dwc3"; 575 reg = <0x0 0x08a00000 0x0 0xcd00>; 576 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 577 phys = <&qusb_phy_0>, <&usb0_ssphy>; 578 phy-names = "usb2-phy", "usb3-phy"; 579 clocks = <&xo>; 580 clock-names = "ref"; 581 tx-fifo-resize; 582 snps,is-utmi-l1-suspend; 583 snps,hird-threshold = /bits/ 8 <0x0>; 584 snps,dis_u2_susphy_quirk; 585 snps,dis_u3_susphy_quirk; 586 dr_mode = "host"; 587 }; 588 }; 589 590 intc: interrupt-controller@b000000 { 591 compatible = "qcom,msm-qgic2"; 592 #address-cells = <2>; 593 #size-cells = <2>; 594 interrupt-controller; 595 #interrupt-cells = <3>; 596 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 597 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 598 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 599 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 600 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 601 ranges = <0 0 0 0xb00a000 0 0xffd>; 602 603 v2m@0 { 604 compatible = "arm,gic-v2m-frame"; 605 msi-controller; 606 reg = <0x0 0x0 0x0 0xffd>; 607 }; 608 }; 609 610 watchdog@b017000 { 611 compatible = "qcom,kpss-wdt"; 612 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 613 reg = <0x0 0x0b017000 0x0 0x40>; 614 clocks = <&sleep_clk>; 615 timeout-sec = <10>; 616 }; 617 618 apcs_glb: mailbox@b111000 { 619 compatible = "qcom,ipq6018-apcs-apps-global"; 620 reg = <0x0 0x0b111000 0x0 0x1000>; 621 #clock-cells = <1>; 622 clocks = <&a53pll>, <&xo>; 623 clock-names = "pll", "xo"; 624 #mbox-cells = <1>; 625 }; 626 627 a53pll: clock@b116000 { 628 compatible = "qcom,ipq6018-a53pll"; 629 reg = <0x0 0x0b116000 0x0 0x40>; 630 #clock-cells = <0>; 631 clocks = <&xo>; 632 clock-names = "xo"; 633 }; 634 635 timer@b120000 { 636 #address-cells = <1>; 637 #size-cells = <1>; 638 ranges = <0 0 0 0x10000000>; 639 compatible = "arm,armv7-timer-mem"; 640 reg = <0x0 0x0b120000 0x0 0x1000>; 641 642 frame@b120000 { 643 frame-number = <0>; 644 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 646 reg = <0x0b121000 0x1000>, 647 <0x0b122000 0x1000>; 648 }; 649 650 frame@b123000 { 651 frame-number = <1>; 652 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 653 reg = <0x0b123000 0x1000>; 654 status = "disabled"; 655 }; 656 657 frame@b124000 { 658 frame-number = <2>; 659 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 660 reg = <0x0b124000 0x1000>; 661 status = "disabled"; 662 }; 663 664 frame@b125000 { 665 frame-number = <3>; 666 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 667 reg = <0x0b125000 0x1000>; 668 status = "disabled"; 669 }; 670 671 frame@b126000 { 672 frame-number = <4>; 673 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 674 reg = <0x0b126000 0x1000>; 675 status = "disabled"; 676 }; 677 678 frame@b127000 { 679 frame-number = <5>; 680 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 681 reg = <0x0b127000 0x1000>; 682 status = "disabled"; 683 }; 684 685 frame@b128000 { 686 frame-number = <6>; 687 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 688 reg = <0x0b128000 0x1000>; 689 status = "disabled"; 690 }; 691 }; 692 693 q6v5_wcss: remoteproc@cd00000 { 694 compatible = "qcom,ipq6018-wcss-pil"; 695 reg = <0x0 0x0cd00000 0x0 0x4040>, 696 <0x0 0x004ab000 0x0 0x20>; 697 reg-names = "qdsp6", 698 "rmb"; 699 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 700 <&wcss_smp2p_in 0 0>, 701 <&wcss_smp2p_in 1 0>, 702 <&wcss_smp2p_in 2 0>, 703 <&wcss_smp2p_in 3 0>; 704 interrupt-names = "wdog", 705 "fatal", 706 "ready", 707 "handover", 708 "stop-ack"; 709 710 resets = <&gcc GCC_WCSSAON_RESET>, 711 <&gcc GCC_WCSS_BCR>, 712 <&gcc GCC_WCSS_Q6_BCR>; 713 714 reset-names = "wcss_aon_reset", 715 "wcss_reset", 716 "wcss_q6_reset"; 717 718 clocks = <&gcc GCC_PRNG_AHB_CLK>; 719 clock-names = "prng"; 720 721 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; 722 723 qcom,smem-states = <&wcss_smp2p_out 0>, 724 <&wcss_smp2p_out 1>; 725 qcom,smem-state-names = "shutdown", 726 "stop"; 727 728 memory-region = <&q6_region>; 729 730 glink-edge { 731 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 732 label = "rtr"; 733 qcom,remote-pid = <1>; 734 mboxes = <&apcs_glb 8>; 735 736 qrtr_requests { 737 qcom,glink-channels = "IPCRTR"; 738 }; 739 }; 740 }; 741 742 pcie0: pci@20000000 { 743 compatible = "qcom,pcie-ipq6018"; 744 reg = <0x0 0x20000000 0x0 0xf1d>, 745 <0x0 0x20000f20 0x0 0xa8>, 746 <0x0 0x20001000 0x0 0x1000>, 747 <0x0 0x80000 0x0 0x4000>, 748 <0x0 0x20100000 0x0 0x1000>; 749 reg-names = "dbi", "elbi", "atu", "parf", "config"; 750 751 device_type = "pci"; 752 linux,pci-domain = <0>; 753 bus-range = <0x00 0xff>; 754 num-lanes = <1>; 755 max-link-speed = <3>; 756 #address-cells = <3>; 757 #size-cells = <2>; 758 759 phys = <&pcie_phy0>; 760 phy-names = "pciephy"; 761 762 ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, 763 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; 764 765 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 766 interrupt-names = "msi"; 767 768 #interrupt-cells = <1>; 769 interrupt-map-mask = <0 0 0 0x7>; 770 interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 771 <0 0 0 2 &intc 0 0 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 772 <0 0 0 3 &intc 0 0 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 773 <0 0 0 4 &intc 0 0 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 774 775 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 776 <&gcc GCC_PCIE0_AXI_M_CLK>, 777 <&gcc GCC_PCIE0_AXI_S_CLK>, 778 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 779 <&gcc PCIE0_RCHNG_CLK>; 780 clock-names = "iface", 781 "axi_m", 782 "axi_s", 783 "axi_bridge", 784 "rchng"; 785 786 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 787 <&gcc GCC_PCIE0_SLEEP_ARES>, 788 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 789 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 790 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 791 <&gcc GCC_PCIE0_AHB_ARES>, 792 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 793 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 794 reset-names = "pipe", 795 "sleep", 796 "sticky", 797 "axi_m", 798 "axi_s", 799 "ahb", 800 "axi_m_sticky", 801 "axi_s_sticky"; 802 803 status = "disabled"; 804 }; 805 }; 806 807 timer { 808 compatible = "arm,armv8-timer"; 809 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 810 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 811 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 812 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 813 }; 814 815 wcss: wcss-smp2p { 816 compatible = "qcom,smp2p"; 817 qcom,smem = <435>, <428>; 818 819 interrupt-parent = <&intc>; 820 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 821 822 mboxes = <&apcs_glb 9>; 823 824 qcom,local-pid = <0>; 825 qcom,remote-pid = <1>; 826 827 wcss_smp2p_out: master-kernel { 828 qcom,entry-name = "master-kernel"; 829 #qcom,smem-state-cells = <1>; 830 }; 831 832 wcss_smp2p_in: slave-kernel { 833 qcom,entry-name = "slave-kernel"; 834 interrupt-controller; 835 #interrupt-cells = <2>; 836 }; 837 }; 838}; 839