Home
last modified time | relevance | path

Searched +full:0 +full:x1f (Results 1 – 25 of 1074) sorted by relevance

12345678910>>...43

/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
H A Dbnx2x_self_test.c6 #define NA 0xCD
8 #define IDLE_CHK_E1 0x01
9 #define IDLE_CHK_E1H 0x02
10 #define IDLE_CHK_E2 0x04
11 #define IDLE_CHK_E3A0 0x08
12 #define IDLE_CHK_E3B0 0x10
118 /*line 2*/{(0x3), 1, 0x2114,
119 NA, 1, 0, pand_neq,
121 "PCIE: ucorr_err_status is not 0",
122 {NA, NA, 0x0FF010, 0, NA, NA} },
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dsys_proto.h39 { 0x00, 0x0f, "USB" },
40 { 0x01, 0x1f, "I2C, master" },
41 { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
42 { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
43 { 0x04, 0x1f, "NAND" },
44 { 0x06, 0x1f, "JTAG" },
45 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
46 { 0x09, 0x1f, "SSP SD/MMC #0" },
47 { 0x0a, 0x1f, "SSP SD/MMC #1" },
48 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
[all …]
/openbmc/linux/drivers/media/platform/verisilicon/
H A Dhantro_g2_regs.h22 #define G2_REG_VERSION G2_SWREG(0)
28 #define G2_REG_INTERRUPT_DEC_E BIT(0)
30 #define HEVC_DEC_MODE 0xc
31 #define VP9_DEC_MODE 0xd
33 #define BUS_WIDTH_32 0
38 #define g2_strm_swap G2_DEC_REG(2, 28, 0xf)
39 #define g2_strm_swap_old G2_DEC_REG(2, 27, 0x1f)
40 #define g2_pic_swap G2_DEC_REG(2, 22, 0x1f)
41 #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf)
42 #define g2_dirmv_swap_old G2_DEC_REG(2, 17, 0x1f)
[all …]
H A Dhantro_g1_regs.h15 #define G1_REG_INTERRUPT 0x004
26 #define G1_REG_INTERRUPT_DEC_E BIT(0)
27 #define G1_REG_CONFIG 0x008
28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24)
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11)
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5)
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0)
46 #define G1_REG_DEC_CTRL0 0x00c
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28)
70 #define G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0)
[all …]
H A Drockchip_vpu2_regs.h13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-leadtek-ltk050h3146w.c42 { 0x22, 0x0A }, /* BGR SS GS */
43 { 0x31, 0x00 }, /* column inversion */
44 { 0x53, 0xA2 }, /* VCOM1 */
45 { 0x55, 0xA2 }, /* VCOM2 */
46 { 0x50, 0x81 }, /* VREG1OUT=5V */
47 { 0x51, 0x85 }, /* VREG2OUT=-5V */
48 { 0x62, 0x0D }, /* EQT Time setting */
53 { 0xA0, 0x00 },
54 { 0xA1, 0x1A },
55 { 0xA2, 0x28 },
[all …]
H A Dpanel-samsung-s6e8aa0.c34 #define PANELCTL_SS_1_800 (0 << 5)
41 #define PANELCTL_CLK1_000 (0 << 3)
43 #define PANELCTL_CLK2_CON_MASK (7 << 0)
44 #define PANELCTL_CLK2_000 (0 << 0)
45 #define PANELCTL_CLK2_001 (1 << 0)
48 #define PANELCTL_INT1_000 (0 << 3)
50 #define PANELCTL_INT2_CON_MASK (7 << 0)
51 #define PANELCTL_INT2_000 (0 << 0)
52 #define PANELCTL_INT2_001 (1 << 0)
55 #define PANELCTL_BICTL_000 (0 << 3)
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_engine.c10 #define PATTERN_1 0x55555555
11 #define PATTERN_2 0xaaaaaaaa
61 0xffff
72 0xffff
114 {0x7, 0x7, 2, 0x7, 0x00000, 8}, /* PATTERN_PBS1 */
115 {0x7, 0x7, 2, 0x7, 0x00080, 8}, /* PATTERN_PBS2 */
116 {0x7, 0x7, 2, 0x7, 0x00100, 8}, /* PATTERN_PBS3 */
117 {0x7, 0x7, 2, 0x7, 0x00030, 8}, /* PATTERN_TEST */
118 {0x7, 0x7, 2, 0x7, 0x00100, 8}, /* PATTERN_RL */
119 {0x7, 0x7, 2, 0x7, 0x00100, 8}, /* PATTERN_RL2 */
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_aic.c25 0, 3, 9, 15, 21, 27
67 for (i = index - 1; i >= 0; i--) { in ar9003_aic_find_valid()
73 if ((i >= ATH_AIC_MAX_BT_CHANNEL) || (i < 0)) in ar9003_aic_find_valid()
80 * type 0: aic_lin_table, 1: com_att_db_table
86 if (type == 0) { in ar9003_aic_find_index()
87 for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { in ar9003_aic_find_index()
92 for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) { in ar9003_aic_find_index()
111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); in ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); in ar9003_aic_gain_table()
115 aic_atten_word[0] = (0x1 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
[all …]
/openbmc/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/openbmc/linux/drivers/media/platform/ti/vpe/
H A Dvpe_regs.h16 #define VPE_PID 0x0000
17 #define VPE_PID_MINOR_MASK 0x3f
18 #define VPE_PID_MINOR_SHIFT 0
19 #define VPE_PID_CUSTOM_MASK 0x03
21 #define VPE_PID_MAJOR_MASK 0x07
23 #define VPE_PID_RTL_MASK 0x1f
25 #define VPE_PID_FUNC_MASK 0xfff
27 #define VPE_PID_SCHEME_MASK 0x03
30 #define VPE_SYSCONFIG 0x0010
31 #define VPE_SYSCONFIG_IDLE_MASK 0x03
[all …]
/openbmc/linux/sound/soc/amd/include/
H A Dacp_2_2_sh_mask.h27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
[all …]
/openbmc/linux/arch/powerpc/math-emu/
H A Dmath.c29 void *op4) { return 0; }
80 #define OP31 0x1f /* 31 */
81 #define LFS 0x30 /* 48 */
82 #define LFSU 0x31 /* 49 */
83 #define LFD 0x32 /* 50 */
84 #define LFDU 0x33 /* 51 */
85 #define STFS 0x34 /* 52 */
86 #define STFSU 0x35 /* 53 */
87 #define STFD 0x36 /* 54 */
88 #define STFDU 0x37 /* 55 */
[all …]
/openbmc/linux/sound/soc/codecs/
H A Des8326.c48 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9550, 50, 0);
49 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9550, 50, 0);
50 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_analog_pga_tlv, 0, 300, 0);
51 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_pga_tlv, 0, 600, 0);
52 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(softramp_rate, 0, 100, 0);
53 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_target_tlv, -3200, 200, 0);
54 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_recovery_tlv, -125, 250, 0);
86 SOC_SINGLE_TLV("DAC Playback Volume", ES8326_DAC_VOL, 0, 0xbf, 0, dac_vol_tlv),
88 SOC_SINGLE_TLV("DAC Ramp Rate", ES8326_DAC_RAMPRATE, 0, 0x0f, 0, softramp_rate),
89 SOC_SINGLE_TLV("DRC Recovery Level", ES8326_DRC_RECOVERY, 0, 4, 0, drc_recovery_tlv),
[all …]
/openbmc/linux/drivers/net/phy/
H A Dvitesse.c15 #define MII_VSC82X4_EXT_PAGE_16E 0x10
16 #define MII_VSC82X4_EXT_PAGE_17E 0x11
17 #define MII_VSC82X4_EXT_PAGE_18E 0x12
20 #define MII_VSC8244_EXT_CON1 0x17
21 #define MII_VSC8244_EXTCON1_INIT 0x0000
22 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
23 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
24 #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
25 #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
28 #define MII_VSC8244_IMASK 0x19
[all …]
/openbmc/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h6 #define DE_STATE1 0x100054
7 #define DE_STATE1_DE_ABORT BIT(0)
9 #define DE_STATE2 0x100058
14 #define SYSTEM_CTRL 0x000000
15 #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30)
16 #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30)
17 #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30)
18 #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30)
19 #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30)
35 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4)
[all …]
/openbmc/u-boot/include/
H A Dmsc01.h14 #define MSC01_BIU_IP1BAS1L_OFS 0x0208
15 #define MSC01_BIU_IP1MSK1L_OFS 0x0218
16 #define MSC01_BIU_IP1BAS2L_OFS 0x0248
17 #define MSC01_BIU_IP1MSK2L_OFS 0x0258
18 #define MSC01_BIU_IP2BAS1L_OFS 0x0288
19 #define MSC01_BIU_IP2MSK1L_OFS 0x0298
20 #define MSC01_BIU_IP2BAS2L_OFS 0x02c8
21 #define MSC01_BIU_IP2MSK2L_OFS 0x02d8
22 #define MSC01_BIU_IP3BAS1L_OFS 0x0308
23 #define MSC01_BIU_IP3MSK1L_OFS 0x0318
[all …]
/openbmc/u-boot/board/freescale/ls1043aqds/
H A Dddr.h31 * memory controller 0
36 {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
37 {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
38 {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,},
39 {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
40 {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
42 {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
43 {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
44 {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
45 {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
[all …]
/openbmc/u-boot/board/freescale/ls1021aqds/
H A Dddr.h31 * memory controller 0
36 {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
37 {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
38 {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,},
39 {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
40 {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
42 {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
43 {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
44 {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
45 {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/athub/
H A Dathub_2_0_0_sh_mask.h27 …S_CNTL__DISABLE_ATC__SHIFT 0x0
28 …S_CNTL__DISABLE_PRI__SHIFT 0x1
29 …S_CNTL__DISABLE_PASID__SHIFT 0x2
30 …S_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
31 …_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
32 …_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
33 …_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
34 …DISABLE_ATC_MASK 0x00000001L
35 …DISABLE_PRI_MASK 0x00000002L
36 …DISABLE_PASID_MASK 0x00000004L
[all …]
/openbmc/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_masks.h15 ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
16 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
17 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))
20 ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
21 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
22 (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
23 (0x1 << PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT))
26 (0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT)
29 ((0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT) | \
30 (0x1 << PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT))
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rv1108.h51 check_member(rv1108_cru, emmc_con[1], 0x01ec);
63 FBDIV_MASK = 0xfff,
64 FBDIV_SHIFT = 0,
71 REFDIV_MASK = 0x3f,
72 REFDIV_SHIFT = 0,
77 FRACDIV_MASK = 0xffffff,
78 FRACDIV_SHIFT = 0,
83 WORK_MODE_SLOW = 0,
88 GLOBAL_POWER_DOWN_SHIFT = 0,
91 GLOBAL_POWER_UP = 0,
[all …]
/openbmc/linux/drivers/infiniband/hw/qib/
H A Dqib_7322_regs.h35 #define QIB_7322_Revision_OFFS 0x0
36 #define QIB_7322_Revision_DEF 0x0000000002010601
37 #define QIB_7322_Revision_R_Simulator_LSB 0x3F
38 #define QIB_7322_Revision_R_Simulator_MSB 0x3F
39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7322_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7322_Revision_R_Emulation_MSB 0x3E
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
43 #define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28
44 #define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D
[all …]
/openbmc/linux/drivers/video/fbdev/sis/
H A Doem300.h55 {0x08,0x08,0x08,0x08},
56 {0x08,0x08,0x08,0x08},
57 {0x08,0x08,0x08,0x08},
58 {0x2c,0x2c,0x2c,0x2c},
59 {0x08,0x08,0x08,0x08},
60 {0x08,0x08,0x08,0x08},
61 {0x08,0x08,0x08,0x08},
62 {0x20,0x20,0x20,0x20}
67 {0x20,0x20,0x20,0x20},
68 {0x20,0x20,0x20,0x20},
[all …]

12345678910>>...43