1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2baf37f06SPaul Burton /* 3baf37f06SPaul Burton * Copyright (C) 2013 Imagination Technologies 4c5bf161fSPaul Burton * Author: Paul Burton <paul.burton@mips.com> 5baf37f06SPaul Burton */ 6baf37f06SPaul Burton 7baf37f06SPaul Burton #ifndef __MSC01_H__ 8baf37f06SPaul Burton #define __MSC01_H__ 9baf37f06SPaul Burton 10baf37f06SPaul Burton /* 11baf37f06SPaul Burton * Bus Interface Unit 12baf37f06SPaul Burton */ 13baf37f06SPaul Burton 14baf37f06SPaul Burton #define MSC01_BIU_IP1BAS1L_OFS 0x0208 15baf37f06SPaul Burton #define MSC01_BIU_IP1MSK1L_OFS 0x0218 16baf37f06SPaul Burton #define MSC01_BIU_IP1BAS2L_OFS 0x0248 17baf37f06SPaul Burton #define MSC01_BIU_IP1MSK2L_OFS 0x0258 18baf37f06SPaul Burton #define MSC01_BIU_IP2BAS1L_OFS 0x0288 19baf37f06SPaul Burton #define MSC01_BIU_IP2MSK1L_OFS 0x0298 20baf37f06SPaul Burton #define MSC01_BIU_IP2BAS2L_OFS 0x02c8 21baf37f06SPaul Burton #define MSC01_BIU_IP2MSK2L_OFS 0x02d8 22baf37f06SPaul Burton #define MSC01_BIU_IP3BAS1L_OFS 0x0308 23baf37f06SPaul Burton #define MSC01_BIU_IP3MSK1L_OFS 0x0318 24baf37f06SPaul Burton #define MSC01_BIU_IP3BAS2L_OFS 0x0348 25baf37f06SPaul Burton #define MSC01_BIU_IP3MSK2L_OFS 0x0358 26baf37f06SPaul Burton #define MSC01_BIU_MCBAS1L_OFS 0x0388 27baf37f06SPaul Burton #define MSC01_BIU_MCMSK1L_OFS 0x0398 28baf37f06SPaul Burton #define MSC01_BIU_MCBAS2L_OFS 0x03c8 29baf37f06SPaul Burton #define MSC01_BIU_MCMSK2L_OFS 0x03d8 30baf37f06SPaul Burton 31baf37f06SPaul Burton /* 32baf37f06SPaul Burton * PCI Bridge 33baf37f06SPaul Burton */ 34baf37f06SPaul Burton 35baf37f06SPaul Burton #define MSC01_PCI_SC2PMBASL_OFS 0x0208 36baf37f06SPaul Burton #define MSC01_PCI_SC2PMMSKL_OFS 0x0218 37baf37f06SPaul Burton #define MSC01_PCI_SC2PMMAPL_OFS 0x0228 38baf37f06SPaul Burton #define MSC01_PCI_SC2PIOBASL_OFS 0x0248 39baf37f06SPaul Burton #define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 40baf37f06SPaul Burton #define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 41baf37f06SPaul Burton #define MSC01_PCI_P2SCMSKL_OFS 0x0308 42baf37f06SPaul Burton #define MSC01_PCI_P2SCMAPL_OFS 0x0318 43baf37f06SPaul Burton #define MSC01_PCI_INTSTAT_OFS 0x0608 44baf37f06SPaul Burton #define MSC01_PCI_CFGADDR_OFS 0x0610 45baf37f06SPaul Burton #define MSC01_PCI_CFGDATA_OFS 0x0618 46baf37f06SPaul Burton #define MSC01_PCI_HEAD0_OFS 0x2000 47baf37f06SPaul Burton #define MSC01_PCI_HEAD1_OFS 0x2008 48baf37f06SPaul Burton #define MSC01_PCI_HEAD2_OFS 0x2010 49baf37f06SPaul Burton #define MSC01_PCI_HEAD3_OFS 0x2018 50baf37f06SPaul Burton #define MSC01_PCI_HEAD4_OFS 0x2020 51baf37f06SPaul Burton #define MSC01_PCI_HEAD5_OFS 0x2028 52baf37f06SPaul Burton #define MSC01_PCI_HEAD6_OFS 0x2030 53baf37f06SPaul Burton #define MSC01_PCI_HEAD7_OFS 0x2038 54baf37f06SPaul Burton #define MSC01_PCI_HEAD8_OFS 0x2040 55baf37f06SPaul Burton #define MSC01_PCI_HEAD9_OFS 0x2048 56baf37f06SPaul Burton #define MSC01_PCI_HEAD10_OFS 0x2050 57baf37f06SPaul Burton #define MSC01_PCI_HEAD11_OFS 0x2058 58baf37f06SPaul Burton #define MSC01_PCI_HEAD12_OFS 0x2060 59baf37f06SPaul Burton #define MSC01_PCI_HEAD13_OFS 0x2068 60baf37f06SPaul Burton #define MSC01_PCI_HEAD14_OFS 0x2070 61baf37f06SPaul Burton #define MSC01_PCI_HEAD15_OFS 0x2078 62baf37f06SPaul Burton #define MSC01_PCI_BAR0_OFS 0x2220 63baf37f06SPaul Burton #define MSC01_PCI_CFG_OFS 0x2380 64baf37f06SPaul Burton #define MSC01_PCI_SWAP_OFS 0x2388 65baf37f06SPaul Burton 66baf37f06SPaul Burton #define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 67baf37f06SPaul Burton #define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 68baf37f06SPaul Burton 69baf37f06SPaul Burton #define MSC01_PCI_INTSTAT_TA_SHF 6 70baf37f06SPaul Burton #define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF) 71baf37f06SPaul Burton #define MSC01_PCI_INTSTAT_MA_SHF 7 72baf37f06SPaul Burton #define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF) 73baf37f06SPaul Burton 74baf37f06SPaul Burton #define MSC01_PCI_CFGADDR_BNUM_SHF 16 75baf37f06SPaul Burton #define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF) 76baf37f06SPaul Burton #define MSC01_PCI_CFGADDR_DNUM_SHF 11 77baf37f06SPaul Burton #define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF) 78baf37f06SPaul Burton #define MSC01_PCI_CFGADDR_FNUM_SHF 8 79baf37f06SPaul Burton #define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF) 80baf37f06SPaul Burton #define MSC01_PCI_CFGADDR_RNUM_SHF 2 81baf37f06SPaul Burton #define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF) 82baf37f06SPaul Burton 83baf37f06SPaul Burton #define MSC01_PCI_HEAD0_VENDORID_SHF 0 84baf37f06SPaul Burton #define MSC01_PCI_HEAD0_DEVICEID_SHF 16 85baf37f06SPaul Burton 86baf37f06SPaul Burton #define MSC01_PCI_HEAD2_REV_SHF 0 87baf37f06SPaul Burton #define MSC01_PCI_HEAD2_CLASS_SHF 16 88baf37f06SPaul Burton 89baf37f06SPaul Burton #define MSC01_PCI_CFG_EN_SHF 15 90baf37f06SPaul Burton #define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF) 91baf37f06SPaul Burton #define MSC01_PCI_CFG_G_SHF 16 92baf37f06SPaul Burton #define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF) 93baf37f06SPaul Burton #define MSC01_PCI_CFG_RA_SHF 17 94baf37f06SPaul Burton #define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF) 95baf37f06SPaul Burton 96baf37f06SPaul Burton #define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0 97baf37f06SPaul Burton #define MSC01_PCI_SWAP_IO_BSWAP_SHF 18 98baf37f06SPaul Burton 99baf37f06SPaul Burton /* 100baf37f06SPaul Burton * Peripheral Bus Controller 101baf37f06SPaul Burton */ 102baf37f06SPaul Burton 103baf37f06SPaul Burton #define MSC01_PBC_CLKCFG_OFS 0x0100 104baf37f06SPaul Burton #define MSC01_PBC_CS0CFG_OFS 0x0400 105baf37f06SPaul Burton #define MSC01_PBC_CS0TIM_OFS 0x0500 106baf37f06SPaul Burton #define MSC01_PBC_CS0RW_OFS 0x0600 107baf37f06SPaul Burton 108baf37f06SPaul Burton #define MSC01_PBC_CLKCFG_SHF 0 109baf37f06SPaul Burton #define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF) 110baf37f06SPaul Burton 111baf37f06SPaul Burton #define MSC01_PBC_CS0CFG_WS_SHF 0 112baf37f06SPaul Burton #define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF) 113baf37f06SPaul Burton #define MSC01_PBC_CS0CFG_WSIDLE_SHF 8 114baf37f06SPaul Burton #define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF) 115baf37f06SPaul Burton #define MSC01_PBC_CS0CFG_DTYP_SHF 16 116baf37f06SPaul Burton #define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF) 117baf37f06SPaul Burton #define MSC01_PBC_CS0CFG_ADM_SHF 20 118baf37f06SPaul Burton #define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF) 119baf37f06SPaul Burton 120baf37f06SPaul Burton #define MSC01_PBC_CS0TIM_CAT_SHF 0 121baf37f06SPaul Burton #define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF) 122baf37f06SPaul Burton #define MSC01_PBC_CS0TIM_CDT_SHF 8 123baf37f06SPaul Burton #define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF) 124baf37f06SPaul Burton 125baf37f06SPaul Burton #define MSC01_PBC_CS0RW_WAT_SHF 0 126baf37f06SPaul Burton #define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF) 127baf37f06SPaul Burton #define MSC01_PBC_CS0RW_WDT_SHF 8 128baf37f06SPaul Burton #define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF) 129baf37f06SPaul Burton #define MSC01_PBC_CS0RW_RAT_SHF 16 130baf37f06SPaul Burton #define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF) 131baf37f06SPaul Burton #define MSC01_PBC_CS0RW_RDT_SHF 24 132baf37f06SPaul Burton #define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF) 133baf37f06SPaul Burton 134baf37f06SPaul Burton #endif /* __MSC01_H__ */ 135