Lines Matching +full:0 +full:x1f
39 { 0x00, 0x0f, "USB" },
40 { 0x01, 0x1f, "I2C, master" },
41 { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
42 { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
43 { 0x04, 0x1f, "NAND" },
44 { 0x06, 0x1f, "JTAG" },
45 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
46 { 0x09, 0x1f, "SSP SD/MMC #0" },
47 { 0x0a, 0x1f, "SSP SD/MMC #1" },
48 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
50 { 0x00, 0x0f, "USB #0" },
51 { 0x01, 0x1f, "I2C #0, master, 3V3" },
52 { 0x11, 0x1f, "I2C #0, master, 1V8" },
53 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
54 { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
55 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
56 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
57 { 0x04, 0x1f, "NAND, 3V3" },
58 { 0x14, 0x1f, "NAND, 1V8" },
59 { 0x06, 0x1f, "JTAG" },
60 { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
61 { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
62 { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
63 { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
64 { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
65 { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
66 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
70 #define MXS_BM_USB 0x00
71 #define MXS_BM_I2C_MASTER_3V3 0x01
72 #define MXS_BM_I2C_MASTER_1V8 0x11
73 #define MXS_BM_SPI2_MASTER_3V3_NOR 0x02
74 #define MXS_BM_SPI2_MASTER_1V8_NOR 0x12
75 #define MXS_BM_SPI3_MASTER_3V3_NOR 0x03
76 #define MXS_BM_SPI3_MASTER_1V8_NOR 0x13
77 #define MXS_BM_NAND_3V3 0x04
78 #define MXS_BM_NAND_1V8 0x14
79 #define MXS_BM_JTAG 0x06
80 #define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08
81 #define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18
82 #define MXS_BM_SDMMC0_3V3 0x09
83 #define MXS_BM_SDMMC0_1V8 0x19
84 #define MXS_BM_SDMMC1_3V3 0x0a
85 #define MXS_BM_SDMMC1_1V8 0x1a
87 #define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200))