1e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2e65e175bSOded Gabbay * 3e65e175bSOded Gabbay * Copyright 2020-2022 HabanaLabs, Ltd. 4e65e175bSOded Gabbay * All Rights Reserved. 5e65e175bSOded Gabbay * 6e65e175bSOded Gabbay */ 7e65e175bSOded Gabbay 8e65e175bSOded Gabbay #ifndef GAUDI2_MASKS_H_ 9e65e175bSOded Gabbay #define GAUDI2_MASKS_H_ 10e65e175bSOded Gabbay 11e65e175bSOded Gabbay #include "../include/gaudi2/asic_reg/gaudi2_regs.h" 12e65e175bSOded Gabbay 13e65e175bSOded Gabbay /* Useful masks for bits in various registers */ 14e65e175bSOded Gabbay #define QMAN_GLBL_ERR_CFG_MSG_EN_MASK \ 15e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ 16e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ 17e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) 18e65e175bSOded Gabbay 19e65e175bSOded Gabbay #define QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK \ 20e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ 21e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ 22e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ 23e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT)) 24e65e175bSOded Gabbay 25e65e175bSOded Gabbay #define QMAN_GLBL_ERR_CFG1_MSG_EN_MASK \ 26e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT) 27e65e175bSOded Gabbay 28e65e175bSOded Gabbay #define QMAN_GLBL_ERR_CFG1_STOP_ON_ERR_EN_MASK \ 29e65e175bSOded Gabbay ((0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT) | \ 30e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT)) 31e65e175bSOded Gabbay 32e65e175bSOded Gabbay #define QM_PQC_LBW_WDATA \ 33e65e175bSOded Gabbay ((1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_SHIFT) | \ 34e65e175bSOded Gabbay (1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_SHIFT)) 35e65e175bSOded Gabbay 36e65e175bSOded Gabbay #define QMAN_MAKE_TRUSTED \ 37e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \ 38e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \ 39e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT)) 40e65e175bSOded Gabbay 41e65e175bSOded Gabbay #define QMAN_MAKE_TRUSTED_TEST_MODE \ 42e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \ 43e65e175bSOded Gabbay (0xF << PDMA0_QM_GLBL_PROT_CQF_SHIFT) | \ 44e65e175bSOded Gabbay (0xF << PDMA0_QM_GLBL_PROT_CP_SHIFT) | \ 45e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \ 46e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT)) 47e65e175bSOded Gabbay 48e65e175bSOded Gabbay #define QMAN_ENABLE \ 49e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ 50e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ 51e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \ 52e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT)) 53e65e175bSOded Gabbay 54e65e175bSOded Gabbay #define PDMA0_QMAN_ENABLE \ 55e65e175bSOded Gabbay ((0x3 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ 56e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ 57e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \ 58e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT)) 59e65e175bSOded Gabbay 60e65e175bSOded Gabbay #define PDMA1_QMAN_ENABLE \ 61e65e175bSOded Gabbay ((0x1 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ 62e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ 63e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \ 64e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT)) 65e65e175bSOded Gabbay 66e65e175bSOded Gabbay /* QM_IDLE_MASK is valid for all engines QM idle check */ 67e65e175bSOded Gabbay #define QM_IDLE_MASK (DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \ 68e65e175bSOded Gabbay DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \ 69e65e175bSOded Gabbay DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK) 70e65e175bSOded Gabbay 71e65e175bSOded Gabbay #define QM_ARC_IDLE_MASK DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 72e65e175bSOded Gabbay 73e65e175bSOded Gabbay #define MME_ARCH_IDLE_MASK \ 74e65e175bSOded Gabbay (DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK | \ 75e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK | \ 76e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK | \ 77e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK | \ 78e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK | \ 79e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK) 80e65e175bSOded Gabbay 81e65e175bSOded Gabbay #define TPC_IDLE_MASK (DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \ 82e65e175bSOded Gabbay DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK | \ 83e65e175bSOded Gabbay DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK | \ 84e65e175bSOded Gabbay DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK | \ 85e65e175bSOded Gabbay DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK) 86e65e175bSOded Gabbay 87e65e175bSOded Gabbay #define DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 88e65e175bSOded Gabbay 89*f7f0085eSKoby Elbaz #define DCORE0_TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK 0x40 90*f7f0085eSKoby Elbaz 91e65e175bSOded Gabbay /* CGM_IDLE_MASK is valid for all engines CGM idle check */ 92e65e175bSOded Gabbay #define CGM_IDLE_MASK DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 93e65e175bSOded Gabbay 94e65e175bSOded Gabbay #define QM_GLBL_CFG1_PQF_STOP PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 95e65e175bSOded Gabbay #define QM_GLBL_CFG1_CQF_STOP PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 96e65e175bSOded Gabbay #define QM_GLBL_CFG1_CP_STOP PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 97e65e175bSOded Gabbay #define QM_GLBL_CFG1_PQF_FLUSH PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 98e65e175bSOded Gabbay #define QM_GLBL_CFG1_CQF_FLUSH PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 99e65e175bSOded Gabbay #define QM_GLBL_CFG1_CP_FLUSH PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 100e65e175bSOded Gabbay 101e65e175bSOded Gabbay #define QM_GLBL_CFG2_ARC_CQF_STOP PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 102e65e175bSOded Gabbay #define QM_GLBL_CFG2_ARC_CQF_FLUSH PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 103e65e175bSOded Gabbay 104e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 105e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 106e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 107e65e175bSOded Gabbay 108e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_MASK (\ 109e65e175bSOded Gabbay QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\ 110e65e175bSOded Gabbay QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\ 111e65e175bSOded Gabbay QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK) 112e65e175bSOded Gabbay 113e65e175bSOded Gabbay #define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1 114e65e175bSOded Gabbay #define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2 115e65e175bSOded Gabbay 116e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK GENMASK(1, 0) 117e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_SRC_POS_INF_MASK BIT(2) 118e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_SRC_NEG_INF_MASK BIT(3) 119e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_SRC_NAN_MASK BIT(4) 120e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_RESULT_POS_INF_MASK BIT(5) 121e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_RESULT_NEG_INF_MASK BIT(6) 122e65e175bSOded Gabbay 123e65e175bSOded Gabbay #define SM_CQ_L2H_MASK_VAL 0xFFFFFFFFFC000000ull 124e65e175bSOded Gabbay #define SM_CQ_L2H_CMPR_VAL 0x1000007FFC000000ull 125e65e175bSOded Gabbay #define SM_CQ_L2H_LOW_MASK GENMASK(31, 20) 126e65e175bSOded Gabbay #define SM_CQ_L2H_LOW_SHIFT 20 127e65e175bSOded Gabbay 128e65e175bSOded Gabbay #define MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK \ 129e65e175bSOded Gabbay REG_FIELD_MASK(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE, HOP4_PAGE_SIZE) 130e65e175bSOded Gabbay #define STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK \ 131e65e175bSOded Gabbay REG_FIELD_MASK(DCORE0_HMMU0_STLB_HOP_CONFIGURATION, ONLY_LARGE_PAGE) 132e65e175bSOded Gabbay 133e65e175bSOded Gabbay #define AXUSER_HB_SEC_ASID_MASK 0x3FF 134e65e175bSOded Gabbay #define AXUSER_HB_SEC_MMBP_MASK 0x400 135e65e175bSOded Gabbay 136e65e175bSOded Gabbay #define MMUBP_ASID_MASK (AXUSER_HB_SEC_ASID_MASK | AXUSER_HB_SEC_MMBP_MASK) 137e65e175bSOded Gabbay 138e65e175bSOded Gabbay #define ROT_MSS_HALT_WBC_MASK BIT(0) 139e65e175bSOded Gabbay #define ROT_MSS_HALT_RSB_MASK BIT(1) 140e65e175bSOded Gabbay #define ROT_MSS_HALT_MRSB_MASK BIT(2) 141e65e175bSOded Gabbay 142e65e175bSOded Gabbay #define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SHIFT 0 143e65e175bSOded Gabbay #define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MASK 0x1 144e65e175bSOded Gabbay 145e65e175bSOded Gabbay #define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_SHIFT 15 146e65e175bSOded Gabbay #define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK 0x8000 147e65e175bSOded Gabbay 148e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_SHIFT 0 149e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK 0x1 150e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_SHIFT 1 151e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK 0x2 152e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_SHIFT 2 153e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK 0x4 154e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK_SHIFT 3 155e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK_MASK 0x8 156e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK_SHIFT 4 157e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK_MASK 0x10 158e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK_SHIFT 5 159e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK_MASK 0x20 160e65e175bSOded Gabbay 161e65e175bSOded Gabbay #endif /* GAUDI2_MASKS_H_ */ 162