183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2550e3dc0SWang Huan /* 3550e3dc0SWang Huan * Copyright 2014 Freescale Semiconductor, Inc. 4550e3dc0SWang Huan */ 5550e3dc0SWang Huan 6550e3dc0SWang Huan #ifndef __DDR_H__ 7550e3dc0SWang Huan #define __DDR_H__ 8*15809705SAlison Wang 9*15809705SAlison Wang void erratum_a008850_post(void); 10*15809705SAlison Wang 11550e3dc0SWang Huan struct board_specific_parameters { 12550e3dc0SWang Huan u32 n_ranks; 13550e3dc0SWang Huan u32 datarate_mhz_high; 14550e3dc0SWang Huan u32 rank_gb; 15550e3dc0SWang Huan u32 clk_adjust; 16550e3dc0SWang Huan u32 wrlvl_start; 17550e3dc0SWang Huan u32 wrlvl_ctl_2; 18550e3dc0SWang Huan u32 wrlvl_ctl_3; 19550e3dc0SWang Huan u32 cpo_override; 20550e3dc0SWang Huan u32 write_data_delay; 21550e3dc0SWang Huan u32 force_2t; 22550e3dc0SWang Huan }; 23550e3dc0SWang Huan 24550e3dc0SWang Huan /* 25550e3dc0SWang Huan * These tables contain all valid speeds we want to override with board 26550e3dc0SWang Huan * specific parameters. datarate_mhz_high values need to be in ascending order 27550e3dc0SWang Huan * for each n_ranks group. 28550e3dc0SWang Huan */ 29550e3dc0SWang Huan static const struct board_specific_parameters udimm0[] = { 30550e3dc0SWang Huan /* 31550e3dc0SWang Huan * memory controller 0 32550e3dc0SWang Huan * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 33550e3dc0SWang Huan * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 34550e3dc0SWang Huan */ 35c7eae7fcSYork Sun #ifdef CONFIG_SYS_FSL_DDR4 36e04f9d0cSShengzhou Liu {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 37e04f9d0cSShengzhou Liu {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, 38e04f9d0cSShengzhou Liu {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,}, 39e04f9d0cSShengzhou Liu {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, 40e04f9d0cSShengzhou Liu {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, 41c7eae7fcSYork Sun #elif defined(CONFIG_SYS_FSL_DDR3) 42e04f9d0cSShengzhou Liu {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 43e04f9d0cSShengzhou Liu {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 44e04f9d0cSShengzhou Liu {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 45e04f9d0cSShengzhou Liu {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 46e04f9d0cSShengzhou Liu {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 47e04f9d0cSShengzhou Liu {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 48e04f9d0cSShengzhou Liu {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 49e04f9d0cSShengzhou Liu {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 50e04f9d0cSShengzhou Liu {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 51c7eae7fcSYork Sun #else 52c7eae7fcSYork Sun #error DDR type not defined 53c7eae7fcSYork Sun #endif 54550e3dc0SWang Huan {} 55550e3dc0SWang Huan }; 56550e3dc0SWang Huan 57550e3dc0SWang Huan static const struct board_specific_parameters *udimms[] = { 58550e3dc0SWang Huan udimm0, 59550e3dc0SWang Huan }; 60550e3dc0SWang Huan 61550e3dc0SWang Huan #endif 62