1db3239f5SHawking Zhang /* 2db3239f5SHawking Zhang * Copyright (C) 2019 Advanced Micro Devices, Inc. 3db3239f5SHawking Zhang * 4db3239f5SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5db3239f5SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6db3239f5SHawking Zhang * to deal in the Software without restriction, including without limitation 7db3239f5SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8db3239f5SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9db3239f5SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10db3239f5SHawking Zhang * 11db3239f5SHawking Zhang * The above copyright notice and this permission notice shall be included 12db3239f5SHawking Zhang * in all copies or substantial portions of the Software. 13db3239f5SHawking Zhang * 14db3239f5SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15db3239f5SHawking Zhang * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16db3239f5SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17db3239f5SHawking Zhang * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18db3239f5SHawking Zhang * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19db3239f5SHawking Zhang * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20db3239f5SHawking Zhang */ 21db3239f5SHawking Zhang #ifndef _athub_2_0_0_SH_MASK_HEADER 22db3239f5SHawking Zhang #define _athub_2_0_0_SH_MASK_HEADER 23db3239f5SHawking Zhang 24db3239f5SHawking Zhang 25db3239f5SHawking Zhang // addressBlock: athub_atsdec 26db3239f5SHawking Zhang //ATC_ATS_CNTL 27db3239f5SHawking Zhang #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 28db3239f5SHawking Zhang #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 29db3239f5SHawking Zhang #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 30db3239f5SHawking Zhang #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 31db3239f5SHawking Zhang #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 32db3239f5SHawking Zhang #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 33db3239f5SHawking Zhang #define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 34db3239f5SHawking Zhang #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 35db3239f5SHawking Zhang #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 36db3239f5SHawking Zhang #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 37db3239f5SHawking Zhang #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L 38db3239f5SHawking Zhang #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L 39db3239f5SHawking Zhang #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L 40db3239f5SHawking Zhang #define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L 41db3239f5SHawking Zhang //ATC_ATS_STATUS 42db3239f5SHawking Zhang #define ATC_ATS_STATUS__BUSY__SHIFT 0x0 43db3239f5SHawking Zhang #define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 44db3239f5SHawking Zhang #define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 45db3239f5SHawking Zhang #define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 46db3239f5SHawking Zhang #define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 47db3239f5SHawking Zhang #define ATC_ATS_STATUS__BUSY_MASK 0x00000001L 48db3239f5SHawking Zhang #define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L 49db3239f5SHawking Zhang #define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L 50db3239f5SHawking Zhang #define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L 51db3239f5SHawking Zhang #define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L 52db3239f5SHawking Zhang //ATC_ATS_FAULT_CNTL 53db3239f5SHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 54db3239f5SHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa 55db3239f5SHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 56db3239f5SHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL 57db3239f5SHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L 58db3239f5SHawking Zhang #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L 59db3239f5SHawking Zhang //ATC_ATS_FAULT_STATUS_INFO 60db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 61db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa 62db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf 63db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 64db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 65db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 66db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 67db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 68db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL 69db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L 70db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L 71db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L 72db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L 73db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L 74db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L 75db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L 76db3239f5SHawking Zhang //ATC_ATS_FAULT_STATUS_ADDR 77db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 78db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL 79db3239f5SHawking Zhang //ATC_ATS_DEFAULT_PAGE_LOW 80db3239f5SHawking Zhang #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 81db3239f5SHawking Zhang #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL 82db3239f5SHawking Zhang //ATC_TRANS_FAULT_RSPCNTRL 83db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 84db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 85db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 86db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 87db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 88db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 89db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 90db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 91db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 92db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 93db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa 94db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb 95db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc 96db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd 97db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe 98db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf 99db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 100db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 101db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 102db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 103db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 104db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 105db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 106db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 107db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 108db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 109db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a 110db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b 111db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c 112db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d 113db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e 114db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f 115db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L 116db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L 117db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L 118db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L 119db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L 120db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L 121db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L 122db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L 123db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L 124db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L 125db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L 126db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L 127db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L 128db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L 129db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L 130db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L 131db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L 132db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L 133db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L 134db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L 135db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L 136db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L 137db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L 138db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L 139db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L 140db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L 141db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L 142db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L 143db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L 144db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L 145db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L 146db3239f5SHawking Zhang #define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L 147db3239f5SHawking Zhang //ATC_ATS_FAULT_STATUS_INFO2 148db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 149db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 150db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 151db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L 152db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000003EL 153db3239f5SHawking Zhang #define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L 154db3239f5SHawking Zhang //ATHUB_MISC_CNTL 155db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 156db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 157db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 158db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 159db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 160db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b 161db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c 162db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L 163db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L 164db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L 165db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L 166db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L 167db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L 168db3239f5SHawking Zhang #define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L 169db3239f5SHawking Zhang //ATC_VMID_PASID_MAPPING_UPDATE_STATUS 170db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 171db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 172db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 173db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 174db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 175db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 176db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 177db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 178db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 179db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 180db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa 181db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb 182db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc 183db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd 184db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe 185db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf 186db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 187db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 188db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 189db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 190db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 191db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 192db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 193db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 194db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 195db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 196db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a 197db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b 198db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c 199db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d 200db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e 201db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f 202db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L 203db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L 204db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L 205db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L 206db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L 207db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L 208db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L 209db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L 210db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L 211db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L 212db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L 213db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L 214db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L 215db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L 216db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L 217db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L 218db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L 219db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L 220db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L 221db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L 222db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L 223db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L 224db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L 225db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L 226db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L 227db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L 228db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L 229db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L 230db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L 231db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L 232db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L 233db3239f5SHawking Zhang #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L 234db3239f5SHawking Zhang //ATC_VMID0_PASID_MAPPING 235db3239f5SHawking Zhang #define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 236db3239f5SHawking Zhang #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 237db3239f5SHawking Zhang #define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f 238db3239f5SHawking Zhang #define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL 239db3239f5SHawking Zhang #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 240db3239f5SHawking Zhang #define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L 241db3239f5SHawking Zhang //ATC_VMID1_PASID_MAPPING 242db3239f5SHawking Zhang #define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 243db3239f5SHawking Zhang #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 244db3239f5SHawking Zhang #define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f 245db3239f5SHawking Zhang #define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL 246db3239f5SHawking Zhang #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 247db3239f5SHawking Zhang #define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L 248db3239f5SHawking Zhang //ATC_VMID2_PASID_MAPPING 249db3239f5SHawking Zhang #define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 250db3239f5SHawking Zhang #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 251db3239f5SHawking Zhang #define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f 252db3239f5SHawking Zhang #define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL 253db3239f5SHawking Zhang #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 254db3239f5SHawking Zhang #define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L 255db3239f5SHawking Zhang //ATC_VMID3_PASID_MAPPING 256db3239f5SHawking Zhang #define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 257db3239f5SHawking Zhang #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 258db3239f5SHawking Zhang #define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f 259db3239f5SHawking Zhang #define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL 260db3239f5SHawking Zhang #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 261db3239f5SHawking Zhang #define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L 262db3239f5SHawking Zhang //ATC_VMID4_PASID_MAPPING 263db3239f5SHawking Zhang #define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 264db3239f5SHawking Zhang #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 265db3239f5SHawking Zhang #define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f 266db3239f5SHawking Zhang #define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL 267db3239f5SHawking Zhang #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 268db3239f5SHawking Zhang #define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L 269db3239f5SHawking Zhang //ATC_VMID5_PASID_MAPPING 270db3239f5SHawking Zhang #define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 271db3239f5SHawking Zhang #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 272db3239f5SHawking Zhang #define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f 273db3239f5SHawking Zhang #define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL 274db3239f5SHawking Zhang #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 275db3239f5SHawking Zhang #define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L 276db3239f5SHawking Zhang //ATC_VMID6_PASID_MAPPING 277db3239f5SHawking Zhang #define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 278db3239f5SHawking Zhang #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 279db3239f5SHawking Zhang #define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f 280db3239f5SHawking Zhang #define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL 281db3239f5SHawking Zhang #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 282db3239f5SHawking Zhang #define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L 283db3239f5SHawking Zhang //ATC_VMID7_PASID_MAPPING 284db3239f5SHawking Zhang #define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 285db3239f5SHawking Zhang #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 286db3239f5SHawking Zhang #define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f 287db3239f5SHawking Zhang #define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL 288db3239f5SHawking Zhang #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 289db3239f5SHawking Zhang #define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L 290db3239f5SHawking Zhang //ATC_VMID8_PASID_MAPPING 291db3239f5SHawking Zhang #define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 292db3239f5SHawking Zhang #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 293db3239f5SHawking Zhang #define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f 294db3239f5SHawking Zhang #define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL 295db3239f5SHawking Zhang #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 296db3239f5SHawking Zhang #define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L 297db3239f5SHawking Zhang //ATC_VMID9_PASID_MAPPING 298db3239f5SHawking Zhang #define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 299db3239f5SHawking Zhang #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 300db3239f5SHawking Zhang #define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f 301db3239f5SHawking Zhang #define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL 302db3239f5SHawking Zhang #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 303db3239f5SHawking Zhang #define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L 304db3239f5SHawking Zhang //ATC_VMID10_PASID_MAPPING 305db3239f5SHawking Zhang #define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 306db3239f5SHawking Zhang #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 307db3239f5SHawking Zhang #define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f 308db3239f5SHawking Zhang #define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL 309db3239f5SHawking Zhang #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 310db3239f5SHawking Zhang #define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L 311db3239f5SHawking Zhang //ATC_VMID11_PASID_MAPPING 312db3239f5SHawking Zhang #define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 313db3239f5SHawking Zhang #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 314db3239f5SHawking Zhang #define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f 315db3239f5SHawking Zhang #define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL 316db3239f5SHawking Zhang #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 317db3239f5SHawking Zhang #define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L 318db3239f5SHawking Zhang //ATC_VMID12_PASID_MAPPING 319db3239f5SHawking Zhang #define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 320db3239f5SHawking Zhang #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 321db3239f5SHawking Zhang #define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f 322db3239f5SHawking Zhang #define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL 323db3239f5SHawking Zhang #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 324db3239f5SHawking Zhang #define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L 325db3239f5SHawking Zhang //ATC_VMID13_PASID_MAPPING 326db3239f5SHawking Zhang #define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 327db3239f5SHawking Zhang #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 328db3239f5SHawking Zhang #define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f 329db3239f5SHawking Zhang #define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL 330db3239f5SHawking Zhang #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 331db3239f5SHawking Zhang #define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L 332db3239f5SHawking Zhang //ATC_VMID14_PASID_MAPPING 333db3239f5SHawking Zhang #define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 334db3239f5SHawking Zhang #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 335db3239f5SHawking Zhang #define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f 336db3239f5SHawking Zhang #define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL 337db3239f5SHawking Zhang #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 338db3239f5SHawking Zhang #define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L 339db3239f5SHawking Zhang //ATC_VMID15_PASID_MAPPING 340db3239f5SHawking Zhang #define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 341db3239f5SHawking Zhang #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 342db3239f5SHawking Zhang #define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f 343db3239f5SHawking Zhang #define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL 344db3239f5SHawking Zhang #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 345db3239f5SHawking Zhang #define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L 346db3239f5SHawking Zhang //ATC_ATS_VMID_STATUS 347db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 348db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 349db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 350db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 351db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 352db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 353db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 354db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 355db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 356db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 357db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa 358db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb 359db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc 360db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd 361db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe 362db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf 363db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 364db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 365db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 366db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 367db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 368db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 369db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 370db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 371db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 372db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 373db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a 374db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b 375db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c 376db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d 377db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e 378db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f 379db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L 380db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L 381db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L 382db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L 383db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L 384db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L 385db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L 386db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L 387db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L 388db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L 389db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L 390db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L 391db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L 392db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L 393db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L 394db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L 395db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L 396db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L 397db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L 398db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L 399db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L 400db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L 401db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L 402db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L 403db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L 404db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L 405db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L 406db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L 407db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L 408db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L 409db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L 410db3239f5SHawking Zhang #define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L 411db3239f5SHawking Zhang //ATC_ATS_GFX_ATCL2_STATUS 412db3239f5SHawking Zhang #define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 413db3239f5SHawking Zhang #define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 414db3239f5SHawking Zhang //ATC_PERFCOUNTER0_CFG 415db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 416db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 417db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 418db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 419db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 420db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 421db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 422db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 423db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 424db3239f5SHawking Zhang #define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 425db3239f5SHawking Zhang //ATC_PERFCOUNTER1_CFG 426db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 427db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 428db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 429db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 430db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 431db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 432db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 433db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 434db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 435db3239f5SHawking Zhang #define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 436db3239f5SHawking Zhang //ATC_PERFCOUNTER2_CFG 437db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 438db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 439db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 440db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 441db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 442db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 443db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 444db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 445db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 446db3239f5SHawking Zhang #define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 447db3239f5SHawking Zhang //ATC_PERFCOUNTER3_CFG 448db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 449db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 450db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 451db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 452db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 453db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 454db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 455db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 456db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 457db3239f5SHawking Zhang #define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 458db3239f5SHawking Zhang //ATC_PERFCOUNTER_RSLT_CNTL 459db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 460db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 461db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 462db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 463db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 464db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 465db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 466db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 467db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 468db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 469db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 470db3239f5SHawking Zhang #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 471db3239f5SHawking Zhang //ATC_PERFCOUNTER_LO 472db3239f5SHawking Zhang #define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 473db3239f5SHawking Zhang #define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 474db3239f5SHawking Zhang //ATC_PERFCOUNTER_HI 475db3239f5SHawking Zhang #define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 476db3239f5SHawking Zhang #define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 477db3239f5SHawking Zhang #define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 478db3239f5SHawking Zhang #define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 479db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL 480db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 481db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 482db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 483db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 484db3239f5SHawking Zhang //ATHUB_PCIE_PASID_CNTL 485db3239f5SHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 486db3239f5SHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 487db3239f5SHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 488db3239f5SHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L 489db3239f5SHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L 490db3239f5SHawking Zhang #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L 491db3239f5SHawking Zhang //ATHUB_PCIE_PAGE_REQ_CNTL 492db3239f5SHawking Zhang #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 493db3239f5SHawking Zhang #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 494db3239f5SHawking Zhang #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L 495db3239f5SHawking Zhang #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L 496db3239f5SHawking Zhang //ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 497db3239f5SHawking Zhang #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 498db3239f5SHawking Zhang #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL 499db3239f5SHawking Zhang //ATHUB_COMMAND 500db3239f5SHawking Zhang #define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 501db3239f5SHawking Zhang #define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L 502db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_0 503db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 504db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 505db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_1 506db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 507db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 508db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_2 509db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 510db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 511db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_3 512db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 513db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 514db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_4 515db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 516db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 517db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_5 518db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 519db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 520db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_6 521db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 522db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 523db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_7 524db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 525db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 526db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_8 527db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 528db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 529db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_9 530db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 531db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 532db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_10 533db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 534db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 535db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_11 536db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 537db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 538db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_12 539db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 540db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 541db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_13 542db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 543db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 544db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_14 545db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 546db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 547db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_15 548db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 549db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 550db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_16 551db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f 552db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L 553db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_17 554db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f 555db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L 556db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_18 557db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f 558db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L 559db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_19 560db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f 561db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L 562db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_20 563db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f 564db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L 565db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_21 566db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f 567db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L 568db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_22 569db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f 570db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L 571db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_23 572db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f 573db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L 574db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_24 575db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f 576db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L 577db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_25 578db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f 579db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L 580db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_26 581db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f 582db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L 583db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_27 584db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f 585db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L 586db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_28 587db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f 588db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L 589db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_29 590db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f 591db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L 592db3239f5SHawking Zhang //ATHUB_PCIE_ATS_CNTL_VF_30 593db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f 594db3239f5SHawking Zhang #define ATHUB_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L 595db3239f5SHawking Zhang //ATHUB_MEM_POWER_LS 596db3239f5SHawking Zhang #define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 597db3239f5SHawking Zhang #define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 598db3239f5SHawking Zhang #define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 599db3239f5SHawking Zhang #define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 600db3239f5SHawking Zhang //ATS_IH_CREDIT 601db3239f5SHawking Zhang #define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 602db3239f5SHawking Zhang #define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 603db3239f5SHawking Zhang #define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 604db3239f5SHawking Zhang #define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 605db3239f5SHawking Zhang //ATHUB_IH_CREDIT 606db3239f5SHawking Zhang #define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 607db3239f5SHawking Zhang #define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 608db3239f5SHawking Zhang #define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 609db3239f5SHawking Zhang #define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 610db3239f5SHawking Zhang //ATC_VMID16_PASID_MAPPING 611db3239f5SHawking Zhang #define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 612db3239f5SHawking Zhang #define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 613db3239f5SHawking Zhang #define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f 614db3239f5SHawking Zhang #define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL 615db3239f5SHawking Zhang #define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 616db3239f5SHawking Zhang #define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L 617db3239f5SHawking Zhang //ATC_VMID17_PASID_MAPPING 618db3239f5SHawking Zhang #define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 619db3239f5SHawking Zhang #define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 620db3239f5SHawking Zhang #define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f 621db3239f5SHawking Zhang #define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL 622db3239f5SHawking Zhang #define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 623db3239f5SHawking Zhang #define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L 624db3239f5SHawking Zhang //ATC_VMID18_PASID_MAPPING 625db3239f5SHawking Zhang #define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 626db3239f5SHawking Zhang #define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 627db3239f5SHawking Zhang #define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f 628db3239f5SHawking Zhang #define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL 629db3239f5SHawking Zhang #define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 630db3239f5SHawking Zhang #define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L 631db3239f5SHawking Zhang //ATC_VMID19_PASID_MAPPING 632db3239f5SHawking Zhang #define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 633db3239f5SHawking Zhang #define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 634db3239f5SHawking Zhang #define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f 635db3239f5SHawking Zhang #define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL 636db3239f5SHawking Zhang #define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 637db3239f5SHawking Zhang #define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L 638db3239f5SHawking Zhang //ATC_VMID20_PASID_MAPPING 639db3239f5SHawking Zhang #define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 640db3239f5SHawking Zhang #define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 641db3239f5SHawking Zhang #define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f 642db3239f5SHawking Zhang #define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL 643db3239f5SHawking Zhang #define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 644db3239f5SHawking Zhang #define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L 645db3239f5SHawking Zhang //ATC_VMID21_PASID_MAPPING 646db3239f5SHawking Zhang #define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 647db3239f5SHawking Zhang #define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 648db3239f5SHawking Zhang #define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f 649db3239f5SHawking Zhang #define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL 650db3239f5SHawking Zhang #define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 651db3239f5SHawking Zhang #define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L 652db3239f5SHawking Zhang //ATC_VMID22_PASID_MAPPING 653db3239f5SHawking Zhang #define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 654db3239f5SHawking Zhang #define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 655db3239f5SHawking Zhang #define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f 656db3239f5SHawking Zhang #define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL 657db3239f5SHawking Zhang #define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 658db3239f5SHawking Zhang #define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L 659db3239f5SHawking Zhang //ATC_VMID23_PASID_MAPPING 660db3239f5SHawking Zhang #define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 661db3239f5SHawking Zhang #define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 662db3239f5SHawking Zhang #define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f 663db3239f5SHawking Zhang #define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL 664db3239f5SHawking Zhang #define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 665db3239f5SHawking Zhang #define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L 666db3239f5SHawking Zhang //ATC_VMID24_PASID_MAPPING 667db3239f5SHawking Zhang #define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 668db3239f5SHawking Zhang #define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 669db3239f5SHawking Zhang #define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f 670db3239f5SHawking Zhang #define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL 671db3239f5SHawking Zhang #define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 672db3239f5SHawking Zhang #define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L 673db3239f5SHawking Zhang //ATC_VMID25_PASID_MAPPING 674db3239f5SHawking Zhang #define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 675db3239f5SHawking Zhang #define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 676db3239f5SHawking Zhang #define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f 677db3239f5SHawking Zhang #define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL 678db3239f5SHawking Zhang #define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 679db3239f5SHawking Zhang #define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L 680db3239f5SHawking Zhang //ATC_VMID26_PASID_MAPPING 681db3239f5SHawking Zhang #define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 682db3239f5SHawking Zhang #define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 683db3239f5SHawking Zhang #define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f 684db3239f5SHawking Zhang #define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL 685db3239f5SHawking Zhang #define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 686db3239f5SHawking Zhang #define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L 687db3239f5SHawking Zhang //ATC_VMID27_PASID_MAPPING 688db3239f5SHawking Zhang #define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 689db3239f5SHawking Zhang #define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 690db3239f5SHawking Zhang #define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f 691db3239f5SHawking Zhang #define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL 692db3239f5SHawking Zhang #define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 693db3239f5SHawking Zhang #define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L 694db3239f5SHawking Zhang //ATC_VMID28_PASID_MAPPING 695db3239f5SHawking Zhang #define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 696db3239f5SHawking Zhang #define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 697db3239f5SHawking Zhang #define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f 698db3239f5SHawking Zhang #define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL 699db3239f5SHawking Zhang #define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 700db3239f5SHawking Zhang #define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L 701db3239f5SHawking Zhang //ATC_VMID29_PASID_MAPPING 702db3239f5SHawking Zhang #define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 703db3239f5SHawking Zhang #define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 704db3239f5SHawking Zhang #define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f 705db3239f5SHawking Zhang #define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL 706db3239f5SHawking Zhang #define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 707db3239f5SHawking Zhang #define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L 708db3239f5SHawking Zhang //ATC_VMID30_PASID_MAPPING 709db3239f5SHawking Zhang #define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 710db3239f5SHawking Zhang #define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 711db3239f5SHawking Zhang #define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f 712db3239f5SHawking Zhang #define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL 713db3239f5SHawking Zhang #define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 714db3239f5SHawking Zhang #define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L 715db3239f5SHawking Zhang //ATC_VMID31_PASID_MAPPING 716db3239f5SHawking Zhang #define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 717db3239f5SHawking Zhang #define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 718db3239f5SHawking Zhang #define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f 719db3239f5SHawking Zhang #define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL 720db3239f5SHawking Zhang #define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 721db3239f5SHawking Zhang #define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L 722db3239f5SHawking Zhang //ATC_ATS_MMHUB_ATCL2_STATUS 723db3239f5SHawking Zhang #define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 724db3239f5SHawking Zhang #define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 725db3239f5SHawking Zhang //ATHUB_SHARED_VIRT_RESET_REQ 726db3239f5SHawking Zhang #define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 727db3239f5SHawking Zhang #define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 728db3239f5SHawking Zhang #define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL 729db3239f5SHawking Zhang #define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 730db3239f5SHawking Zhang //ATHUB_SHARED_ACTIVE_FCN_ID 731db3239f5SHawking Zhang #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 732db3239f5SHawking Zhang #define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 733db3239f5SHawking Zhang #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL 734db3239f5SHawking Zhang #define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 735db3239f5SHawking Zhang //ATC_ATS_SDPPORT_CNTL 736db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 737db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 738db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 739db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 740db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 741db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 742db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd 743db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe 744db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf 745db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 746db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 747db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 748db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 749db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 750db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 751db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 752db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 753db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 754db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 755db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L 756db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L 757db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L 758db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L 759db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L 760db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L 761db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L 762db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L 763db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L 764db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L 765db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L 766db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L 767db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L 768db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L 769db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L 770db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L 771db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L 772db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L 773db3239f5SHawking Zhang #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L 774db3239f5SHawking Zhang //ATC_ATS_VMID_SNAPSHOT_GFX_STAT 775db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 776db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 777db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 778db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 779db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 780db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 781db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 782db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 783db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 784db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 785db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa 786db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb 787db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc 788db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd 789db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe 790db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf 791db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L 792db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L 793db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L 794db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L 795db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L 796db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L 797db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L 798db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L 799db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L 800db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L 801db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L 802db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L 803db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L 804db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L 805db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L 806db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L 807db3239f5SHawking Zhang //ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 808db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 809db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 810db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 811db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 812db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 813db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 814db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 815db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 816db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 817db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 818db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa 819db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb 820db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc 821db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd 822db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe 823db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf 824db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L 825db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L 826db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L 827db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L 828db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L 829db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L 830db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L 831db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L 832db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L 833db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L 834db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L 835db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L 836db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L 837db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L 838db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L 839db3239f5SHawking Zhang #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L 840db3239f5SHawking Zhang 841db3239f5SHawking Zhang 842db3239f5SHawking Zhang // addressBlock: athub_xpbdec 843db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR0 844db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 845db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 846db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR1 847db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 848db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 849db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR2 850db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 851db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 852db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR3 853db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 854db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 855db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR4 856db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 857db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL 858db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR5 859db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 860db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL 861db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR6 862db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 863db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL 864db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR7 865db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 866db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL 867db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR8 868db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 869db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL 870db3239f5SHawking Zhang //XPB_RTR_SRC_APRTR9 871db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 872db3239f5SHawking Zhang #define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL 873db3239f5SHawking Zhang //XPB_XDMA_RTR_SRC_APRTR0 874db3239f5SHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 875db3239f5SHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 876db3239f5SHawking Zhang //XPB_XDMA_RTR_SRC_APRTR1 877db3239f5SHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 878db3239f5SHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 879db3239f5SHawking Zhang //XPB_XDMA_RTR_SRC_APRTR2 880db3239f5SHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 881db3239f5SHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 882db3239f5SHawking Zhang //XPB_XDMA_RTR_SRC_APRTR3 883db3239f5SHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 884db3239f5SHawking Zhang #define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 885db3239f5SHawking Zhang //XPB_RTR_DEST_MAP0 886db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 887db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 888db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 889db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 890db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 891db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 892db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 893db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 894db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 895db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 896db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 897db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 898db3239f5SHawking Zhang //XPB_RTR_DEST_MAP1 899db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 900db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 901db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 902db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 903db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 904db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 905db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 906db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 907db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 908db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 909db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 910db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 911db3239f5SHawking Zhang //XPB_RTR_DEST_MAP2 912db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 913db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 914db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 915db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 916db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 917db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 918db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 919db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 920db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 921db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 922db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 923db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 924db3239f5SHawking Zhang //XPB_RTR_DEST_MAP3 925db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 926db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 927db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 928db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 929db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 930db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 931db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 932db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 933db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 934db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 935db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 936db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 937db3239f5SHawking Zhang //XPB_RTR_DEST_MAP4 938db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 939db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 940db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 941db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 942db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 943db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 944db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 945db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL 946db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L 947db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 948db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L 949db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L 950db3239f5SHawking Zhang //XPB_RTR_DEST_MAP5 951db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 952db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 953db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 954db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 955db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 956db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 957db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 958db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL 959db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L 960db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 961db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L 962db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L 963db3239f5SHawking Zhang //XPB_RTR_DEST_MAP6 964db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 965db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 966db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 967db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 968db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 969db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 970db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 971db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL 972db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L 973db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 974db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L 975db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L 976db3239f5SHawking Zhang //XPB_RTR_DEST_MAP7 977db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 978db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 979db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 980db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 981db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 982db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 983db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 984db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL 985db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L 986db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 987db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L 988db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L 989db3239f5SHawking Zhang //XPB_RTR_DEST_MAP8 990db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 991db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 992db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 993db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 994db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 995db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 996db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 997db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL 998db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L 999db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 1000db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L 1001db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L 1002db3239f5SHawking Zhang //XPB_RTR_DEST_MAP9 1003db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 1004db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 1005db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 1006db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 1007db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 1008db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 1009db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 1010db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL 1011db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L 1012db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 1013db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L 1014db3239f5SHawking Zhang #define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L 1015db3239f5SHawking Zhang //XPB_XDMA_RTR_DEST_MAP0 1016db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 1017db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 1018db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 1019db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 1020db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 1021db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 1022db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L 1023db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 1024db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 1025db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 1026db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 1027db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 1028db3239f5SHawking Zhang //XPB_XDMA_RTR_DEST_MAP1 1029db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 1030db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 1031db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 1032db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 1033db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 1034db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 1035db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L 1036db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 1037db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 1038db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 1039db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 1040db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 1041db3239f5SHawking Zhang //XPB_XDMA_RTR_DEST_MAP2 1042db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 1043db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 1044db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 1045db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 1046db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 1047db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 1048db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L 1049db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 1050db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 1051db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 1052db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 1053db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 1054db3239f5SHawking Zhang //XPB_XDMA_RTR_DEST_MAP3 1055db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 1056db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 1057db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 1058db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 1059db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 1060db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 1061db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L 1062db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 1063db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 1064db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 1065db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 1066db3239f5SHawking Zhang #define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 1067db3239f5SHawking Zhang //XPB_CLG_CFG0 1068db3239f5SHawking Zhang #define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 1069db3239f5SHawking Zhang #define XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 1070db3239f5SHawking Zhang #define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 1071db3239f5SHawking Zhang #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 1072db3239f5SHawking Zhang #define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe 1073db3239f5SHawking Zhang #define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL 1074db3239f5SHawking Zhang #define XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L 1075db3239f5SHawking Zhang #define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 1076db3239f5SHawking Zhang #define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L 1077db3239f5SHawking Zhang #define XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003C000L 1078db3239f5SHawking Zhang //XPB_CLG_CFG1 1079db3239f5SHawking Zhang #define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 1080db3239f5SHawking Zhang #define XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 1081db3239f5SHawking Zhang #define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 1082db3239f5SHawking Zhang #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 1083db3239f5SHawking Zhang #define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe 1084db3239f5SHawking Zhang #define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL 1085db3239f5SHawking Zhang #define XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L 1086db3239f5SHawking Zhang #define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 1087db3239f5SHawking Zhang #define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L 1088db3239f5SHawking Zhang #define XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003C000L 1089db3239f5SHawking Zhang //XPB_CLG_CFG2 1090db3239f5SHawking Zhang #define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 1091db3239f5SHawking Zhang #define XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 1092db3239f5SHawking Zhang #define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 1093db3239f5SHawking Zhang #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 1094db3239f5SHawking Zhang #define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe 1095db3239f5SHawking Zhang #define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL 1096db3239f5SHawking Zhang #define XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L 1097db3239f5SHawking Zhang #define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 1098db3239f5SHawking Zhang #define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L 1099db3239f5SHawking Zhang #define XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003C000L 1100db3239f5SHawking Zhang //XPB_CLG_CFG3 1101db3239f5SHawking Zhang #define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 1102db3239f5SHawking Zhang #define XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 1103db3239f5SHawking Zhang #define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 1104db3239f5SHawking Zhang #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 1105db3239f5SHawking Zhang #define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe 1106db3239f5SHawking Zhang #define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL 1107db3239f5SHawking Zhang #define XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L 1108db3239f5SHawking Zhang #define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 1109db3239f5SHawking Zhang #define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L 1110db3239f5SHawking Zhang #define XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003C000L 1111db3239f5SHawking Zhang //XPB_CLG_CFG4 1112db3239f5SHawking Zhang #define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 1113db3239f5SHawking Zhang #define XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 1114db3239f5SHawking Zhang #define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 1115db3239f5SHawking Zhang #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 1116db3239f5SHawking Zhang #define XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe 1117db3239f5SHawking Zhang #define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL 1118db3239f5SHawking Zhang #define XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L 1119db3239f5SHawking Zhang #define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 1120db3239f5SHawking Zhang #define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L 1121db3239f5SHawking Zhang #define XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003C000L 1122db3239f5SHawking Zhang //XPB_CLG_CFG5 1123db3239f5SHawking Zhang #define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 1124db3239f5SHawking Zhang #define XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 1125db3239f5SHawking Zhang #define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 1126db3239f5SHawking Zhang #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 1127db3239f5SHawking Zhang #define XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe 1128db3239f5SHawking Zhang #define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL 1129db3239f5SHawking Zhang #define XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L 1130db3239f5SHawking Zhang #define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 1131db3239f5SHawking Zhang #define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L 1132db3239f5SHawking Zhang #define XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003C000L 1133db3239f5SHawking Zhang //XPB_CLG_CFG6 1134db3239f5SHawking Zhang #define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 1135db3239f5SHawking Zhang #define XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 1136db3239f5SHawking Zhang #define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 1137db3239f5SHawking Zhang #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 1138db3239f5SHawking Zhang #define XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe 1139db3239f5SHawking Zhang #define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL 1140db3239f5SHawking Zhang #define XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L 1141db3239f5SHawking Zhang #define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 1142db3239f5SHawking Zhang #define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L 1143db3239f5SHawking Zhang #define XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003C000L 1144db3239f5SHawking Zhang //XPB_CLG_CFG7 1145db3239f5SHawking Zhang #define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 1146db3239f5SHawking Zhang #define XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 1147db3239f5SHawking Zhang #define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 1148db3239f5SHawking Zhang #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 1149db3239f5SHawking Zhang #define XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe 1150db3239f5SHawking Zhang #define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL 1151db3239f5SHawking Zhang #define XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L 1152db3239f5SHawking Zhang #define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 1153db3239f5SHawking Zhang #define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L 1154db3239f5SHawking Zhang #define XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003C000L 1155db3239f5SHawking Zhang //XPB_CLG_EXTRA 1156db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 1157db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 1158db3239f5SHawking Zhang #define XPB_CLG_EXTRA__VLD0__SHIFT 0xb 1159db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc 1160db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf 1161db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 1162db3239f5SHawking Zhang #define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a 1163db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b 1164db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL 1165db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L 1166db3239f5SHawking Zhang #define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L 1167db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L 1168db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L 1169db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L 1170db3239f5SHawking Zhang #define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L 1171db3239f5SHawking Zhang #define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L 1172db3239f5SHawking Zhang //XPB_CLG_EXTRA_MSK 1173db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 1174db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 1175db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb 1176db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 1177db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL 1178db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L 1179db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L 1180db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L 1181db3239f5SHawking Zhang //XPB_LB_ADDR 1182db3239f5SHawking Zhang #define XPB_LB_ADDR__CMP0__SHIFT 0x0 1183db3239f5SHawking Zhang #define XPB_LB_ADDR__MASK0__SHIFT 0xa 1184db3239f5SHawking Zhang #define XPB_LB_ADDR__CMP1__SHIFT 0x14 1185db3239f5SHawking Zhang #define XPB_LB_ADDR__MASK1__SHIFT 0x1a 1186db3239f5SHawking Zhang #define XPB_LB_ADDR__CMP0_MASK 0x000003FFL 1187db3239f5SHawking Zhang #define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L 1188db3239f5SHawking Zhang #define XPB_LB_ADDR__CMP1_MASK 0x03F00000L 1189db3239f5SHawking Zhang #define XPB_LB_ADDR__MASK1_MASK 0xFC000000L 1190db3239f5SHawking Zhang //XPB_WCB_STS 1191db3239f5SHawking Zhang #define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 1192db3239f5SHawking Zhang #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 1193db3239f5SHawking Zhang #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 1194db3239f5SHawking Zhang #define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL 1195db3239f5SHawking Zhang #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L 1196db3239f5SHawking Zhang #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L 1197db3239f5SHawking Zhang //XPB_HST_CFG 1198db3239f5SHawking Zhang #define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 1199db3239f5SHawking Zhang #define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L 1200db3239f5SHawking Zhang //XPB_P2P_BAR_CFG 1201db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 1202db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 1203db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 1204db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 1205db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 1206db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 1207db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 1208db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 1209db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 1210db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL 1211db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 1212db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 1213db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 1214db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 1215db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 1216db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 1217db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 1218db3239f5SHawking Zhang #define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 1219db3239f5SHawking Zhang //XPB_P2P_BAR0 1220db3239f5SHawking Zhang #define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 1221db3239f5SHawking Zhang #define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 1222db3239f5SHawking Zhang #define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 1223db3239f5SHawking Zhang #define XPB_P2P_BAR0__VALID__SHIFT 0xc 1224db3239f5SHawking Zhang #define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 1225db3239f5SHawking Zhang #define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 1226db3239f5SHawking Zhang #define XPB_P2P_BAR0__RESERVED__SHIFT 0xf 1227db3239f5SHawking Zhang #define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 1228db3239f5SHawking Zhang #define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL 1229db3239f5SHawking Zhang #define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L 1230db3239f5SHawking Zhang #define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L 1231db3239f5SHawking Zhang #define XPB_P2P_BAR0__VALID_MASK 0x00001000L 1232db3239f5SHawking Zhang #define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 1233db3239f5SHawking Zhang #define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 1234db3239f5SHawking Zhang #define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L 1235db3239f5SHawking Zhang #define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L 1236db3239f5SHawking Zhang //XPB_P2P_BAR1 1237db3239f5SHawking Zhang #define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 1238db3239f5SHawking Zhang #define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 1239db3239f5SHawking Zhang #define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 1240db3239f5SHawking Zhang #define XPB_P2P_BAR1__VALID__SHIFT 0xc 1241db3239f5SHawking Zhang #define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 1242db3239f5SHawking Zhang #define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 1243db3239f5SHawking Zhang #define XPB_P2P_BAR1__RESERVED__SHIFT 0xf 1244db3239f5SHawking Zhang #define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 1245db3239f5SHawking Zhang #define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL 1246db3239f5SHawking Zhang #define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L 1247db3239f5SHawking Zhang #define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L 1248db3239f5SHawking Zhang #define XPB_P2P_BAR1__VALID_MASK 0x00001000L 1249db3239f5SHawking Zhang #define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 1250db3239f5SHawking Zhang #define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 1251db3239f5SHawking Zhang #define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L 1252db3239f5SHawking Zhang #define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L 1253db3239f5SHawking Zhang //XPB_P2P_BAR2 1254db3239f5SHawking Zhang #define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 1255db3239f5SHawking Zhang #define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 1256db3239f5SHawking Zhang #define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 1257db3239f5SHawking Zhang #define XPB_P2P_BAR2__VALID__SHIFT 0xc 1258db3239f5SHawking Zhang #define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 1259db3239f5SHawking Zhang #define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 1260db3239f5SHawking Zhang #define XPB_P2P_BAR2__RESERVED__SHIFT 0xf 1261db3239f5SHawking Zhang #define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 1262db3239f5SHawking Zhang #define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL 1263db3239f5SHawking Zhang #define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L 1264db3239f5SHawking Zhang #define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L 1265db3239f5SHawking Zhang #define XPB_P2P_BAR2__VALID_MASK 0x00001000L 1266db3239f5SHawking Zhang #define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 1267db3239f5SHawking Zhang #define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 1268db3239f5SHawking Zhang #define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L 1269db3239f5SHawking Zhang #define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L 1270db3239f5SHawking Zhang //XPB_P2P_BAR3 1271db3239f5SHawking Zhang #define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 1272db3239f5SHawking Zhang #define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 1273db3239f5SHawking Zhang #define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 1274db3239f5SHawking Zhang #define XPB_P2P_BAR3__VALID__SHIFT 0xc 1275db3239f5SHawking Zhang #define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 1276db3239f5SHawking Zhang #define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 1277db3239f5SHawking Zhang #define XPB_P2P_BAR3__RESERVED__SHIFT 0xf 1278db3239f5SHawking Zhang #define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 1279db3239f5SHawking Zhang #define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL 1280db3239f5SHawking Zhang #define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L 1281db3239f5SHawking Zhang #define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L 1282db3239f5SHawking Zhang #define XPB_P2P_BAR3__VALID_MASK 0x00001000L 1283db3239f5SHawking Zhang #define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 1284db3239f5SHawking Zhang #define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 1285db3239f5SHawking Zhang #define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L 1286db3239f5SHawking Zhang #define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L 1287db3239f5SHawking Zhang //XPB_P2P_BAR4 1288db3239f5SHawking Zhang #define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 1289db3239f5SHawking Zhang #define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 1290db3239f5SHawking Zhang #define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 1291db3239f5SHawking Zhang #define XPB_P2P_BAR4__VALID__SHIFT 0xc 1292db3239f5SHawking Zhang #define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 1293db3239f5SHawking Zhang #define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 1294db3239f5SHawking Zhang #define XPB_P2P_BAR4__RESERVED__SHIFT 0xf 1295db3239f5SHawking Zhang #define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 1296db3239f5SHawking Zhang #define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL 1297db3239f5SHawking Zhang #define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L 1298db3239f5SHawking Zhang #define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L 1299db3239f5SHawking Zhang #define XPB_P2P_BAR4__VALID_MASK 0x00001000L 1300db3239f5SHawking Zhang #define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 1301db3239f5SHawking Zhang #define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 1302db3239f5SHawking Zhang #define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L 1303db3239f5SHawking Zhang #define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L 1304db3239f5SHawking Zhang //XPB_P2P_BAR5 1305db3239f5SHawking Zhang #define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 1306db3239f5SHawking Zhang #define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 1307db3239f5SHawking Zhang #define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 1308db3239f5SHawking Zhang #define XPB_P2P_BAR5__VALID__SHIFT 0xc 1309db3239f5SHawking Zhang #define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 1310db3239f5SHawking Zhang #define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 1311db3239f5SHawking Zhang #define XPB_P2P_BAR5__RESERVED__SHIFT 0xf 1312db3239f5SHawking Zhang #define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 1313db3239f5SHawking Zhang #define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL 1314db3239f5SHawking Zhang #define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L 1315db3239f5SHawking Zhang #define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L 1316db3239f5SHawking Zhang #define XPB_P2P_BAR5__VALID_MASK 0x00001000L 1317db3239f5SHawking Zhang #define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 1318db3239f5SHawking Zhang #define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 1319db3239f5SHawking Zhang #define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L 1320db3239f5SHawking Zhang #define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L 1321db3239f5SHawking Zhang //XPB_P2P_BAR6 1322db3239f5SHawking Zhang #define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 1323db3239f5SHawking Zhang #define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 1324db3239f5SHawking Zhang #define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 1325db3239f5SHawking Zhang #define XPB_P2P_BAR6__VALID__SHIFT 0xc 1326db3239f5SHawking Zhang #define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 1327db3239f5SHawking Zhang #define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 1328db3239f5SHawking Zhang #define XPB_P2P_BAR6__RESERVED__SHIFT 0xf 1329db3239f5SHawking Zhang #define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 1330db3239f5SHawking Zhang #define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL 1331db3239f5SHawking Zhang #define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L 1332db3239f5SHawking Zhang #define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L 1333db3239f5SHawking Zhang #define XPB_P2P_BAR6__VALID_MASK 0x00001000L 1334db3239f5SHawking Zhang #define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 1335db3239f5SHawking Zhang #define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 1336db3239f5SHawking Zhang #define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L 1337db3239f5SHawking Zhang #define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L 1338db3239f5SHawking Zhang //XPB_P2P_BAR7 1339db3239f5SHawking Zhang #define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 1340db3239f5SHawking Zhang #define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 1341db3239f5SHawking Zhang #define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 1342db3239f5SHawking Zhang #define XPB_P2P_BAR7__VALID__SHIFT 0xc 1343db3239f5SHawking Zhang #define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 1344db3239f5SHawking Zhang #define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 1345db3239f5SHawking Zhang #define XPB_P2P_BAR7__RESERVED__SHIFT 0xf 1346db3239f5SHawking Zhang #define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 1347db3239f5SHawking Zhang #define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL 1348db3239f5SHawking Zhang #define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L 1349db3239f5SHawking Zhang #define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L 1350db3239f5SHawking Zhang #define XPB_P2P_BAR7__VALID_MASK 0x00001000L 1351db3239f5SHawking Zhang #define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 1352db3239f5SHawking Zhang #define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 1353db3239f5SHawking Zhang #define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L 1354db3239f5SHawking Zhang #define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L 1355db3239f5SHawking Zhang //XPB_P2P_BAR_SETUP 1356db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 1357db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 1358db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 1359db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 1360db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 1361db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf 1362db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 1363db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL 1364db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L 1365db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 1366db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 1367db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 1368db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L 1369db3239f5SHawking Zhang #define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L 1370db3239f5SHawking Zhang //XPB_P2P_BAR_DELTA_ABOVE 1371db3239f5SHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 1372db3239f5SHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 1373db3239f5SHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL 1374db3239f5SHawking Zhang #define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L 1375db3239f5SHawking Zhang //XPB_P2P_BAR_DELTA_BELOW 1376db3239f5SHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 1377db3239f5SHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 1378db3239f5SHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL 1379db3239f5SHawking Zhang #define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L 1380db3239f5SHawking Zhang //XPB_PEER_SYS_BAR0 1381db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 1382db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 1383db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 1384db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 1385db3239f5SHawking Zhang //XPB_PEER_SYS_BAR1 1386db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 1387db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 1388db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 1389db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 1390db3239f5SHawking Zhang //XPB_PEER_SYS_BAR2 1391db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 1392db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 1393db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 1394db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 1395db3239f5SHawking Zhang //XPB_PEER_SYS_BAR3 1396db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 1397db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 1398db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 1399db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 1400db3239f5SHawking Zhang //XPB_PEER_SYS_BAR4 1401db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 1402db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 1403db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 1404db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL 1405db3239f5SHawking Zhang //XPB_PEER_SYS_BAR5 1406db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 1407db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 1408db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 1409db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL 1410db3239f5SHawking Zhang //XPB_PEER_SYS_BAR6 1411db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 1412db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 1413db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 1414db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL 1415db3239f5SHawking Zhang //XPB_PEER_SYS_BAR7 1416db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 1417db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 1418db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 1419db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL 1420db3239f5SHawking Zhang //XPB_PEER_SYS_BAR8 1421db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 1422db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 1423db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 1424db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL 1425db3239f5SHawking Zhang //XPB_PEER_SYS_BAR9 1426db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 1427db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 1428db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 1429db3239f5SHawking Zhang #define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL 1430db3239f5SHawking Zhang //XPB_XDMA_PEER_SYS_BAR0 1431db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 1432db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 1433db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L 1434db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 1435db3239f5SHawking Zhang //XPB_XDMA_PEER_SYS_BAR1 1436db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 1437db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 1438db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L 1439db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 1440db3239f5SHawking Zhang //XPB_XDMA_PEER_SYS_BAR2 1441db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 1442db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 1443db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L 1444db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 1445db3239f5SHawking Zhang //XPB_XDMA_PEER_SYS_BAR3 1446db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 1447db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 1448db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L 1449db3239f5SHawking Zhang #define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 1450db3239f5SHawking Zhang //XPB_CLK_GAT 1451db3239f5SHawking Zhang #define XPB_CLK_GAT__ONDLY__SHIFT 0x0 1452db3239f5SHawking Zhang #define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 1453db3239f5SHawking Zhang #define XPB_CLK_GAT__RDYDLY__SHIFT 0xc 1454db3239f5SHawking Zhang #define XPB_CLK_GAT__ENABLE__SHIFT 0x12 1455db3239f5SHawking Zhang #define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 1456db3239f5SHawking Zhang #define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL 1457db3239f5SHawking Zhang #define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L 1458db3239f5SHawking Zhang #define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L 1459db3239f5SHawking Zhang #define XPB_CLK_GAT__ENABLE_MASK 0x00040000L 1460db3239f5SHawking Zhang #define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 1461db3239f5SHawking Zhang //XPB_INTF_CFG 1462db3239f5SHawking Zhang #define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 1463db3239f5SHawking Zhang #define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 1464db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 1465db3239f5SHawking Zhang #define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 1466db3239f5SHawking Zhang #define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 1467db3239f5SHawking Zhang #define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 1468db3239f5SHawking Zhang #define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a 1469db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 1470db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 1471db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 1472db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f 1473db3239f5SHawking Zhang #define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL 1474db3239f5SHawking Zhang #define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L 1475db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L 1476db3239f5SHawking Zhang #define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L 1477db3239f5SHawking Zhang #define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L 1478db3239f5SHawking Zhang #define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L 1479db3239f5SHawking Zhang #define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L 1480db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 1481db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 1482db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 1483db3239f5SHawking Zhang #define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L 1484db3239f5SHawking Zhang //XPB_INTF_STS 1485db3239f5SHawking Zhang #define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 1486db3239f5SHawking Zhang #define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 1487db3239f5SHawking Zhang #define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 1488db3239f5SHawking Zhang #define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 1489db3239f5SHawking Zhang #define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 1490db3239f5SHawking Zhang #define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 1491db3239f5SHawking Zhang #define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 1492db3239f5SHawking Zhang #define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL 1493db3239f5SHawking Zhang #define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L 1494db3239f5SHawking Zhang #define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 1495db3239f5SHawking Zhang #define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 1496db3239f5SHawking Zhang #define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 1497db3239f5SHawking Zhang #define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 1498db3239f5SHawking Zhang #define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L 1499db3239f5SHawking Zhang //XPB_PIPE_STS 1500db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 1501db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 1502db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 1503db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 1504db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 1505db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 1506db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 1507db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 1508db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 1509db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 1510db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 1511db3239f5SHawking Zhang #define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 1512db3239f5SHawking Zhang #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 1513db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 1514db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL 1515db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L 1516db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 1517db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 1518db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 1519db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 1520db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 1521db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 1522db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 1523db3239f5SHawking Zhang #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 1524db3239f5SHawking Zhang #define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 1525db3239f5SHawking Zhang #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L 1526db3239f5SHawking Zhang //XPB_SUB_CTRL 1527db3239f5SHawking Zhang #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 1528db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 1529db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 1530db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 1531db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 1532db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 1533db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 1534db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 1535db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 1536db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 1537db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 1538db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 1539db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 1540db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 1541db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 1542db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 1543db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 1544db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 1545db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 1546db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 1547db3239f5SHawking Zhang #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 1548db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 1549db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 1550db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 1551db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 1552db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 1553db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 1554db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 1555db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 1556db3239f5SHawking Zhang #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 1557db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 1558db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 1559db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 1560db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 1561db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 1562db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 1563db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 1564db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 1565db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 1566db3239f5SHawking Zhang #define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 1567db3239f5SHawking Zhang //XPB_MAP_INVERT_FLUSH_NUM_LSB 1568db3239f5SHawking Zhang #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 1569db3239f5SHawking Zhang #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL 1570db3239f5SHawking Zhang //XPB_PERF_KNOBS 1571db3239f5SHawking Zhang #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 1572db3239f5SHawking Zhang #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 1573db3239f5SHawking Zhang #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 1574db3239f5SHawking Zhang #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL 1575db3239f5SHawking Zhang #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L 1576db3239f5SHawking Zhang #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L 1577db3239f5SHawking Zhang //XPB_STICKY 1578db3239f5SHawking Zhang #define XPB_STICKY__BITS__SHIFT 0x0 1579db3239f5SHawking Zhang #define XPB_STICKY__BITS_MASK 0xFFFFFFFFL 1580db3239f5SHawking Zhang //XPB_STICKY_W1C 1581db3239f5SHawking Zhang #define XPB_STICKY_W1C__BITS__SHIFT 0x0 1582db3239f5SHawking Zhang #define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL 1583db3239f5SHawking Zhang //XPB_MISC_CFG 1584db3239f5SHawking Zhang #define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 1585db3239f5SHawking Zhang #define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 1586db3239f5SHawking Zhang #define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 1587db3239f5SHawking Zhang #define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 1588db3239f5SHawking Zhang #define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 1589db3239f5SHawking Zhang #define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL 1590db3239f5SHawking Zhang #define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L 1591db3239f5SHawking Zhang #define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L 1592db3239f5SHawking Zhang #define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L 1593db3239f5SHawking Zhang #define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 1594db3239f5SHawking Zhang //XPB_INTF_CFG2 1595db3239f5SHawking Zhang #define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 1596db3239f5SHawking Zhang #define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL 1597db3239f5SHawking Zhang //XPB_CLG_EXTRA_RD 1598db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 1599db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 1600db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb 1601db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc 1602db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf 1603db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 1604db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a 1605db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b 1606db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL 1607db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L 1608db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L 1609db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L 1610db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L 1611db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L 1612db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L 1613db3239f5SHawking Zhang #define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L 1614db3239f5SHawking Zhang //XPB_CLG_EXTRA_MSK_RD 1615db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 1616db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 1617db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb 1618db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 1619db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL 1620db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L 1621db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L 1622db3239f5SHawking Zhang #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L 1623db3239f5SHawking Zhang //XPB_CLG_GFX_MATCH 1624db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 1625db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 1626db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc 1627db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 1628db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 1629db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 1630db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a 1631db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b 1632db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1633db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 1634db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L 1635db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 1636db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L 1637db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L 1638db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L 1639db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L 1640db3239f5SHawking Zhang //XPB_CLG_GFX_MATCH_MSK 1641db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1642db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 1643db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 1644db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 1645db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1646db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 1647db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 1648db3239f5SHawking Zhang #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 1649db3239f5SHawking Zhang //XPB_CLG_MM_MATCH 1650db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 1651db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 1652db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0xc 1653db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0xd 1654db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1655db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 1656db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x00001000L 1657db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x00002000L 1658db3239f5SHawking Zhang //XPB_CLG_MM_MATCH_MSK 1659db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1660db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 1661db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1662db3239f5SHawking Zhang #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 1663db3239f5SHawking Zhang //XPB_CLG_GUS_MATCH 1664db3239f5SHawking Zhang #define XPB_CLG_GUS_MATCH__FARBIRC0_ID__SHIFT 0x0 1665db3239f5SHawking Zhang #define XPB_CLG_GUS_MATCH__FARBIRC0_VLD__SHIFT 0x6 1666db3239f5SHawking Zhang #define XPB_CLG_GUS_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1667db3239f5SHawking Zhang #define XPB_CLG_GUS_MATCH__FARBIRC0_VLD_MASK 0x00000040L 1668db3239f5SHawking Zhang //XPB_CLG_GUS_MATCH_MSK 1669db3239f5SHawking Zhang #define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1670db3239f5SHawking Zhang #define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1671db3239f5SHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING0 1672db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1673db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1674db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1675db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1676db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1677db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1678db3239f5SHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING1 1679db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1680db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1681db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1682db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1683db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1684db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1685db3239f5SHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING2 1686db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1687db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1688db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1689db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1690db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1691db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1692db3239f5SHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING3 1693db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1694db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1695db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1696db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1697db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1698db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1699db3239f5SHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING4 1700db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 1701db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 1702db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 1703db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL 1704db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L 1705db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L 1706db3239f5SHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING5 1707db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 1708db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 1709db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 1710db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL 1711db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L 1712db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L 1713db3239f5SHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING6 1714db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 1715db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 1716db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 1717db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL 1718db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L 1719db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L 1720db3239f5SHawking Zhang //XPB_CLG_GFX_UNITID_MAPPING7 1721db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 1722db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 1723db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 1724db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL 1725db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L 1726db3239f5SHawking Zhang #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L 1727db3239f5SHawking Zhang //XPB_CLG_MM_UNITID_MAPPING0 1728db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1729db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1730db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1731db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1732db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1733db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1734db3239f5SHawking Zhang //XPB_CLG_MM_UNITID_MAPPING1 1735db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1736db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1737db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1738db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1739db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1740db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1741db3239f5SHawking Zhang //XPB_CLG_MM_UNITID_MAPPING2 1742db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1743db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1744db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1745db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1746db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1747db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1748db3239f5SHawking Zhang //XPB_CLG_MM_UNITID_MAPPING3 1749db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1750db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1751db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1752db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1753db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1754db3239f5SHawking Zhang #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1755db3239f5SHawking Zhang //XPB_CLG_GUS_UNITID_MAPPING0 1756db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1757db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1758db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1759db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1760db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1761db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1762db3239f5SHawking Zhang //XPB_CLG_GUS_UNITID_MAPPING1 1763db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1764db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1765db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1766db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1767db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1768db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1769db3239f5SHawking Zhang //XPB_CLG_GUS_UNITID_MAPPING2 1770db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1771db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1772db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1773db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1774db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1775db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1776db3239f5SHawking Zhang //XPB_CLG_GUS_UNITID_MAPPING3 1777db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1778db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1779db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1780db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1781db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1782db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1783db3239f5SHawking Zhang //XPB_CLG_GUS_UNITID_MAPPING4 1784db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 1785db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 1786db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 1787db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL 1788db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L 1789db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L 1790db3239f5SHawking Zhang //XPB_CLG_GUS_UNITID_MAPPING5 1791db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 1792db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 1793db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 1794db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL 1795db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L 1796db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L 1797db3239f5SHawking Zhang //XPB_CLG_GUS_UNITID_MAPPING6 1798db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 1799db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 1800db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 1801db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL 1802db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L 1803db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L 1804db3239f5SHawking Zhang //XPB_CLG_GUS_UNITID_MAPPING7 1805db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 1806db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 1807db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 1808db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL 1809db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L 1810db3239f5SHawking Zhang #define XPB_CLG_GUS_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L 1811db3239f5SHawking Zhang 1812db3239f5SHawking Zhang 1813db3239f5SHawking Zhang // addressBlock: athub_rpbdec 1814db3239f5SHawking Zhang //RPB_PASSPW_CONF 1815db3239f5SHawking Zhang #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 1816db3239f5SHawking Zhang #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 1817db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 1818db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 1819db3239f5SHawking Zhang #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 1820db3239f5SHawking Zhang #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 1821db3239f5SHawking Zhang #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 1822db3239f5SHawking Zhang #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 1823db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 1824db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 1825db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa 1826db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb 1827db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc 1828db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd 1829db3239f5SHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe 1830db3239f5SHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf 1831db3239f5SHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 1832db3239f5SHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 1833db3239f5SHawking Zhang #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L 1834db3239f5SHawking Zhang #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L 1835db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L 1836db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L 1837db3239f5SHawking Zhang #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L 1838db3239f5SHawking Zhang #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L 1839db3239f5SHawking Zhang #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L 1840db3239f5SHawking Zhang #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L 1841db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L 1842db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L 1843db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L 1844db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L 1845db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L 1846db3239f5SHawking Zhang #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L 1847db3239f5SHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L 1848db3239f5SHawking Zhang #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L 1849db3239f5SHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L 1850db3239f5SHawking Zhang #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L 1851db3239f5SHawking Zhang //RPB_BLOCKLEVEL_CONF 1852db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 1853db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2 1854db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4 1855db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6 1856db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8 1857db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa 1858db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc 1859db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe 1860db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf 1861db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 1862db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 1863db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L 1864db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL 1865db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L 1866db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L 1867db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L 1868db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L 1869db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L 1870db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L 1871db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L 1872db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L 1873db3239f5SHawking Zhang #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L 1874db3239f5SHawking Zhang //RPB_TAG_CONF 1875db3239f5SHawking Zhang #define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0 1876db3239f5SHawking Zhang #define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0xa 1877db3239f5SHawking Zhang #define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x14 1878db3239f5SHawking Zhang #define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000003FFL 1879db3239f5SHawking Zhang #define RPB_TAG_CONF__RPB_IO_WR_MASK 0x000FFC00L 1880db3239f5SHawking Zhang #define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x3FF00000L 1881db3239f5SHawking Zhang //RPB_EFF_CNTL 1882db3239f5SHawking Zhang #define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 1883db3239f5SHawking Zhang #define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 1884db3239f5SHawking Zhang #define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL 1885db3239f5SHawking Zhang #define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L 1886db3239f5SHawking Zhang //RPB_ARB_CNTL 1887db3239f5SHawking Zhang #define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 1888db3239f5SHawking Zhang #define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 1889db3239f5SHawking Zhang #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 1890db3239f5SHawking Zhang #define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 1891db3239f5SHawking Zhang #define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 1892db3239f5SHawking Zhang #define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL 1893db3239f5SHawking Zhang #define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L 1894db3239f5SHawking Zhang #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L 1895db3239f5SHawking Zhang #define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L 1896db3239f5SHawking Zhang #define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L 1897db3239f5SHawking Zhang //RPB_ARB_CNTL2 1898db3239f5SHawking Zhang #define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 1899db3239f5SHawking Zhang #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 1900db3239f5SHawking Zhang #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 1901db3239f5SHawking Zhang #define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL 1902db3239f5SHawking Zhang #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L 1903db3239f5SHawking Zhang #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L 1904db3239f5SHawking Zhang //RPB_BIF_CNTL 1905db3239f5SHawking Zhang #define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 1906db3239f5SHawking Zhang #define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 1907db3239f5SHawking Zhang #define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10 1908db3239f5SHawking Zhang #define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11 1909db3239f5SHawking Zhang #define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12 1910db3239f5SHawking Zhang #define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13 1911db3239f5SHawking Zhang #define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b 1912db3239f5SHawking Zhang #define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c 1913db3239f5SHawking Zhang #define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d 1914db3239f5SHawking Zhang #define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e 1915db3239f5SHawking Zhang #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN__SHIFT 0x1f 1916db3239f5SHawking Zhang #define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL 1917db3239f5SHawking Zhang #define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L 1918db3239f5SHawking Zhang #define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L 1919db3239f5SHawking Zhang #define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L 1920db3239f5SHawking Zhang #define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L 1921db3239f5SHawking Zhang #define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L 1922db3239f5SHawking Zhang #define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L 1923db3239f5SHawking Zhang #define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L 1924db3239f5SHawking Zhang #define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L 1925db3239f5SHawking Zhang #define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L 1926db3239f5SHawking Zhang #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN_MASK 0x80000000L 1927db3239f5SHawking Zhang //RPB_WR_SWITCH_CNTL 1928db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 1929db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 1930db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 1931db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 1932db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 1933db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__WORKLOAD_ADJUST_EN__SHIFT 0x1d 1934db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__WEIGHT_ADJUST_STEP__SHIFT 0x1e 1935db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 1936db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 1937db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 1938db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 1939db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 1940db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__WORKLOAD_ADJUST_EN_MASK 0x20000000L 1941db3239f5SHawking Zhang #define RPB_WR_SWITCH_CNTL__WEIGHT_ADJUST_STEP_MASK 0xC0000000L 1942db3239f5SHawking Zhang //RPB_WR_COMBINE_CNTL 1943db3239f5SHawking Zhang #define RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x0 1944db3239f5SHawking Zhang #define RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x2 1945db3239f5SHawking Zhang #define RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x6 1946db3239f5SHawking Zhang #define RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x00000003L 1947db3239f5SHawking Zhang #define RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x0000003CL 1948db3239f5SHawking Zhang #define RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x00000040L 1949db3239f5SHawking Zhang //RPB_RD_SWITCH_CNTL 1950db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 1951db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 1952db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 1953db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 1954db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 1955db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__WORKLOAD_ADJUST_EN__SHIFT 0x1d 1956db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__WEIGHT_ADJUST_STEP__SHIFT 0x1e 1957db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 1958db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 1959db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 1960db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 1961db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 1962db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__WORKLOAD_ADJUST_EN_MASK 0x20000000L 1963db3239f5SHawking Zhang #define RPB_RD_SWITCH_CNTL__WEIGHT_ADJUST_STEP_MASK 0xC0000000L 1964db3239f5SHawking Zhang //RPB_CID_QUEUE_WR 1965db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 1966db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 1967db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb 1968db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc 1969db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf 1970db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 1971db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL 1972db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L 1973db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L 1974db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L 1975db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L 1976db3239f5SHawking Zhang #define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L 1977db3239f5SHawking Zhang //RPB_CID_QUEUE_RD 1978db3239f5SHawking Zhang #define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 1979db3239f5SHawking Zhang #define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 1980db3239f5SHawking Zhang #define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb 1981db3239f5SHawking Zhang #define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe 1982db3239f5SHawking Zhang #define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL 1983db3239f5SHawking Zhang #define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L 1984db3239f5SHawking Zhang #define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L 1985db3239f5SHawking Zhang #define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L 1986db3239f5SHawking Zhang //RPB_PERF_COUNTER_CNTL 1987db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1988db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 1989db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 1990db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 1991db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 1992db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 1993db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe 1994db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 1995db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 1996db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 1997db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L 1998db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L 1999db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L 2000db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001E0L 2001db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003E00L 2002db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007C000L 2003db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00F80000L 2004db3239f5SHawking Zhang #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1F000000L 2005db3239f5SHawking Zhang //RPB_PERF_COUNTER_STATUS 2006db3239f5SHawking Zhang #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 2007db3239f5SHawking Zhang #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xFFFFFFFFL 2008db3239f5SHawking Zhang //RPB_CID_QUEUE_EX 2009db3239f5SHawking Zhang #define RPB_CID_QUEUE_EX__START__SHIFT 0x0 2010db3239f5SHawking Zhang #define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 2011db3239f5SHawking Zhang #define RPB_CID_QUEUE_EX__START_MASK 0x00000001L 2012db3239f5SHawking Zhang #define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL 2013db3239f5SHawking Zhang //RPB_CID_QUEUE_EX_DATA 2014db3239f5SHawking Zhang #define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 2015db3239f5SHawking Zhang #define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 2016db3239f5SHawking Zhang #define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL 2017db3239f5SHawking Zhang #define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L 2018db3239f5SHawking Zhang //RPB_SWITCH_CNTL2 2019db3239f5SHawking Zhang #define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 2020db3239f5SHawking Zhang #define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 2021db3239f5SHawking Zhang #define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe 2022db3239f5SHawking Zhang #define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 2023db3239f5SHawking Zhang #define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL 2024db3239f5SHawking Zhang #define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L 2025db3239f5SHawking Zhang #define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L 2026db3239f5SHawking Zhang #define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L 2027db3239f5SHawking Zhang //RPB_DEINTRLV_COMBINE_CNTL 2028db3239f5SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 2029db3239f5SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 2030db3239f5SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 2031db3239f5SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD__SHIFT 0x6 2032db3239f5SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL 2033db3239f5SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L 2034db3239f5SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L 2035db3239f5SHawking Zhang #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD_MASK 0x00003FC0L 2036db3239f5SHawking Zhang //RPB_VC_SWITCH_RDWR 2037db3239f5SHawking Zhang #define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 2038db3239f5SHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 2039db3239f5SHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa 2040db3239f5SHawking Zhang #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD__SHIFT 0x12 2041db3239f5SHawking Zhang #define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L 2042db3239f5SHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL 2043db3239f5SHawking Zhang #define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L 2044db3239f5SHawking Zhang #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD_MASK 0x03FC0000L 2045db3239f5SHawking Zhang //RPB_PERFCOUNTER_LO 2046db3239f5SHawking Zhang #define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 2047db3239f5SHawking Zhang #define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 2048db3239f5SHawking Zhang //RPB_PERFCOUNTER_HI 2049db3239f5SHawking Zhang #define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 2050db3239f5SHawking Zhang #define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 2051db3239f5SHawking Zhang #define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 2052db3239f5SHawking Zhang #define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 2053db3239f5SHawking Zhang //RPB_PERFCOUNTER0_CFG 2054db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 2055db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 2056db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 2057db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 2058db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 2059db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 2060db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 2061db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 2062db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 2063db3239f5SHawking Zhang #define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 2064db3239f5SHawking Zhang //RPB_PERFCOUNTER1_CFG 2065db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 2066db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 2067db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 2068db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 2069db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 2070db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 2071db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 2072db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 2073db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 2074db3239f5SHawking Zhang #define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 2075db3239f5SHawking Zhang //RPB_PERFCOUNTER2_CFG 2076db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 2077db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 2078db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 2079db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 2080db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 2081db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 2082db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 2083db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 2084db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 2085db3239f5SHawking Zhang #define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 2086db3239f5SHawking Zhang //RPB_PERFCOUNTER3_CFG 2087db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 2088db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 2089db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 2090db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 2091db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 2092db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 2093db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 2094db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 2095db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 2096db3239f5SHawking Zhang #define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 2097db3239f5SHawking Zhang //RPB_PERFCOUNTER_RSLT_CNTL 2098db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 2099db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 2100db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 2101db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 2102db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 2103db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 2104db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 2105db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 2106db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 2107db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 2108db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 2109db3239f5SHawking Zhang #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 2110db3239f5SHawking Zhang //RPB_BIF_CNTL2 2111db3239f5SHawking Zhang #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN__SHIFT 0x0 2112db3239f5SHawking Zhang #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN_MASK 0x00000001L 2113db3239f5SHawking Zhang //RPB_RD_QUEUE_CNTL 2114db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 2115db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 2116db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 2117db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 2118db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 2119db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 2120db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 2121db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 2122db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 2123db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 2124db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 2125db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 2126db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 2127db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 2128db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 2129db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 2130db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 2131db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 2132db3239f5SHawking Zhang //RPB_RD_QUEUE_CNTL2 2133db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 2134db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 2135db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 2136db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 2137db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 2138db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 2139db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 2140db3239f5SHawking Zhang #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 2141db3239f5SHawking Zhang //RPB_WR_QUEUE_CNTL 2142db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 2143db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 2144db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 2145db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 2146db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 2147db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 2148db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 2149db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 2150db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 2151db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 2152db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 2153db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 2154db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 2155db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 2156db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 2157db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 2158db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 2159db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 2160db3239f5SHawking Zhang //RPB_WR_QUEUE_CNTL2 2161db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 2162db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 2163db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 2164db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 2165db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 2166db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 2167db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 2168db3239f5SHawking Zhang #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 2169db3239f5SHawking Zhang //RPB_EA_QUEUE_WR 2170db3239f5SHawking Zhang #define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 2171db3239f5SHawking Zhang #define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 2172db3239f5SHawking Zhang #define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 2173db3239f5SHawking Zhang #define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb 2174db3239f5SHawking Zhang #define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL 2175db3239f5SHawking Zhang #define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L 2176db3239f5SHawking Zhang #define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L 2177db3239f5SHawking Zhang #define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L 2178db3239f5SHawking Zhang //RPB_ATS_CNTL 2179db3239f5SHawking Zhang #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 2180db3239f5SHawking Zhang #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 2181db3239f5SHawking Zhang #define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 2182db3239f5SHawking Zhang #define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 2183db3239f5SHawking Zhang #define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf 2184db3239f5SHawking Zhang #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 2185db3239f5SHawking Zhang #define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 2186db3239f5SHawking Zhang #define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 2187db3239f5SHawking Zhang #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L 2188db3239f5SHawking Zhang #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L 2189db3239f5SHawking Zhang #define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL 2190db3239f5SHawking Zhang #define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L 2191db3239f5SHawking Zhang #define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L 2192db3239f5SHawking Zhang #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L 2193db3239f5SHawking Zhang #define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L 2194db3239f5SHawking Zhang #define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L 2195db3239f5SHawking Zhang //RPB_ATS_CNTL2 2196db3239f5SHawking Zhang #define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 2197db3239f5SHawking Zhang #define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 2198db3239f5SHawking Zhang #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc 2199db3239f5SHawking Zhang #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf 2200db3239f5SHawking Zhang #define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 2201db3239f5SHawking Zhang #define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL 2202db3239f5SHawking Zhang #define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L 2203db3239f5SHawking Zhang #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L 2204db3239f5SHawking Zhang #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L 2205db3239f5SHawking Zhang #define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L 2206db3239f5SHawking Zhang //RPB_DF_SDPPORT_CNTL 2207db3239f5SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD__SHIFT 0x0 2208db3239f5SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD__SHIFT 0x6 2209db3239f5SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD__SHIFT 0xc 2210db3239f5SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD_MASK 0x0000003FL 2211db3239f5SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD_MASK 0x00000FC0L 2212db3239f5SHawking Zhang #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD_MASK 0x0000F000L 2213db3239f5SHawking Zhang //RPB_SDPPORT_CNTL 2214db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 2215db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 2216db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 2217db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 2218db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 2219db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 2220db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa 2221db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb 2222db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd 2223db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe 2224db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf 2225db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 2226db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 2227db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 2228db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 2229db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 2230db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 2231db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 2232db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 2233db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 2234db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L 2235db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L 2236db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L 2237db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L 2238db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L 2239db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L 2240db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L 2241db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L 2242db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L 2243db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L 2244db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L 2245db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L 2246db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L 2247db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L 2248db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 2249db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 2250db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 2251db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 2252db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 2253db3239f5SHawking Zhang #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 2254db3239f5SHawking Zhang //RPB_NBIF_SDPPORT_CNTL 2255db3239f5SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD__SHIFT 0x0 2256db3239f5SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD__SHIFT 0x8 2257db3239f5SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD__SHIFT 0x10 2258db3239f5SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD__SHIFT 0x18 2259db3239f5SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD_MASK 0x000000FFL 2260db3239f5SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD_MASK 0x0000FF00L 2261db3239f5SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD_MASK 0x00FF0000L 2262db3239f5SHawking Zhang #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD_MASK 0xFF000000L 2263db3239f5SHawking Zhang 2264db3239f5SHawking Zhang #endif 2265