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/openbmc/linux/Documentation/devicetree/bindings/arm/omap/
H A Dprm-inst.txt21 - #power-domain-cells: Should be 0 if the instance is a power domain provider.
28 reg = <0x1b00 0x40>;
29 #power-domain-cells = <0>;
/openbmc/linux/arch/arm/mach-omap2/
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/openbmc/linux/drivers/net/ethernet/qualcomm/
H A Dqca_7k.h35 #define QCA7K_SPI_WRITE (0 << 15)
37 #define QCA7K_SPI_EXTERNAL (0 << 14)
41 #define QCASPI_HW_BUF_LEN 0xC5B
44 #define SPI_REG_BFR_SIZE 0x0100
45 #define SPI_REG_WRBUF_SPC_AVA 0x0200
46 #define SPI_REG_RDBUF_BYTE_AVA 0x0300
47 #define SPI_REG_SPI_CONFIG 0x0400
48 #define SPI_REG_SPI_STATUS 0x0500
49 #define SPI_REG_INTR_CAUSE 0x0C00
50 #define SPI_REG_INTR_ENABLE 0x0D00
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap4/
H A Dcpu.h19 u32 tidr; /* 0x00 r */
20 u8 res[0xc];
21 u32 tiocp_cfg; /* 0x10 rw */
22 u32 tistat; /* 0x14 r */
23 u32 tisr; /* 0x18 rw */
24 u32 tier; /* 0x1c rw */
25 u32 twer; /* 0x20 rw */
26 u32 tclr; /* 0x24 rw */
27 u32 tcrr; /* 0x28 rw */
28 u32 tldr; /* 0x2c rw */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dcpu.h23 u32 tidr; /* 0x00 r */
24 u8 res1[0xc];
25 u32 tiocp_cfg; /* 0x10 rw */
26 u8 res2[0x10];
27 u32 tisr_raw; /* 0x24 r */
28 u32 tisr; /* 0x28 rw */
29 u32 tier; /* 0x2c rw */
30 u32 ticr; /* 0x30 rw */
31 u32 twer; /* 0x34 rw */
32 u32 tclr; /* 0x38 rw */
[all …]
/openbmc/u-boot/fs/ext4/
H A Dcrc16.c13 /** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */
15 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
16 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
17 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
18 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
19 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
20 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
21 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
22 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
23 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/linux/lib/
H A Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/u-boot/fs/ubifs/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/linux/drivers/gpu/host1x/
H A Ddev.c90 .sync_offset = 0x3000,
94 .num_sid_entries = 0,
105 .sync_offset = 0x3000,
109 .num_sid_entries = 0,
120 .sync_offset = 0x2100,
124 .num_sid_entries = 0,
135 .sync_offset = 0x2100,
139 .num_sid_entries = 0,
147 .base = 0x1af0,
148 .offset = 0x30,
[all …]
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dstart.S44 bic r0,r0,#0x1f
45 orr r0,r0,#0xd3
100 mov r0, #0
101 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
102 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
107 mrc p15, 0, r0, c1, c0, 0
108 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
109 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
110 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
111 mcr p15, 0, r0, c1, c0, 0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dboard_env_spec.h12 #define MV_6710_DEV_ID 0x6710
14 #define MV_6710_Z1_REV 0x0
19 #define MV_78130_DEV_ID 0x7813
20 #define MV_78160_DEV_ID 0x7816
21 #define MV_78230_DEV_ID 0x7823
22 #define MV_78260_DEV_ID 0x7826
23 #define MV_78460_DEV_ID 0x7846
24 #define MV_78000_DEV_ID 0x7888
26 #define MV_FPGA_DEV_ID 0x2107
28 #define MV_78XX0_Z1_REV 0x0
[all …]
/openbmc/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac.h17 #define EMAC_DMA_MAS_CTRL 0x1400
18 #define EMAC_IRQ_MOD_TIM_INIT 0x1408
19 #define EMAC_BLK_IDLE_STS 0x140c
20 #define EMAC_PHY_LINK_DELAY 0x141c
21 #define EMAC_SYS_ALIV_CTRL 0x1434
22 #define EMAC_MAC_CTRL 0x1480
23 #define EMAC_MAC_IPGIFG_CTRL 0x1484
24 #define EMAC_MAC_STA_ADDR0 0x1488
25 #define EMAC_MAC_STA_ADDR1 0x148c
26 #define EMAC_HASH_TAB_REG0 0x1490
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c.h11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
20 u8 res0[0x4a]; /* 0x120 */
21 u8 mac_addr[ETH_ALEN]; /* 0x16a */
25 u8 mac_addr[ETH_ALEN]; /* 0x120 */
33 u8 ltr_cap; /* 0x133 */
38 u8 res0:2; /* 0x144 */
62 u8 res0[0x0e];
[all …]
/openbmc/linux/drivers/mfd/
H A Dintel_pmc_bxt.c38 #define PLAT_RESOURCE_IPC_INDEX 0
39 #define PLAT_RESOURCE_IPC_SIZE 0x1000
40 #define PLAT_RESOURCE_GCR_OFFSET 0x1000
41 #define PLAT_RESOURCE_GCR_SIZE 0x1000
49 #define PLAT_RESOURCE_ACPI_IO_INDEX 0
57 #define SMI_EN_OFFSET 0x0040
59 #define TCO_BASE_OFFSET 0x0060
62 #define TELEM_PMC_SSRAM_OFFSET 0x1b00
63 #define TELEM_PUNIT_SSRAM_OFFSET 0x1a00
66 #define PMC_NORTHPEAK_CTRL 0xed
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/
H A Ddebug.c80 int max = 0xff; in rtl_debug_get_mac_page()
82 for (n = 0; n <= max; ) { in rtl_debug_get_mac_page()
84 for (i = 0; i < 4 && n <= max; i++, n += 4) in rtl_debug_get_mac_page()
89 return 0; in rtl_debug_get_mac_page()
98 RTL_DEBUG_IMPL_MAC_SERIES(0, 0x0000);
99 RTL_DEBUG_IMPL_MAC_SERIES(1, 0x0100);
100 RTL_DEBUG_IMPL_MAC_SERIES(2, 0x0200);
101 RTL_DEBUG_IMPL_MAC_SERIES(3, 0x0300);
102 RTL_DEBUG_IMPL_MAC_SERIES(4, 0x0400);
103 RTL_DEBUG_IMPL_MAC_SERIES(5, 0x0500);
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb4_regs.h32 * stacks, thus for PEC2, the global registers are at offset 0, the
33 * PHB3 registers at offset 0x40, the PHB4 at offset 0x80 etc....
36 * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc..
38 #define PEC_STACK_OFFSET 0x40
41 #define PEC_NEST_PBCQ_HW_CONFIG 0x00
42 #define PEC_NEST_DROP_PRIO_CTRL 0x01
43 #define PEC_NEST_PBCQ_ERR_INJECT 0x02
44 #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03
45 #define PEC_NEST_PBCQ_PMON_CTRL 0x04
46 #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx93.c58 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
59 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
60 { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
61 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
62 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
63 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
64 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
65 { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
66 { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, },
67 { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dperf_event.h17 #define MSR_ARCH_PERFMON_PERFCTR0 0xc1
18 #define MSR_ARCH_PERFMON_PERFCTR1 0xc2
20 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186
21 #define MSR_ARCH_PERFMON_EVENTSEL1 0x187
23 #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
24 #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
33 #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
35 #define INTEL_FIXED_BITS_MASK 0xFULL
37 #define INTEL_FIXED_0_KERNEL (1ULL << 0)
56 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dstart.S11 * The processor starts at 0x00000100 and the code is executed
21 * address and (s)dram will be positioned at address 0
64 .long 0x27051956 /* U-Boot Magic Number */
67 .ascii U_BOOT_VERSION_STRING, "\0"
138 li r2, 0x0007
159 ori r4, r4, (0x2000 - 4)
160 li r0, (0x2000 / 4)
162 li r0, 0
187 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
190 STD_EXCEPTION(0x300, DataStorage, UnknownException)
[all …]
/openbmc/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/openbmc/linux/drivers/media/usb/gspca/
H A Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
[all …]
/openbmc/linux/drivers/net/ethernet/atheros/alx/
H A Dreg.h38 #define ALX_DEV_ID_AR8161 0x1091
39 #define ALX_DEV_ID_E2200 0xe091
40 #define ALX_DEV_ID_E2400 0xe0a1
41 #define ALX_DEV_ID_E2500 0xe0b1
42 #define ALX_DEV_ID_AR8162 0x1090
43 #define ALX_DEV_ID_AR8171 0x10A1
44 #define ALX_DEV_ID_AR8172 0x10A0
47 * bit(0): with xD support
52 #define ALX_REV_A0 0
57 #define ALX_DEV_CTRL 0x0060
[all …]

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