125f1ca31SMika Westerberg // SPDX-License-Identifier: GPL-2.0
225f1ca31SMika Westerberg /*
325f1ca31SMika Westerberg * Driver for the Intel Broxton PMC
425f1ca31SMika Westerberg *
525f1ca31SMika Westerberg * (C) Copyright 2014 - 2020 Intel Corporation
625f1ca31SMika Westerberg *
725f1ca31SMika Westerberg * This driver is based on Intel SCU IPC driver (intel_scu_ipc.c) by
825f1ca31SMika Westerberg * Sreedhara DS <sreedhara.ds@intel.com>
925f1ca31SMika Westerberg *
1025f1ca31SMika Westerberg * The PMC (Power Management Controller) running on the ARC processor
1125f1ca31SMika Westerberg * communicates with another entity running in the IA (Intel Architecture)
1225f1ca31SMika Westerberg * core through an IPC (Intel Processor Communications) mechanism which in
1325f1ca31SMika Westerberg * turn sends messages between the IA and the PMC.
1425f1ca31SMika Westerberg */
1525f1ca31SMika Westerberg
1625f1ca31SMika Westerberg #include <linux/acpi.h>
1725f1ca31SMika Westerberg #include <linux/delay.h>
1825f1ca31SMika Westerberg #include <linux/errno.h>
1925f1ca31SMika Westerberg #include <linux/interrupt.h>
2025f1ca31SMika Westerberg #include <linux/io-64-nonatomic-lo-hi.h>
2125f1ca31SMika Westerberg #include <linux/mfd/core.h>
2225f1ca31SMika Westerberg #include <linux/mfd/intel_pmc_bxt.h>
2325f1ca31SMika Westerberg #include <linux/module.h>
2425f1ca31SMika Westerberg #include <linux/platform_device.h>
2525f1ca31SMika Westerberg #include <linux/platform_data/itco_wdt.h>
2625f1ca31SMika Westerberg
2725f1ca31SMika Westerberg #include <asm/intel_scu_ipc.h>
2825f1ca31SMika Westerberg
2925f1ca31SMika Westerberg /* Residency with clock rate at 19.2MHz to usecs */
3025f1ca31SMika Westerberg #define S0IX_RESIDENCY_IN_USECS(d, s) \
3125f1ca31SMika Westerberg ({ \
3225f1ca31SMika Westerberg u64 result = 10ull * ((d) + (s)); \
3325f1ca31SMika Westerberg do_div(result, 192); \
3425f1ca31SMika Westerberg result; \
3525f1ca31SMika Westerberg })
3625f1ca31SMika Westerberg
3725f1ca31SMika Westerberg /* Resources exported from IFWI */
3825f1ca31SMika Westerberg #define PLAT_RESOURCE_IPC_INDEX 0
3925f1ca31SMika Westerberg #define PLAT_RESOURCE_IPC_SIZE 0x1000
4025f1ca31SMika Westerberg #define PLAT_RESOURCE_GCR_OFFSET 0x1000
4125f1ca31SMika Westerberg #define PLAT_RESOURCE_GCR_SIZE 0x1000
4225f1ca31SMika Westerberg #define PLAT_RESOURCE_BIOS_DATA_INDEX 1
4325f1ca31SMika Westerberg #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
4425f1ca31SMika Westerberg #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3
4525f1ca31SMika Westerberg #define PLAT_RESOURCE_ISP_DATA_INDEX 4
4625f1ca31SMika Westerberg #define PLAT_RESOURCE_ISP_IFACE_INDEX 5
4725f1ca31SMika Westerberg #define PLAT_RESOURCE_GTD_DATA_INDEX 6
4825f1ca31SMika Westerberg #define PLAT_RESOURCE_GTD_IFACE_INDEX 7
4925f1ca31SMika Westerberg #define PLAT_RESOURCE_ACPI_IO_INDEX 0
5025f1ca31SMika Westerberg
5125f1ca31SMika Westerberg /*
5225f1ca31SMika Westerberg * BIOS does not create an ACPI device for each PMC function, but
5325f1ca31SMika Westerberg * exports multiple resources from one ACPI device (IPC) for multiple
5425f1ca31SMika Westerberg * functions. This driver is responsible for creating a child device and
5525f1ca31SMika Westerberg * to export resources for those functions.
5625f1ca31SMika Westerberg */
5725f1ca31SMika Westerberg #define SMI_EN_OFFSET 0x0040
5825f1ca31SMika Westerberg #define SMI_EN_SIZE 4
5925f1ca31SMika Westerberg #define TCO_BASE_OFFSET 0x0060
6025f1ca31SMika Westerberg #define TCO_REGS_SIZE 16
6125f1ca31SMika Westerberg #define TELEM_SSRAM_SIZE 240
6225f1ca31SMika Westerberg #define TELEM_PMC_SSRAM_OFFSET 0x1b00
6325f1ca31SMika Westerberg #define TELEM_PUNIT_SSRAM_OFFSET 0x1a00
6425f1ca31SMika Westerberg
6525f1ca31SMika Westerberg /* Commands */
6625f1ca31SMika Westerberg #define PMC_NORTHPEAK_CTRL 0xed
6725f1ca31SMika Westerberg
is_gcr_valid(u32 offset)6825f1ca31SMika Westerberg static inline bool is_gcr_valid(u32 offset)
6925f1ca31SMika Westerberg {
7025f1ca31SMika Westerberg return offset < PLAT_RESOURCE_GCR_SIZE - 8;
7125f1ca31SMika Westerberg }
7225f1ca31SMika Westerberg
7325f1ca31SMika Westerberg /**
7425f1ca31SMika Westerberg * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register
7525f1ca31SMika Westerberg * @pmc: PMC device pointer
7625f1ca31SMika Westerberg * @offset: offset of GCR register from GCR address base
7725f1ca31SMika Westerberg * @data: data pointer for storing the register output
7825f1ca31SMika Westerberg *
7925f1ca31SMika Westerberg * Reads the 64-bit PMC GCR register at given offset.
8025f1ca31SMika Westerberg *
8125f1ca31SMika Westerberg * Return: Negative value on error or 0 on success.
8225f1ca31SMika Westerberg */
intel_pmc_gcr_read64(struct intel_pmc_dev * pmc,u32 offset,u64 * data)8325f1ca31SMika Westerberg int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data)
8425f1ca31SMika Westerberg {
8525f1ca31SMika Westerberg if (!is_gcr_valid(offset))
8625f1ca31SMika Westerberg return -EINVAL;
8725f1ca31SMika Westerberg
8825f1ca31SMika Westerberg spin_lock(&pmc->gcr_lock);
8925f1ca31SMika Westerberg *data = readq(pmc->gcr_mem_base + offset);
9025f1ca31SMika Westerberg spin_unlock(&pmc->gcr_lock);
9125f1ca31SMika Westerberg
9225f1ca31SMika Westerberg return 0;
9325f1ca31SMika Westerberg }
9425f1ca31SMika Westerberg EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64);
9525f1ca31SMika Westerberg
9625f1ca31SMika Westerberg /**
9725f1ca31SMika Westerberg * intel_pmc_gcr_update() - Update PMC GCR register bits
9825f1ca31SMika Westerberg * @pmc: PMC device pointer
9925f1ca31SMika Westerberg * @offset: offset of GCR register from GCR address base
10025f1ca31SMika Westerberg * @mask: bit mask for update operation
10125f1ca31SMika Westerberg * @val: update value
10225f1ca31SMika Westerberg *
10325f1ca31SMika Westerberg * Updates the bits of given GCR register as specified by
10425f1ca31SMika Westerberg * @mask and @val.
10525f1ca31SMika Westerberg *
10625f1ca31SMika Westerberg * Return: Negative value on error or 0 on success.
10725f1ca31SMika Westerberg */
intel_pmc_gcr_update(struct intel_pmc_dev * pmc,u32 offset,u32 mask,u32 val)10825f1ca31SMika Westerberg int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val)
10925f1ca31SMika Westerberg {
11025f1ca31SMika Westerberg u32 new_val;
11125f1ca31SMika Westerberg
11225f1ca31SMika Westerberg if (!is_gcr_valid(offset))
11325f1ca31SMika Westerberg return -EINVAL;
11425f1ca31SMika Westerberg
11525f1ca31SMika Westerberg spin_lock(&pmc->gcr_lock);
11625f1ca31SMika Westerberg new_val = readl(pmc->gcr_mem_base + offset);
11725f1ca31SMika Westerberg
11825f1ca31SMika Westerberg new_val = (new_val & ~mask) | (val & mask);
11925f1ca31SMika Westerberg writel(new_val, pmc->gcr_mem_base + offset);
12025f1ca31SMika Westerberg
12125f1ca31SMika Westerberg new_val = readl(pmc->gcr_mem_base + offset);
12225f1ca31SMika Westerberg spin_unlock(&pmc->gcr_lock);
12325f1ca31SMika Westerberg
12425f1ca31SMika Westerberg /* Check whether the bit update is successful */
12525f1ca31SMika Westerberg return (new_val & mask) != (val & mask) ? -EIO : 0;
12625f1ca31SMika Westerberg }
12725f1ca31SMika Westerberg EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);
12825f1ca31SMika Westerberg
12925f1ca31SMika Westerberg /**
13025f1ca31SMika Westerberg * intel_pmc_s0ix_counter_read() - Read S0ix residency
13125f1ca31SMika Westerberg * @pmc: PMC device pointer
13225f1ca31SMika Westerberg * @data: Out param that contains current S0ix residency count.
13325f1ca31SMika Westerberg *
13425f1ca31SMika Westerberg * Writes to @data how many usecs the system has been in low-power S0ix
13525f1ca31SMika Westerberg * state.
13625f1ca31SMika Westerberg *
13725f1ca31SMika Westerberg * Return: An error code or 0 on success.
13825f1ca31SMika Westerberg */
intel_pmc_s0ix_counter_read(struct intel_pmc_dev * pmc,u64 * data)13925f1ca31SMika Westerberg int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data)
14025f1ca31SMika Westerberg {
14125f1ca31SMika Westerberg u64 deep, shlw;
14225f1ca31SMika Westerberg
14325f1ca31SMika Westerberg spin_lock(&pmc->gcr_lock);
14425f1ca31SMika Westerberg deep = readq(pmc->gcr_mem_base + PMC_GCR_TELEM_DEEP_S0IX_REG);
14525f1ca31SMika Westerberg shlw = readq(pmc->gcr_mem_base + PMC_GCR_TELEM_SHLW_S0IX_REG);
14625f1ca31SMika Westerberg spin_unlock(&pmc->gcr_lock);
14725f1ca31SMika Westerberg
14825f1ca31SMika Westerberg *data = S0IX_RESIDENCY_IN_USECS(deep, shlw);
14925f1ca31SMika Westerberg return 0;
15025f1ca31SMika Westerberg }
15125f1ca31SMika Westerberg EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read);
15225f1ca31SMika Westerberg
15325f1ca31SMika Westerberg /**
15425f1ca31SMika Westerberg * simplecmd_store() - Send a simple IPC command
15525f1ca31SMika Westerberg * @dev: Device under the attribute is
15625f1ca31SMika Westerberg * @attr: Attribute in question
15725f1ca31SMika Westerberg * @buf: Buffer holding data to be stored to the attribute
15825f1ca31SMika Westerberg * @count: Number of bytes in @buf
15925f1ca31SMika Westerberg *
16025f1ca31SMika Westerberg * Expects a string with two integers separated with space. These two
16125f1ca31SMika Westerberg * values hold command and subcommand that is send to PMC.
16225f1ca31SMika Westerberg *
16325f1ca31SMika Westerberg * Return: Number number of bytes written (@count) or negative errno in
16425f1ca31SMika Westerberg * case of error.
16525f1ca31SMika Westerberg */
simplecmd_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)16625f1ca31SMika Westerberg static ssize_t simplecmd_store(struct device *dev, struct device_attribute *attr,
16725f1ca31SMika Westerberg const char *buf, size_t count)
16825f1ca31SMika Westerberg {
16925f1ca31SMika Westerberg struct intel_pmc_dev *pmc = dev_get_drvdata(dev);
17025f1ca31SMika Westerberg struct intel_scu_ipc_dev *scu = pmc->scu;
17125f1ca31SMika Westerberg int subcmd;
17225f1ca31SMika Westerberg int cmd;
17325f1ca31SMika Westerberg int ret;
17425f1ca31SMika Westerberg
17525f1ca31SMika Westerberg ret = sscanf(buf, "%d %d", &cmd, &subcmd);
17625f1ca31SMika Westerberg if (ret != 2) {
17725f1ca31SMika Westerberg dev_err(dev, "Invalid values, expected: cmd subcmd\n");
17825f1ca31SMika Westerberg return -EINVAL;
17925f1ca31SMika Westerberg }
18025f1ca31SMika Westerberg
18125f1ca31SMika Westerberg ret = intel_scu_ipc_dev_simple_command(scu, cmd, subcmd);
18225f1ca31SMika Westerberg if (ret)
18325f1ca31SMika Westerberg return ret;
18425f1ca31SMika Westerberg
18525f1ca31SMika Westerberg return count;
18625f1ca31SMika Westerberg }
18725f1ca31SMika Westerberg static DEVICE_ATTR_WO(simplecmd);
18825f1ca31SMika Westerberg
18925f1ca31SMika Westerberg /**
19025f1ca31SMika Westerberg * northpeak_store() - Enable or disable Northpeak
19125f1ca31SMika Westerberg * @dev: Device under the attribute is
19225f1ca31SMika Westerberg * @attr: Attribute in question
19325f1ca31SMika Westerberg * @buf: Buffer holding data to be stored to the attribute
19425f1ca31SMika Westerberg * @count: Number of bytes in @buf
19525f1ca31SMika Westerberg *
19625f1ca31SMika Westerberg * Expects an unsigned integer. Non-zero enables Northpeak and zero
19725f1ca31SMika Westerberg * disables it.
19825f1ca31SMika Westerberg *
19925f1ca31SMika Westerberg * Return: Number number of bytes written (@count) or negative errno in
20025f1ca31SMika Westerberg * case of error.
20125f1ca31SMika Westerberg */
northpeak_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)20225f1ca31SMika Westerberg static ssize_t northpeak_store(struct device *dev, struct device_attribute *attr,
20325f1ca31SMika Westerberg const char *buf, size_t count)
20425f1ca31SMika Westerberg {
20525f1ca31SMika Westerberg struct intel_pmc_dev *pmc = dev_get_drvdata(dev);
20625f1ca31SMika Westerberg struct intel_scu_ipc_dev *scu = pmc->scu;
20725f1ca31SMika Westerberg unsigned long val;
20825f1ca31SMika Westerberg int subcmd;
20925f1ca31SMika Westerberg int ret;
21025f1ca31SMika Westerberg
21125f1ca31SMika Westerberg ret = kstrtoul(buf, 0, &val);
21225f1ca31SMika Westerberg if (ret)
21325f1ca31SMika Westerberg return ret;
21425f1ca31SMika Westerberg
21525f1ca31SMika Westerberg /* Northpeak is enabled if subcmd == 1 and disabled if it is 0 */
21625f1ca31SMika Westerberg if (val)
21725f1ca31SMika Westerberg subcmd = 1;
21825f1ca31SMika Westerberg else
21925f1ca31SMika Westerberg subcmd = 0;
22025f1ca31SMika Westerberg
22125f1ca31SMika Westerberg ret = intel_scu_ipc_dev_simple_command(scu, PMC_NORTHPEAK_CTRL, subcmd);
22225f1ca31SMika Westerberg if (ret)
22325f1ca31SMika Westerberg return ret;
22425f1ca31SMika Westerberg
22525f1ca31SMika Westerberg return count;
22625f1ca31SMika Westerberg }
22725f1ca31SMika Westerberg static DEVICE_ATTR_WO(northpeak);
22825f1ca31SMika Westerberg
22925f1ca31SMika Westerberg static struct attribute *intel_pmc_attrs[] = {
23025f1ca31SMika Westerberg &dev_attr_northpeak.attr,
23125f1ca31SMika Westerberg &dev_attr_simplecmd.attr,
23225f1ca31SMika Westerberg NULL
23325f1ca31SMika Westerberg };
23425f1ca31SMika Westerberg
23525f1ca31SMika Westerberg static const struct attribute_group intel_pmc_group = {
23625f1ca31SMika Westerberg .attrs = intel_pmc_attrs,
23725f1ca31SMika Westerberg };
23825f1ca31SMika Westerberg
23925f1ca31SMika Westerberg static const struct attribute_group *intel_pmc_groups[] = {
24025f1ca31SMika Westerberg &intel_pmc_group,
24125f1ca31SMika Westerberg NULL
24225f1ca31SMika Westerberg };
24325f1ca31SMika Westerberg
24425f1ca31SMika Westerberg static struct resource punit_res[6];
24525f1ca31SMika Westerberg
24625f1ca31SMika Westerberg static struct mfd_cell punit = {
24725f1ca31SMika Westerberg .name = "intel_punit_ipc",
24825f1ca31SMika Westerberg .resources = punit_res,
24925f1ca31SMika Westerberg };
25025f1ca31SMika Westerberg
25125f1ca31SMika Westerberg static struct itco_wdt_platform_data tco_pdata = {
25225f1ca31SMika Westerberg .name = "Apollo Lake SoC",
25325f1ca31SMika Westerberg .version = 5,
25425f1ca31SMika Westerberg .no_reboot_use_pmc = true,
25525f1ca31SMika Westerberg };
25625f1ca31SMika Westerberg
25725f1ca31SMika Westerberg static struct resource tco_res[2];
25825f1ca31SMika Westerberg
25925f1ca31SMika Westerberg static const struct mfd_cell tco = {
26025f1ca31SMika Westerberg .name = "iTCO_wdt",
26125f1ca31SMika Westerberg .ignore_resource_conflicts = true,
26225f1ca31SMika Westerberg .resources = tco_res,
26325f1ca31SMika Westerberg .num_resources = ARRAY_SIZE(tco_res),
26425f1ca31SMika Westerberg .platform_data = &tco_pdata,
26525f1ca31SMika Westerberg .pdata_size = sizeof(tco_pdata),
26625f1ca31SMika Westerberg };
26725f1ca31SMika Westerberg
26825f1ca31SMika Westerberg static const struct resource telem_res[] = {
26925f1ca31SMika Westerberg DEFINE_RES_MEM(TELEM_PUNIT_SSRAM_OFFSET, TELEM_SSRAM_SIZE),
27025f1ca31SMika Westerberg DEFINE_RES_MEM(TELEM_PMC_SSRAM_OFFSET, TELEM_SSRAM_SIZE),
27125f1ca31SMika Westerberg };
27225f1ca31SMika Westerberg
27325f1ca31SMika Westerberg static const struct mfd_cell telem = {
27425f1ca31SMika Westerberg .name = "intel_telemetry",
27525f1ca31SMika Westerberg .resources = telem_res,
27625f1ca31SMika Westerberg .num_resources = ARRAY_SIZE(telem_res),
27725f1ca31SMika Westerberg };
27825f1ca31SMika Westerberg
intel_pmc_get_tco_resources(struct platform_device * pdev)27925f1ca31SMika Westerberg static int intel_pmc_get_tco_resources(struct platform_device *pdev)
28025f1ca31SMika Westerberg {
28125f1ca31SMika Westerberg struct resource *res;
28225f1ca31SMika Westerberg
28325f1ca31SMika Westerberg if (acpi_has_watchdog())
28425f1ca31SMika Westerberg return 0;
28525f1ca31SMika Westerberg
28625f1ca31SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_IO,
28725f1ca31SMika Westerberg PLAT_RESOURCE_ACPI_IO_INDEX);
28825f1ca31SMika Westerberg if (!res) {
28925f1ca31SMika Westerberg dev_err(&pdev->dev, "Failed to get IO resource\n");
29025f1ca31SMika Westerberg return -EINVAL;
29125f1ca31SMika Westerberg }
29225f1ca31SMika Westerberg
29325f1ca31SMika Westerberg tco_res[0].flags = IORESOURCE_IO;
29425f1ca31SMika Westerberg tco_res[0].start = res->start + TCO_BASE_OFFSET;
29525f1ca31SMika Westerberg tco_res[0].end = tco_res[0].start + TCO_REGS_SIZE - 1;
29625f1ca31SMika Westerberg tco_res[1].flags = IORESOURCE_IO;
29725f1ca31SMika Westerberg tco_res[1].start = res->start + SMI_EN_OFFSET;
29825f1ca31SMika Westerberg tco_res[1].end = tco_res[1].start + SMI_EN_SIZE - 1;
29925f1ca31SMika Westerberg
30025f1ca31SMika Westerberg return 0;
30125f1ca31SMika Westerberg }
30225f1ca31SMika Westerberg
intel_pmc_get_resources(struct platform_device * pdev,struct intel_pmc_dev * pmc,struct intel_scu_ipc_data * scu_data)30325f1ca31SMika Westerberg static int intel_pmc_get_resources(struct platform_device *pdev,
30425f1ca31SMika Westerberg struct intel_pmc_dev *pmc,
30525f1ca31SMika Westerberg struct intel_scu_ipc_data *scu_data)
30625f1ca31SMika Westerberg {
30725f1ca31SMika Westerberg struct resource gcr_res;
30825f1ca31SMika Westerberg size_t npunit_res = 0;
30925f1ca31SMika Westerberg struct resource *res;
31025f1ca31SMika Westerberg int ret;
31125f1ca31SMika Westerberg
31225f1ca31SMika Westerberg scu_data->irq = platform_get_irq_optional(pdev, 0);
31325f1ca31SMika Westerberg
31425f1ca31SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM,
31525f1ca31SMika Westerberg PLAT_RESOURCE_IPC_INDEX);
31625f1ca31SMika Westerberg if (!res) {
31725f1ca31SMika Westerberg dev_err(&pdev->dev, "Failed to get IPC resource\n");
31825f1ca31SMika Westerberg return -EINVAL;
31925f1ca31SMika Westerberg }
32025f1ca31SMika Westerberg
32125f1ca31SMika Westerberg /* IPC registers */
32225f1ca31SMika Westerberg scu_data->mem.flags = res->flags;
32325f1ca31SMika Westerberg scu_data->mem.start = res->start;
32425f1ca31SMika Westerberg scu_data->mem.end = res->start + PLAT_RESOURCE_IPC_SIZE - 1;
32525f1ca31SMika Westerberg
32625f1ca31SMika Westerberg /* GCR registers */
32725f1ca31SMika Westerberg gcr_res.flags = res->flags;
32825f1ca31SMika Westerberg gcr_res.start = res->start + PLAT_RESOURCE_GCR_OFFSET;
32925f1ca31SMika Westerberg gcr_res.end = gcr_res.start + PLAT_RESOURCE_GCR_SIZE - 1;
33025f1ca31SMika Westerberg
33125f1ca31SMika Westerberg pmc->gcr_mem_base = devm_ioremap_resource(&pdev->dev, &gcr_res);
33225f1ca31SMika Westerberg if (IS_ERR(pmc->gcr_mem_base))
33325f1ca31SMika Westerberg return PTR_ERR(pmc->gcr_mem_base);
33425f1ca31SMika Westerberg
33525f1ca31SMika Westerberg /* Only register iTCO watchdog if there is no WDAT ACPI table */
33625f1ca31SMika Westerberg ret = intel_pmc_get_tco_resources(pdev);
33725f1ca31SMika Westerberg if (ret)
33825f1ca31SMika Westerberg return ret;
33925f1ca31SMika Westerberg
34025f1ca31SMika Westerberg /* BIOS data register */
34125f1ca31SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM,
34225f1ca31SMika Westerberg PLAT_RESOURCE_BIOS_DATA_INDEX);
34325f1ca31SMika Westerberg if (!res) {
34425f1ca31SMika Westerberg dev_err(&pdev->dev, "Failed to get resource of P-unit BIOS data\n");
34525f1ca31SMika Westerberg return -EINVAL;
34625f1ca31SMika Westerberg }
34725f1ca31SMika Westerberg punit_res[npunit_res++] = *res;
34825f1ca31SMika Westerberg
34925f1ca31SMika Westerberg /* BIOS interface register */
35025f1ca31SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM,
35125f1ca31SMika Westerberg PLAT_RESOURCE_BIOS_IFACE_INDEX);
35225f1ca31SMika Westerberg if (!res) {
35325f1ca31SMika Westerberg dev_err(&pdev->dev, "Failed to get resource of P-unit BIOS interface\n");
35425f1ca31SMika Westerberg return -EINVAL;
35525f1ca31SMika Westerberg }
35625f1ca31SMika Westerberg punit_res[npunit_res++] = *res;
35725f1ca31SMika Westerberg
35825f1ca31SMika Westerberg /* ISP data register, optional */
35925f1ca31SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM,
36025f1ca31SMika Westerberg PLAT_RESOURCE_ISP_DATA_INDEX);
36125f1ca31SMika Westerberg if (res)
36225f1ca31SMika Westerberg punit_res[npunit_res++] = *res;
36325f1ca31SMika Westerberg
36425f1ca31SMika Westerberg /* ISP interface register, optional */
36525f1ca31SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM,
36625f1ca31SMika Westerberg PLAT_RESOURCE_ISP_IFACE_INDEX);
36725f1ca31SMika Westerberg if (res)
36825f1ca31SMika Westerberg punit_res[npunit_res++] = *res;
36925f1ca31SMika Westerberg
37025f1ca31SMika Westerberg /* GTD data register, optional */
37125f1ca31SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM,
37225f1ca31SMika Westerberg PLAT_RESOURCE_GTD_DATA_INDEX);
37325f1ca31SMika Westerberg if (res)
37425f1ca31SMika Westerberg punit_res[npunit_res++] = *res;
37525f1ca31SMika Westerberg
37625f1ca31SMika Westerberg /* GTD interface register, optional */
37725f1ca31SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM,
37825f1ca31SMika Westerberg PLAT_RESOURCE_GTD_IFACE_INDEX);
37925f1ca31SMika Westerberg if (res)
38025f1ca31SMika Westerberg punit_res[npunit_res++] = *res;
38125f1ca31SMika Westerberg
38225f1ca31SMika Westerberg punit.num_resources = npunit_res;
38325f1ca31SMika Westerberg
38425f1ca31SMika Westerberg /* Telemetry SSRAM is optional */
38525f1ca31SMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM,
38625f1ca31SMika Westerberg PLAT_RESOURCE_TELEM_SSRAM_INDEX);
38725f1ca31SMika Westerberg if (res)
38825f1ca31SMika Westerberg pmc->telem_base = res;
38925f1ca31SMika Westerberg
39025f1ca31SMika Westerberg return 0;
39125f1ca31SMika Westerberg }
39225f1ca31SMika Westerberg
intel_pmc_create_devices(struct intel_pmc_dev * pmc)39325f1ca31SMika Westerberg static int intel_pmc_create_devices(struct intel_pmc_dev *pmc)
39425f1ca31SMika Westerberg {
39525f1ca31SMika Westerberg int ret;
39625f1ca31SMika Westerberg
39725f1ca31SMika Westerberg if (!acpi_has_watchdog()) {
39825f1ca31SMika Westerberg ret = devm_mfd_add_devices(pmc->dev, PLATFORM_DEVID_AUTO, &tco,
39925f1ca31SMika Westerberg 1, NULL, 0, NULL);
40025f1ca31SMika Westerberg if (ret)
40125f1ca31SMika Westerberg return ret;
40225f1ca31SMika Westerberg }
40325f1ca31SMika Westerberg
40425f1ca31SMika Westerberg ret = devm_mfd_add_devices(pmc->dev, PLATFORM_DEVID_AUTO, &punit, 1,
40525f1ca31SMika Westerberg NULL, 0, NULL);
40625f1ca31SMika Westerberg if (ret)
40725f1ca31SMika Westerberg return ret;
40825f1ca31SMika Westerberg
40925f1ca31SMika Westerberg if (pmc->telem_base) {
41025f1ca31SMika Westerberg ret = devm_mfd_add_devices(pmc->dev, PLATFORM_DEVID_AUTO,
41125f1ca31SMika Westerberg &telem, 1, pmc->telem_base, 0, NULL);
41225f1ca31SMika Westerberg }
41325f1ca31SMika Westerberg
41425f1ca31SMika Westerberg return ret;
41525f1ca31SMika Westerberg }
41625f1ca31SMika Westerberg
41725f1ca31SMika Westerberg static const struct acpi_device_id intel_pmc_acpi_ids[] = {
41825f1ca31SMika Westerberg { "INT34D2" },
41925f1ca31SMika Westerberg { }
42025f1ca31SMika Westerberg };
42125f1ca31SMika Westerberg MODULE_DEVICE_TABLE(acpi, intel_pmc_acpi_ids);
42225f1ca31SMika Westerberg
intel_pmc_probe(struct platform_device * pdev)42325f1ca31SMika Westerberg static int intel_pmc_probe(struct platform_device *pdev)
42425f1ca31SMika Westerberg {
42525f1ca31SMika Westerberg struct intel_scu_ipc_data scu_data = {};
42625f1ca31SMika Westerberg struct intel_pmc_dev *pmc;
42725f1ca31SMika Westerberg int ret;
42825f1ca31SMika Westerberg
42925f1ca31SMika Westerberg pmc = devm_kzalloc(&pdev->dev, sizeof(*pmc), GFP_KERNEL);
43025f1ca31SMika Westerberg if (!pmc)
43125f1ca31SMika Westerberg return -ENOMEM;
43225f1ca31SMika Westerberg
43325f1ca31SMika Westerberg pmc->dev = &pdev->dev;
43425f1ca31SMika Westerberg spin_lock_init(&pmc->gcr_lock);
43525f1ca31SMika Westerberg
43625f1ca31SMika Westerberg ret = intel_pmc_get_resources(pdev, pmc, &scu_data);
43725f1ca31SMika Westerberg if (ret) {
43825f1ca31SMika Westerberg dev_err(&pdev->dev, "Failed to request resources\n");
43925f1ca31SMika Westerberg return ret;
44025f1ca31SMika Westerberg }
44125f1ca31SMika Westerberg
44225f1ca31SMika Westerberg pmc->scu = devm_intel_scu_ipc_register(&pdev->dev, &scu_data);
44325f1ca31SMika Westerberg if (IS_ERR(pmc->scu))
44425f1ca31SMika Westerberg return PTR_ERR(pmc->scu);
44525f1ca31SMika Westerberg
44625f1ca31SMika Westerberg platform_set_drvdata(pdev, pmc);
44725f1ca31SMika Westerberg
44825f1ca31SMika Westerberg ret = intel_pmc_create_devices(pmc);
44925f1ca31SMika Westerberg if (ret)
45025f1ca31SMika Westerberg dev_err(&pdev->dev, "Failed to create PMC devices\n");
45125f1ca31SMika Westerberg
45225f1ca31SMika Westerberg return ret;
45325f1ca31SMika Westerberg }
45425f1ca31SMika Westerberg
45525f1ca31SMika Westerberg static struct platform_driver intel_pmc_driver = {
45625f1ca31SMika Westerberg .probe = intel_pmc_probe,
45725f1ca31SMika Westerberg .driver = {
45825f1ca31SMika Westerberg .name = "intel_pmc_bxt",
45925f1ca31SMika Westerberg .acpi_match_table = intel_pmc_acpi_ids,
46025f1ca31SMika Westerberg .dev_groups = intel_pmc_groups,
46125f1ca31SMika Westerberg },
46225f1ca31SMika Westerberg };
46325f1ca31SMika Westerberg module_platform_driver(intel_pmc_driver);
46425f1ca31SMika Westerberg
46525f1ca31SMika Westerberg MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
46625f1ca31SMika Westerberg MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
46725f1ca31SMika Westerberg MODULE_DESCRIPTION("Intel Broxton PMC driver");
46825f1ca31SMika Westerberg MODULE_LICENSE("GPL v2");
469