1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2d34efc76SSteve Sakoman /* 3d34efc76SSteve Sakoman * (C) Copyright 2006-2010 4d34efc76SSteve Sakoman * Texas Instruments, <www.ti.com> 5d34efc76SSteve Sakoman */ 6d34efc76SSteve Sakoman 7d34efc76SSteve Sakoman #ifndef _CPU_H 8d34efc76SSteve Sakoman #define _CPU_H 9d34efc76SSteve Sakoman 10d34efc76SSteve Sakoman #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 11d34efc76SSteve Sakoman #include <asm/types.h> 12d34efc76SSteve Sakoman #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 13d34efc76SSteve Sakoman 14e4426d07Spekon gupta #include <asm/arch/hardware.h> 15e4426d07Spekon gupta 16d34efc76SSteve Sakoman #ifndef __KERNEL_STRICT_NAMES 17d34efc76SSteve Sakoman #ifndef __ASSEMBLY__ 18d34efc76SSteve Sakoman struct gptimer { 19d34efc76SSteve Sakoman u32 tidr; /* 0x00 r */ 20d34efc76SSteve Sakoman u8 res[0xc]; 21d34efc76SSteve Sakoman u32 tiocp_cfg; /* 0x10 rw */ 22d34efc76SSteve Sakoman u32 tistat; /* 0x14 r */ 23d34efc76SSteve Sakoman u32 tisr; /* 0x18 rw */ 24d34efc76SSteve Sakoman u32 tier; /* 0x1c rw */ 25d34efc76SSteve Sakoman u32 twer; /* 0x20 rw */ 26d34efc76SSteve Sakoman u32 tclr; /* 0x24 rw */ 27d34efc76SSteve Sakoman u32 tcrr; /* 0x28 rw */ 28d34efc76SSteve Sakoman u32 tldr; /* 0x2c rw */ 29d34efc76SSteve Sakoman u32 ttgr; /* 0x30 rw */ 30d34efc76SSteve Sakoman u32 twpc; /* 0x34 r */ 31d34efc76SSteve Sakoman u32 tmar; /* 0x38 rw */ 32d34efc76SSteve Sakoman u32 tcar1; /* 0x3c r */ 33d34efc76SSteve Sakoman u32 tcicr; /* 0x40 rw */ 34d34efc76SSteve Sakoman u32 tcar2; /* 0x44 r */ 35d34efc76SSteve Sakoman }; 36d34efc76SSteve Sakoman #endif /* __ASSEMBLY__ */ 37d34efc76SSteve Sakoman #endif /* __KERNEL_STRICT_NAMES */ 38d34efc76SSteve Sakoman 39d34efc76SSteve Sakoman /* enable sys_clk NO-prescale /1 */ 40d34efc76SSteve Sakoman #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 41d34efc76SSteve Sakoman 42d34efc76SSteve Sakoman /* Watchdog */ 43d34efc76SSteve Sakoman #ifndef __KERNEL_STRICT_NAMES 44d34efc76SSteve Sakoman #ifndef __ASSEMBLY__ 45d34efc76SSteve Sakoman struct watchdog { 46d34efc76SSteve Sakoman u8 res1[0x34]; 47d34efc76SSteve Sakoman u32 wwps; /* 0x34 r */ 48d34efc76SSteve Sakoman u8 res2[0x10]; 49d34efc76SSteve Sakoman u32 wspr; /* 0x48 rw */ 50d34efc76SSteve Sakoman }; 51d34efc76SSteve Sakoman #endif /* __ASSEMBLY__ */ 52d34efc76SSteve Sakoman #endif /* __KERNEL_STRICT_NAMES */ 53d34efc76SSteve Sakoman 54d34efc76SSteve Sakoman #define WD_UNLOCK1 0xAAAA 55d34efc76SSteve Sakoman #define WD_UNLOCK2 0x5555 56d34efc76SSteve Sakoman 57d34efc76SSteve Sakoman #define TCLR_ST (0x1 << 0) 58d34efc76SSteve Sakoman #define TCLR_AR (0x1 << 1) 59d34efc76SSteve Sakoman #define TCLR_PRE (0x1 << 5) 60d34efc76SSteve Sakoman 61d34efc76SSteve Sakoman /* I2C base */ 62d34efc76SSteve Sakoman #define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) 63d34efc76SSteve Sakoman #define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) 64d34efc76SSteve Sakoman #define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) 65a5322780SKoen Kooi #define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) 66d34efc76SSteve Sakoman 679b167577SSteve Sakoman /* MUSB base */ 689b167577SSteve Sakoman #define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) 699b167577SSteve Sakoman 7025223a68SAneesh V /* OMAP4 GPIO registers */ 7125223a68SAneesh V #define OMAP_GPIO_REVISION 0x0000 7225223a68SAneesh V #define OMAP_GPIO_SYSCONFIG 0x0010 7325223a68SAneesh V #define OMAP_GPIO_SYSSTATUS 0x0114 7425223a68SAneesh V #define OMAP_GPIO_IRQSTATUS1 0x0118 7525223a68SAneesh V #define OMAP_GPIO_IRQSTATUS2 0x0128 7625223a68SAneesh V #define OMAP_GPIO_IRQENABLE2 0x012c 7725223a68SAneesh V #define OMAP_GPIO_IRQENABLE1 0x011c 7825223a68SAneesh V #define OMAP_GPIO_WAKE_EN 0x0120 7925223a68SAneesh V #define OMAP_GPIO_CTRL 0x0130 8025223a68SAneesh V #define OMAP_GPIO_OE 0x0134 8125223a68SAneesh V #define OMAP_GPIO_DATAIN 0x0138 8225223a68SAneesh V #define OMAP_GPIO_DATAOUT 0x013c 8325223a68SAneesh V #define OMAP_GPIO_LEVELDETECT0 0x0140 8425223a68SAneesh V #define OMAP_GPIO_LEVELDETECT1 0x0144 8525223a68SAneesh V #define OMAP_GPIO_RISINGDETECT 0x0148 8625223a68SAneesh V #define OMAP_GPIO_FALLINGDETECT 0x014c 8725223a68SAneesh V #define OMAP_GPIO_DEBOUNCE_EN 0x0150 8825223a68SAneesh V #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 8925223a68SAneesh V #define OMAP_GPIO_CLEARIRQENABLE1 0x0160 9025223a68SAneesh V #define OMAP_GPIO_SETIRQENABLE1 0x0164 9125223a68SAneesh V #define OMAP_GPIO_CLEARWKUENA 0x0180 9225223a68SAneesh V #define OMAP_GPIO_SETWKUENA 0x0184 9325223a68SAneesh V #define OMAP_GPIO_CLEARDATAOUT 0x0190 9425223a68SAneesh V #define OMAP_GPIO_SETDATAOUT 0x0194 9525223a68SAneesh V 96d417d1dbSSRICHARAN R /* 97d417d1dbSSRICHARAN R * PRCM 98d417d1dbSSRICHARAN R */ 99d417d1dbSSRICHARAN R 100d417d1dbSSRICHARAN R /* PRM */ 101d417d1dbSSRICHARAN R #define PRM_BASE 0x4A306000 102d417d1dbSSRICHARAN R #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) 103d417d1dbSSRICHARAN R 104d417d1dbSSRICHARAN R #define PRM_RSTCTRL PRM_DEVICE_BASE 105d417d1dbSSRICHARAN R #define PRM_RSTCTRL_RESET 0x01 10670239507SLokesh Vutla #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) 10770239507SLokesh Vutla #define PRM_RSTST_WARM_RESET_MASK 0x07EA 108d417d1dbSSRICHARAN R 109d34efc76SSteve Sakoman #endif /* _CPU_H */ 110