Lines Matching +full:0 +full:x1b00
32 * stacks, thus for PEC2, the global registers are at offset 0, the
33 * PHB3 registers at offset 0x40, the PHB4 at offset 0x80 etc....
36 * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc..
38 #define PEC_STACK_OFFSET 0x40
41 #define PEC_NEST_PBCQ_HW_CONFIG 0x00
42 #define PEC_NEST_DROP_PRIO_CTRL 0x01
43 #define PEC_NEST_PBCQ_ERR_INJECT 0x02
44 #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03
45 #define PEC_NEST_PBCQ_PMON_CTRL 0x04
46 #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05
47 #define PEC_NEST_PBCQ_PRED_VEC_TIMEOUT 0x06
48 #define PEC_NEST_CAPP_CTRL 0x07
49 #define PEC_NEST_PBCQ_READ_STK_OVR 0x08
50 #define PEC_NEST_PBCQ_WRITE_STK_OVR 0x09
51 #define PEC_NEST_PBCQ_STORE_STK_OVR 0x0a
52 #define PEC_NEST_PBCQ_RETRY_BKOFF_CTRL 0x0b
55 #define PEC_NEST_STK_PCI_NEST_FIR 0x00
56 #define PEC_NEST_STK_PCI_NEST_FIR_CLR 0x01
57 #define PEC_NEST_STK_PCI_NEST_FIR_SET 0x02
58 #define PEC_NEST_STK_PCI_NEST_FIR_MSK 0x03
59 #define PEC_NEST_STK_PCI_NEST_FIR_MSKC 0x04
60 #define PEC_NEST_STK_PCI_NEST_FIR_MSKS 0x05
61 #define PEC_NEST_STK_PCI_NEST_FIR_ACT0 0x06
62 #define PEC_NEST_STK_PCI_NEST_FIR_ACT1 0x07
63 #define PEC_NEST_STK_PCI_NEST_FIR_WOF 0x08
64 #define PEC_NEST_STK_ERR_REPORT_0 0x0a
65 #define PEC_NEST_STK_ERR_REPORT_1 0x0b
66 #define PEC_NEST_STK_PBCQ_GNRL_STATUS 0x0c
67 #define PEC_NEST_STK_PBCQ_MODE 0x0d
68 #define PEC_NEST_STK_MMIO_BAR0 0x0e
69 #define PEC_NEST_STK_MMIO_BAR0_MASK 0x0f
70 #define PEC_NEST_STK_MMIO_BAR1 0x10
71 #define PEC_NEST_STK_MMIO_BAR1_MASK 0x11
72 #define PEC_NEST_STK_PHB_REGS_BAR 0x12
73 #define PEC_NEST_STK_INT_BAR 0x13
74 #define PEC_NEST_STK_BAR_EN 0x14
75 #define PEC_NEST_STK_BAR_EN_MMIO0 PPC_BIT(0)
79 #define PEC_NEST_STK_DATA_FRZ_TYPE 0x15
80 #define PEC_NEST_STK_PBCQ_SPARSE_PAGE 0x16 /* P10 */
81 #define PEC_NEST_STK_PBCQ_CACHE_INJ 0x17 /* P10 */
84 #define PEC_PCI_PBAIB_HW_CONFIG 0x00
85 #define PEC_PCI_PBAIB_HW_OVR 0x01
86 #define PEC_PCI_PBAIB_READ_STK_OVR 0x02
89 #define PEC_PCI_STK_PCI_FIR 0x00
90 #define PEC_PCI_STK_PCI_FIR_CLR 0x01
91 #define PEC_PCI_STK_PCI_FIR_SET 0x02
92 #define PEC_PCI_STK_PCI_FIR_MSK 0x03
93 #define PEC_PCI_STK_PCI_FIR_MSKC 0x04
94 #define PEC_PCI_STK_PCI_FIR_MSKS 0x05
95 #define PEC_PCI_STK_PCI_FIR_ACT0 0x06
96 #define PEC_PCI_STK_PCI_FIR_ACT1 0x07
97 #define PEC_PCI_STK_PCI_FIR_WOF 0x08
98 #define PEC_PCI_STK_ETU_RESET 0x0a
99 #define PEC_PCI_STK_PBAIB_ERR_REPORT 0x0b
100 #define PEC_PCI_STK_PBAIB_TX_CMD_CRED 0x0d
101 #define PEC_PCI_STK_PBAIB_TX_DAT_CRED 0x0e
110 #define PHB_SCOM_HV_IND_ADDR 0x00
111 #define PHB_SCOM_HV_IND_ADDR_VALID PPC_BIT(0)
115 #define PHB_SCOM_HV_IND_DATA 0x01
116 #define PHB_SCOM_ETU_LEM_FIR 0x08
117 #define PHB_SCOM_ETU_LEM_FIR_AND 0x09
118 #define PHB_SCOM_ETU_LEM_FIR_OR 0x0a
119 #define PHB_SCOM_ETU_LEM_FIR_MSK 0x0b
120 #define PHB_SCOM_ETU_LEM_ERR_MSK_AND 0x0c
121 #define PHB_SCOM_ETU_LEM_ERR_MSK_OR 0x0d
122 #define PHB_SCOM_ETU_LEM_ACT0 0x0e
123 #define PHB_SCOM_ETU_LEM_ACT1 0x0f
124 #define PHB_SCOM_ETU_LEM_WOF 0x10
125 #define PHB_SCOM_ETU_PMON_CONFIG 0x17
126 #define PHB_SCOM_ETU_PMON_CTR0 0x18
127 #define PHB_SCOM_ETU_PMON_CTR1 0x19
128 #define PHB_SCOM_ETU_PMON_CTR2 0x1a
129 #define PHB_SCOM_ETU_PMON_CTR3 0x1b
137 #define PHB_LSI_SOURCE_ID 0x100
139 #define PHB_DMA_CHAN_STATUS 0x110
143 #define PHB_CPU_LOADSTORE_STATUS 0x120
147 #define PHB_CONFIG_DATA 0x130
148 #define PHB_LOCK0 0x138
149 #define PHB_CONFIG_ADDRESS 0x140
150 #define PHB_CA_ENABLE PPC_BIT(0)
152 #define PHB_CA_STATUS_GOOD 0
162 #define PHB_LOCK1 0x148
163 #define PHB_PHB4_CONFIG 0x160
166 #define PHB_RTT_BAR 0x168
167 #define PHB_RTT_BAR_ENABLE PPC_BIT(0)
169 #define PHB_PELTV_BAR 0x188
170 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0)
172 #define PHB_M32_START_ADDR 0x1a0
173 #define PHB_PEST_BAR 0x1a8
174 #define PHB_PEST_BAR_ENABLE PPC_BIT(0)
176 #define PHB_ASN_CMPM 0x1C0
178 #define PHB_CAPI_CMPM 0x1C8
180 #define PHB_M64_AOMASK 0x1d0
181 #define PHB_M64_UPPER_BITS 0x1f0
182 #define PHB_NXLATE_PREFIX 0x1f8
183 #define PHB_DMARD_SYNC 0x200
184 #define PHB_DMARD_SYNC_START PPC_BIT(0)
186 #define PHB_RTC_INVALIDATE 0x208
187 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0)
189 #define PHB_TCE_KILL 0x210
190 #define PHB_TCE_KILL_ALL PPC_BIT(0)
194 #define PHB_TCE_KILL_64K 0x1000 /* Address override */
195 #define PHB_TCE_KILL_2M 0x2000 /* Address override */
196 #define PHB_TCE_KILL_1G 0x3000 /* Address override */
198 #define PHB_TCE_SPEC_CTL 0x218
199 #define PHB_IODA_ADDR 0x220
200 #define PHB_IODA_AD_AUTOINC PPC_BIT(0)
204 #define PHB_IODA_DATA0 0x228
205 #define PHB_PHB4_GEN_CAP 0x250
206 #define PHB_PHB4_TCE_CAP 0x258
207 #define PHB_PHB4_IRQ_CAP 0x260
208 #define PHB_PHB4_EEH_CAP 0x268
209 #define PHB_PAPR_ERR_INJ_CTL 0x2b0
210 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0)
217 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8
219 #define PHB_PAPR_ERR_INJ_MASK 0x2c0
223 #define PHB_ETU_ERR_SUMMARY 0x2c8
224 #define PHB_INT_NOTIFY_ADDR 0x300
226 #define PHB_INT_NOTIFY_INDEX 0x308
229 #define PHB_VERSION 0x800
230 #define PHB_CTRLR 0x810
240 #define TVT_DD1_1_PER_PE 0
245 #define TVT_2_PER_PE 0
250 #define PHB_AIB_FENCE_CTRL 0x860
251 #define PHB_TCE_TAG_ENABLE 0x868
252 #define PHB_TCE_WATERMARK 0x870
253 #define PHB_TIMEOUT_CTRL1 0x878
254 #define PHB_TIMEOUT_CTRL2 0x880
255 #define PHB_Q_DMA_R 0x888
256 #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0)
262 #define PHB_TCE_TAG_STATUS 0x908
265 #define PHB_LEM_FIR_ACCUM 0xc00
266 #define PHB_LEM_FIR_AND_MASK 0xc08
267 #define PHB_LEM_FIR_OR_MASK 0xc10
268 #define PHB_LEM_ERROR_MASK 0xc18
269 #define PHB_LEM_ERROR_AND_MASK 0xc20
270 #define PHB_LEM_ERROR_OR_MASK 0xc28
271 #define PHB_LEM_ACTION0 0xc30
272 #define PHB_LEM_ACTION1 0xc38
273 #define PHB_LEM_WOF 0xc40
274 #define PHB_ERR_STATUS 0xc80
275 #define PHB_ERR1_STATUS 0xc88
276 #define PHB_ERR_INJECT 0xc90
277 #define PHB_ERR_LEM_ENABLE 0xc98
278 #define PHB_ERR_IRQ_ENABLE 0xca0
279 #define PHB_ERR_FREEZE_ENABLE 0xca8
280 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0
281 #define PHB_ERR_LOG_0 0xcc0
282 #define PHB_ERR_LOG_1 0xcc8
283 #define PHB_ERR_STATUS_MASK 0xcd0
284 #define PHB_ERR1_STATUS_MASK 0xcd8
286 #define PHB_TXE_ERR_STATUS 0xd00
287 #define PHB_TXE_ERR1_STATUS 0xd08
288 #define PHB_TXE_ERR_INJECT 0xd10
289 #define PHB_TXE_ERR_LEM_ENABLE 0xd18
290 #define PHB_TXE_ERR_IRQ_ENABLE 0xd20
291 #define PHB_TXE_ERR_FREEZE_ENABLE 0xd28
292 #define PHB_TXE_ERR_AIB_FENCE_ENABLE 0xd30
293 #define PHB_TXE_ERR_LOG_0 0xd40
294 #define PHB_TXE_ERR_LOG_1 0xd48
295 #define PHB_TXE_ERR_STATUS_MASK 0xd50
296 #define PHB_TXE_ERR1_STATUS_MASK 0xd58
298 #define PHB_RXE_ARB_ERR_STATUS 0xd80
299 #define PHB_RXE_ARB_ERR1_STATUS 0xd88
300 #define PHB_RXE_ARB_ERR_INJECT 0xd90
301 #define PHB_RXE_ARB_ERR_LEM_ENABLE 0xd98
302 #define PHB_RXE_ARB_ERR_IRQ_ENABLE 0xda0
303 #define PHB_RXE_ARB_ERR_FREEZE_ENABLE 0xda8
304 #define PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE 0xdb0
305 #define PHB_RXE_ARB_ERR_LOG_0 0xdc0
306 #define PHB_RXE_ARB_ERR_LOG_1 0xdc8
307 #define PHB_RXE_ARB_ERR_STATUS_MASK 0xdd0
308 #define PHB_RXE_ARB_ERR1_STATUS_MASK 0xdd8
310 #define PHB_RXE_MRG_ERR_STATUS 0xe00
311 #define PHB_RXE_MRG_ERR1_STATUS 0xe08
312 #define PHB_RXE_MRG_ERR_INJECT 0xe10
313 #define PHB_RXE_MRG_ERR_LEM_ENABLE 0xe18
314 #define PHB_RXE_MRG_ERR_IRQ_ENABLE 0xe20
315 #define PHB_RXE_MRG_ERR_FREEZE_ENABLE 0xe28
316 #define PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE 0xe30
317 #define PHB_RXE_MRG_ERR_LOG_0 0xe40
318 #define PHB_RXE_MRG_ERR_LOG_1 0xe48
319 #define PHB_RXE_MRG_ERR_STATUS_MASK 0xe50
320 #define PHB_RXE_MRG_ERR1_STATUS_MASK 0xe58
322 #define PHB_RXE_TCE_ERR_STATUS 0xe80
323 #define PHB_RXE_TCE_ERR1_STATUS 0xe88
324 #define PHB_RXE_TCE_ERR_INJECT 0xe90
325 #define PHB_RXE_TCE_ERR_LEM_ENABLE 0xe98
326 #define PHB_RXE_TCE_ERR_IRQ_ENABLE 0xea0
327 #define PHB_RXE_TCE_ERR_FREEZE_ENABLE 0xea8
328 #define PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE 0xeb0
329 #define PHB_RXE_TCE_ERR_LOG_0 0xec0
330 #define PHB_RXE_TCE_ERR_LOG_1 0xec8
331 #define PHB_RXE_TCE_ERR_STATUS_MASK 0xed0
332 #define PHB_RXE_TCE_ERR1_STATUS_MASK 0xed8
335 #define PHB_TRACE_CONTROL 0xf80
336 #define PHB_PERFMON_CONFIG 0xf88
337 #define PHB_PERFMON_CTR0 0xf90
338 #define PHB_PERFMON_CTR1 0xf98
339 #define PHB_PERFMON_CTR2 0xfa0
340 #define PHB_PERFMON_CTR3 0xfa8
343 #define PHB_RC_CONFIG_BASE 0x1000
344 #define PHB_RC_CONFIG_SIZE 0x800
349 #define PHB_PBL_CONTROL 0x1800
350 #define PHB_PBL_TIMEOUT_CTRL 0x1810
351 #define PHB_PBL_NPTAG_ENABLE 0x1820
352 #define PHB_PBL_NBW_CMP_MASK 0x1830
354 #define PHB_PBL_SYS_LINK_INIT 0x1838
355 #define PHB_PBL_BUF_STATUS 0x1840
356 #define PHB_PBL_ERR_STATUS 0x1900
357 #define PHB_PBL_ERR1_STATUS 0x1908
358 #define PHB_PBL_ERR_INJECT 0x1910
359 #define PHB_PBL_ERR_INF_ENABLE 0x1920
360 #define PHB_PBL_ERR_ERC_ENABLE 0x1928
361 #define PHB_PBL_ERR_FAT_ENABLE 0x1930
362 #define PHB_PBL_ERR_LOG_0 0x1940
363 #define PHB_PBL_ERR_LOG_1 0x1948
364 #define PHB_PBL_ERR_STATUS_MASK 0x1950
365 #define PHB_PBL_ERR1_STATUS_MASK 0x1958
368 #define PHB_PCIE_SCR 0x1A00
373 #define PHB_PCIE_CRESET 0x1A10
374 #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0)
381 #define PHB_PCIE_HOTPLUG_STATUS 0x1A20
384 #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40
388 #define PHB_PCIE_DLP_LTSSM_RESET 0
404 #define PHB_PCIE_DLP_CTL 0x1A78
408 #define PHB_PCIE_DLP_TRWCTL 0x1A80
409 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0)
411 #define PHB_PCIE_DLP_ERRLOG1 0x1AA0
412 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8
413 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0
414 #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8
416 #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0
417 #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8
418 #define PHB_PCIE_LANE_EQ_CNTL2 0x1AE0
419 #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8
420 #define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0
421 #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8
422 #define PHB_PCIE_LANE_EQ_CNTL22 0x1B00 /* DD1 only */
423 #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */
424 #define PHB_PCIE_TRACE_CTRL 0x1B20
425 #define PHB_PCIE_MISC_STRAP 0x1B30
428 #define PHB_REGB_ERR_STATUS 0x1C00
429 #define PHB_REGB_ERR1_STATUS 0x1C08
430 #define PHB_REGB_ERR_INJECT 0x1C10
431 #define PHB_REGB_ERR_INF_ENABLE 0x1C20
432 #define PHB_REGB_ERR_ERC_ENABLE 0x1C28
433 #define PHB_REGB_ERR_FAT_ENABLE 0x1C30
434 #define PHB_REGB_ERR_LOG_0 0x1C40
435 #define PHB_REGB_ERR_LOG_1 0x1C48
436 #define PHB_REGB_ERR_STATUS_MASK 0x1C50
437 #define PHB_REGB_ERR1_STATUS_MASK 0x1C58
462 #define IODA3_MIST_P3 PPC_BIT(48 + 0)
467 #define IODA3_TVT_TABLE_ADDR PPC_BITMASK(0, 47)
469 #define IODA3_TVE_1_LEVEL 0
479 #define IODA3_PESTA_MMIO_FROZEN PPC_BIT(0)
481 #define IODA3_PESTA_TRANS_TYPE_MMIOLOAD 0x4
486 #define IODA3_PESTB_DMA_STOPPED PPC_BIT(0)
490 #define IODA3_MDT_PE_A PPC_BITMASK(0, 15)
496 #define IODA3_MBT0_ENABLE PPC_BIT(0)
499 #define IODA3_MBT0_TYPE_M64 0
501 #define IODA3_MBT0_MODE_PE_SEG 0
505 #define IODA3_MBT0_SEG_DIV_MAX 0
512 #define IODA3_MBT1_ENABLE PPC_BIT(0)
531 #define PEST_TTYPE_DMA_WRITE 0