1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 242e872a4SBenoit Cousson /* 342e872a4SBenoit Cousson * OMAP54xx PRM instance offset macros 442e872a4SBenoit Cousson * 53aa36fddSAlexander A. Klimov * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 642e872a4SBenoit Cousson * 742e872a4SBenoit Cousson * Paul Walmsley (paul@pwsan.com) 842e872a4SBenoit Cousson * Rajendra Nayak (rnayak@ti.com) 942e872a4SBenoit Cousson * Benoit Cousson (b-cousson@ti.com) 1042e872a4SBenoit Cousson * 1142e872a4SBenoit Cousson * This file is automatically generated from the OMAP hardware databases. 1242e872a4SBenoit Cousson * We respectfully ask that any modifications to this file be coordinated 1342e872a4SBenoit Cousson * with the public linux-omap@vger.kernel.org mailing list and the 1442e872a4SBenoit Cousson * authors above to ensure that the autogeneration scripts are kept 1542e872a4SBenoit Cousson * up-to-date with the file contents. 1642e872a4SBenoit Cousson */ 1742e872a4SBenoit Cousson 1842e872a4SBenoit Cousson #ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H 1942e872a4SBenoit Cousson #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H 2042e872a4SBenoit Cousson 2142e872a4SBenoit Cousson #include "prm44xx_54xx.h" 2242e872a4SBenoit Cousson #include "prm.h" 2342e872a4SBenoit Cousson 2442e872a4SBenoit Cousson #define OMAP54XX_PRM_BASE 0x4ae06000 2542e872a4SBenoit Cousson 2642e872a4SBenoit Cousson #define OMAP54XX_PRM_REGADDR(inst, reg) \ 2742e872a4SBenoit Cousson OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg)) 2842e872a4SBenoit Cousson 2942e872a4SBenoit Cousson 3042e872a4SBenoit Cousson /* PRM instances */ 3142e872a4SBenoit Cousson #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000 3242e872a4SBenoit Cousson #define OMAP54XX_PRM_CKGEN_INST 0x0100 3342e872a4SBenoit Cousson #define OMAP54XX_PRM_MPU_INST 0x0300 3442e872a4SBenoit Cousson #define OMAP54XX_PRM_DSP_INST 0x0400 3542e872a4SBenoit Cousson #define OMAP54XX_PRM_ABE_INST 0x0500 3642e872a4SBenoit Cousson #define OMAP54XX_PRM_COREAON_INST 0x0600 3742e872a4SBenoit Cousson #define OMAP54XX_PRM_CORE_INST 0x0700 3842e872a4SBenoit Cousson #define OMAP54XX_PRM_IVA_INST 0x1200 3942e872a4SBenoit Cousson #define OMAP54XX_PRM_CAM_INST 0x1300 4042e872a4SBenoit Cousson #define OMAP54XX_PRM_DSS_INST 0x1400 4142e872a4SBenoit Cousson #define OMAP54XX_PRM_GPU_INST 0x1500 4242e872a4SBenoit Cousson #define OMAP54XX_PRM_L3INIT_INST 0x1600 4342e872a4SBenoit Cousson #define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700 4442e872a4SBenoit Cousson #define OMAP54XX_PRM_WKUPAON_INST 0x1800 4542e872a4SBenoit Cousson #define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900 4642e872a4SBenoit Cousson #define OMAP54XX_PRM_EMU_INST 0x1a00 4742e872a4SBenoit Cousson #define OMAP54XX_PRM_EMU_CM_INST 0x1b00 4842e872a4SBenoit Cousson #define OMAP54XX_PRM_DEVICE_INST 0x1c00 4942e872a4SBenoit Cousson 5042e872a4SBenoit Cousson /* PRM clockdomain register offsets (from instance start) */ 5142e872a4SBenoit Cousson #define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 5242e872a4SBenoit Cousson #define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 5342e872a4SBenoit Cousson 5442e872a4SBenoit Cousson /* PRM.DEVICE_PRM register offsets */ 5542e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 5642e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 5742e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c 5842e872a4SBenoit Cousson 5942e872a4SBenoit Cousson #endif 60