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/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-phy-7nm.yaml40 Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
61 reg = <0x0ae94400 0x200>,
62 <0x0ae94600 0x280>,
63 <0x0ae94900 0x260>;
69 #phy-cells = <0>;
H A Ddsi-phy-14nm.yaml63 reg = <0x0ae94400 0x200>,
64 <0x0ae94600 0x280>,
65 <0x0ae94a00 0x1e0>;
71 #phy-cells = <0>;
H A Ddsi-phy-10nm.yaml82 reg = <0x0ae94400 0x200>,
83 <0x0ae94600 0x280>,
84 <0x0ae94a00 0x1e0>;
90 #phy-cells = <0>;
97 qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
98 qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
H A Dqcom,sm6350-mdss.yaml44 "^display-controller@[0-9a-f]+$":
50 "^dsi@[0-9a-f]+$":
58 "^phy@[0-9a-f]+$":
76 reg = <0x0ae00000 0x1000>;
90 iommus = <&apps_smmu 0x800 0x2>;
97 reg = <0x0ae01000 0x8f000>,
98 <0x0aeb0000 0x2008>;
120 interrupts = <0>;
126 #size-cells = <0>;
128 port@0 {
[all …]
H A Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
49 "^displayport-controller@[0-9a-f]+$":
55 "^dsi@[0-9a-f]+$":
63 "^phy@[0-9a-f]+$":
86 reg = <0x0ae00000 0x1000>;
98 iommus = <&apps_smmu 0x880 0x8>,
99 <&apps_smmu 0xc80 0x8>;
104 reg = <0x0ae01000 0x8f000>,
105 <0x0aeb0000 0x2008>;
116 interrupts = <0>;
[all …]
H A Dqcom,sc7180-mdss.yaml45 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
89 reg = <0xae00000 0x1000>;
104 iommus = <&apps_smmu 0x800 0x2>;
109 reg = <0x0ae01000 0x8f000>,
110 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
130 #size-cells = <0>;
[all …]
H A Dqcom,sm8250-mdss.yaml47 "^display-controller@[0-9a-f]+$":
53 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
83 reg = <0x0ae00000 0x1000>;
102 iommus = <&apps_smmu 0x820 0x402>;
110 reg = <0x0ae01000 0x8f000>,
111 <0x0aeb0000 0x2008>;
127 interrupts = <0>;
131 #size-cells = <0>;
133 port@0 {
[all …]
H A Dqcom,sm8150-mdss.yaml48 "^display-controller@[0-9a-f]+$":
54 "^dsi@[0-9a-f]+$":
62 "^phy@[0-9a-f]+$":
81 reg = <0x0ae00000 0x1000>;
100 iommus = <&apps_smmu 0x800 0x420>;
108 reg = <0x0ae01000 0x8f000>,
109 <0x0aeb0000 0x2008>;
125 interrupts = <0>;
129 #size-cells = <0>;
131 port@0 {
[all …]
H A Dqcom,sm8450-mdss.yaml39 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
53 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
83 reg = <0x0ae00000 0x1000>;
86 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
87 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
104 iommus = <&apps_smmu 0x2800 0x402>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
[all …]
H A Dqcom,sc7280-mdss.yaml45 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
65 "^edp@[0-9a-f]+$":
71 "^phy@[0-9a-f]+$":
97 reg = <0xae00000 0x1000>;
114 iommus = <&apps_smmu 0x900 0x402>;
119 reg = <0x0ae01000 0x8f000>,
120 <0x0aeb0000 0x2008>;
138 interrupts = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8180x.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
57 clocks = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
86 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi36 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #size-cells = <0>;
52 CPU0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #size-cells = <0>;
77 CPU0: cpu@0 {
80 reg = <0x0 0x0>;
81 clocks = <&cpufreq_hw 0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x100>;
110 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8450.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc7280.dtsi78 #clock-cells = <0>;
84 #clock-cells = <0>;
95 reg = <0x0 0x004cd000 0x0 0x1000>;
99 reg = <0x0 0x80000000 0x0 0x600000>;
104 reg = <0x0 0x80600000 0x0 0x200000>;
109 reg = <0x0 0x80800000 0x0 0x60000>;
114 reg = <0x0 0x80860000 0x0 0x20000>;
120 reg = <0x0 0x80884000 0x0 0x10000>;
125 reg = <0x0 0x808ff000 0x0 0x1000>;
130 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 CPU0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]