Lines Matching +full:0 +full:x0ae94600
81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 CPU0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
131 reg = <0x0 0x100>;
132 clocks = <&cpufreq_hw 0>;
139 qcom,freq-domain = <&cpufreq_hw 0>;
141 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
147 cache-size = <0x20000>;
156 reg = <0x0 0x200>;
157 clocks = <&cpufreq_hw 0>;
164 qcom,freq-domain = <&cpufreq_hw 0>;
166 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
172 cache-size = <0x20000>;
181 reg = <0x0 0x300>;
182 clocks = <&cpufreq_hw 0>;
189 qcom,freq-domain = <&cpufreq_hw 0>;
191 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
197 cache-size = <0x20000>;
206 reg = <0x0 0x400>;
216 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
222 cache-size = <0x40000>;
231 reg = <0x0 0x500>;
241 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
247 cache-size = <0x40000>;
256 reg = <0x0 0x600>;
266 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
272 cache-size = <0x40000>;
281 reg = <0x0 0x700>;
291 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
297 cache-size = <0x80000>;
342 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
345 arm,psci-suspend-param = <0x40000004>;
352 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
355 arm,psci-suspend-param = <0x40000004>;
364 CLUSTER_SLEEP_0: cluster-sleep-0 {
366 arm,psci-suspend-param = <0x4100c244>;
674 reg = <0x0 0x80000000 0x0 0x0>;
687 #power-domain-cells = <0>;
693 #power-domain-cells = <0>;
699 #power-domain-cells = <0>;
705 #power-domain-cells = <0>;
711 #power-domain-cells = <0>;
717 #power-domain-cells = <0>;
723 #power-domain-cells = <0>;
729 #power-domain-cells = <0>;
735 #power-domain-cells = <0>;
765 reg = <0x0 0x80000000 0x0 0x600000>;
770 reg = <0x0 0x80700000 0x0 0x160000>;
776 reg = <0x0 0x80860000 0x0 0x20000>;
781 reg = <0x0 0x80900000 0x0 0x200000>;
786 reg = <0x0 0x80b00000 0x0 0x5300000>;
791 reg = <0x0 0x86200000 0x0 0x500000>;
796 reg = <0x0 0x86700000 0x0 0x100000>;
801 reg = <0x0 0x86800000 0x0 0x10000>;
806 reg = <0x0 0x86810000 0x0 0xa000>;
811 reg = <0x0 0x8681a000 0x0 0x2000>;
816 reg = <0x0 0x86900000 0x0 0x500000>;
821 reg = <0x0 0x86e00000 0x0 0x500000>;
826 reg = <0x0 0x87300000 0x0 0x500000>;
831 reg = <0x0 0x87800000 0x0 0x1400000>;
836 reg = <0x0 0x88c00000 0x0 0x1500000>;
841 reg = <0x0 0x8a100000 0x0 0x1d00000>;
846 reg = <0x0 0x8be00000 0x0 0x100000>;
851 reg = <0x0 0x8bf00000 0x0 0x4600000>;
871 qcom,local-pid = <0>;
895 qcom,local-pid = <0>;
919 qcom,local-pid = <0>;
934 soc: soc@0 {
937 ranges = <0 0 0 0 0x10 0>;
938 dma-ranges = <0 0 0 0 0x10 0>;
943 reg = <0x0 0x00100000 0x0 0x1f0000>;
957 reg = <0 0x00408000 0 0x1000>;
966 reg = <0 0x00784000 0 0x8ff>;
971 reg = <0x19b 0x1>;
978 reg = <0 0x00793000 0 0x1000>;
985 reg = <0 0x00800000 0 0x70000>;
997 dma-channel-mask = <0x3f>;
998 iommus = <&apps_smmu 0x76 0x0>;
1005 reg = <0x0 0x008c0000 0x0 0x6000>;
1011 iommus = <&apps_smmu 0x63 0x0>;
1017 reg = <0 0x00880000 0 0x4000>;
1021 pinctrl-0 = <&qup_i2c14_default>;
1023 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1024 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1027 #size-cells = <0>;
1033 reg = <0 0x00880000 0 0x4000>;
1037 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1038 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1043 #size-cells = <0>;
1049 reg = <0 0x00884000 0 0x4000>;
1053 pinctrl-0 = <&qup_i2c15_default>;
1055 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1059 #size-cells = <0>;
1065 reg = <0 0x00884000 0 0x4000>;
1069 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1075 #size-cells = <0>;
1081 reg = <0 0x00888000 0 0x4000>;
1085 pinctrl-0 = <&qup_i2c16_default>;
1087 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1091 #size-cells = <0>;
1097 reg = <0 0x00888000 0 0x4000>;
1101 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1107 #size-cells = <0>;
1113 reg = <0 0x0088c000 0 0x4000>;
1117 pinctrl-0 = <&qup_i2c17_default>;
1119 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1123 #size-cells = <0>;
1129 reg = <0 0x0088c000 0 0x4000>;
1133 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1139 #size-cells = <0>;
1145 reg = <0 0x0088c000 0 0x4000>;
1149 pinctrl-0 = <&qup_uart17_default>;
1158 reg = <0 0x00890000 0 0x4000>;
1162 pinctrl-0 = <&qup_i2c18_default>;
1164 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1168 #size-cells = <0>;
1174 reg = <0 0x00890000 0 0x4000>;
1178 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1184 #size-cells = <0>;
1190 reg = <0 0x00890000 0 0x4000>;
1194 pinctrl-0 = <&qup_uart18_default>;
1203 reg = <0 0x00894000 0 0x4000>;
1207 pinctrl-0 = <&qup_i2c19_default>;
1209 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1213 #size-cells = <0>;
1219 reg = <0 0x00894000 0 0x4000>;
1223 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1229 #size-cells = <0>;
1236 reg = <0 0x00900000 0 0x70000>;
1251 dma-channel-mask = <0x7ff>;
1252 iommus = <&apps_smmu 0x5b6 0x0>;
1259 reg = <0x0 0x009c0000 0x0 0x6000>;
1265 iommus = <&apps_smmu 0x5a3 0x0>;
1271 reg = <0 0x00980000 0 0x4000>;
1275 pinctrl-0 = <&qup_i2c0_default>;
1277 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1278 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1281 #size-cells = <0>;
1287 reg = <0 0x00980000 0 0x4000>;
1291 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1292 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1297 #size-cells = <0>;
1303 reg = <0 0x00984000 0 0x4000>;
1307 pinctrl-0 = <&qup_i2c1_default>;
1309 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1313 #size-cells = <0>;
1319 reg = <0 0x00984000 0 0x4000>;
1323 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1329 #size-cells = <0>;
1335 reg = <0 0x00988000 0 0x4000>;
1339 pinctrl-0 = <&qup_i2c2_default>;
1341 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1345 #size-cells = <0>;
1351 reg = <0 0x00988000 0 0x4000>;
1355 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1361 #size-cells = <0>;
1367 reg = <0 0x00988000 0 0x4000>;
1371 pinctrl-0 = <&qup_uart2_default>;
1380 reg = <0 0x0098c000 0 0x4000>;
1384 pinctrl-0 = <&qup_i2c3_default>;
1386 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1390 #size-cells = <0>;
1396 reg = <0 0x0098c000 0 0x4000>;
1400 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1406 #size-cells = <0>;
1412 reg = <0 0x00990000 0 0x4000>;
1416 pinctrl-0 = <&qup_i2c4_default>;
1418 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1422 #size-cells = <0>;
1428 reg = <0 0x00990000 0 0x4000>;
1432 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1438 #size-cells = <0>;
1444 reg = <0 0x00994000 0 0x4000>;
1448 pinctrl-0 = <&qup_i2c5_default>;
1450 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1454 #size-cells = <0>;
1460 reg = <0 0x00994000 0 0x4000>;
1464 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1470 #size-cells = <0>;
1476 reg = <0 0x00998000 0 0x4000>;
1480 pinctrl-0 = <&qup_i2c6_default>;
1482 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1486 #size-cells = <0>;
1492 reg = <0 0x00998000 0 0x4000>;
1496 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1502 #size-cells = <0>;
1508 reg = <0 0x00998000 0 0x4000>;
1512 pinctrl-0 = <&qup_uart6_default>;
1521 reg = <0 0x0099c000 0 0x4000>;
1525 pinctrl-0 = <&qup_i2c7_default>;
1527 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1531 #size-cells = <0>;
1537 reg = <0 0x0099c000 0 0x4000>;
1541 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1547 #size-cells = <0>;
1554 reg = <0 0x00a00000 0 0x70000>;
1566 dma-channel-mask = <0x3f>;
1567 iommus = <&apps_smmu 0x56 0x0>;
1574 reg = <0x0 0x00ac0000 0x0 0x6000>;
1580 iommus = <&apps_smmu 0x43 0x0>;
1586 reg = <0 0x00a80000 0 0x4000>;
1590 pinctrl-0 = <&qup_i2c8_default>;
1592 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1593 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1596 #size-cells = <0>;
1602 reg = <0 0x00a80000 0 0x4000>;
1606 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1607 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1612 #size-cells = <0>;
1618 reg = <0 0x00a84000 0 0x4000>;
1622 pinctrl-0 = <&qup_i2c9_default>;
1624 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1628 #size-cells = <0>;
1634 reg = <0 0x00a84000 0 0x4000>;
1638 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1644 #size-cells = <0>;
1650 reg = <0 0x00a88000 0 0x4000>;
1654 pinctrl-0 = <&qup_i2c10_default>;
1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1660 #size-cells = <0>;
1666 reg = <0 0x00a88000 0 0x4000>;
1670 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1676 #size-cells = <0>;
1682 reg = <0 0x00a8c000 0 0x4000>;
1686 pinctrl-0 = <&qup_i2c11_default>;
1688 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1692 #size-cells = <0>;
1698 reg = <0 0x00a8c000 0 0x4000>;
1702 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1708 #size-cells = <0>;
1714 reg = <0 0x00a90000 0 0x4000>;
1718 pinctrl-0 = <&qup_i2c12_default>;
1720 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1724 #size-cells = <0>;
1730 reg = <0 0x00a90000 0 0x4000>;
1734 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1740 #size-cells = <0>;
1746 reg = <0x0 0x00a90000 0x0 0x4000>;
1750 pinctrl-0 = <&qup_uart12_default>;
1759 reg = <0 0x00a94000 0 0x4000>;
1763 pinctrl-0 = <&qup_i2c13_default>;
1765 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1769 #size-cells = <0>;
1775 reg = <0 0x00a94000 0 0x4000>;
1779 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1785 #size-cells = <0>;
1792 reg = <0 0x01500000 0 0xa580>;
1799 reg = <0 0x01620000 0 0x1c200>;
1806 reg = <0 0x0163d000 0 0x1000>;
1813 reg = <0 0x016e0000 0 0x1f180>;
1820 reg = <0 0x01700000 0 0x33000>;
1827 reg = <0 0x01733000 0 0xa180>;
1834 reg = <0 0x01740000 0 0x1f080>;
1841 reg = <0 0x01c00000 0 0x3000>,
1842 <0 0x60000000 0 0xf1d>,
1843 <0 0x60000f20 0 0xa8>,
1844 <0 0x60001000 0 0x1000>,
1845 <0 0x60100000 0 0x100000>,
1846 <0 0x01c03000 0 0x1000>;
1849 linux,pci-domain = <0>;
1850 bus-range = <0x00 0xff>;
1856 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1857 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1870 interrupt-map-mask = <0 0 0 0x7>;
1871 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1872 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1873 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1874 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1893 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1894 <0x100 &apps_smmu 0x1c01 0x1>;
1908 pinctrl-0 = <&pcie0_default_state>;
1916 reg = <0 0x01c06000 0 0x1c0>;
1935 reg = <0 0x01c06200 0 0x170>, /* tx */
1936 <0 0x01c06400 0 0x200>, /* rx */
1937 <0 0x01c06800 0 0x1f0>, /* pcs */
1938 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1942 #phy-cells = <0>;
1944 #clock-cells = <0>;
1951 reg = <0 0x01c08000 0 0x3000>,
1952 <0 0x40000000 0 0xf1d>,
1953 <0 0x40000f20 0 0xa8>,
1954 <0 0x40001000 0 0x1000>,
1955 <0 0x40100000 0 0x100000>,
1956 <0 0x01c0b000 0 0x1000>;
1960 bus-range = <0x00 0xff>;
1966 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1967 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1972 interrupt-map-mask = <0 0 0 0x7>;
1973 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1974 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1975 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1976 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2000 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2001 <0x100 &apps_smmu 0x1c81 0x1>;
2015 pinctrl-0 = <&pcie1_default_state>;
2023 reg = <0 0x01c0e000 0 0x1c0>;
2042 reg = <0 0x01c0e200 0 0x170>, /* tx0 */
2043 <0 0x01c0e400 0 0x200>, /* rx0 */
2044 <0 0x01c0ea00 0 0x1f0>, /* pcs */
2045 <0 0x01c0e600 0 0x170>, /* tx1 */
2046 <0 0x01c0e800 0 0x200>, /* rx1 */
2047 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2051 #phy-cells = <0>;
2053 #clock-cells = <0>;
2060 reg = <0 0x01c10000 0 0x3000>,
2061 <0 0x64000000 0 0xf1d>,
2062 <0 0x64000f20 0 0xa8>,
2063 <0 0x64001000 0 0x1000>,
2064 <0 0x64100000 0 0x100000>,
2065 <0 0x01c13000 0 0x1000>;
2069 bus-range = <0x00 0xff>;
2075 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2076 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2081 interrupt-map-mask = <0 0 0 0x7>;
2082 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2083 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2084 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2085 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2109 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2110 <0x100 &apps_smmu 0x1d01 0x1>;
2124 pinctrl-0 = <&pcie2_default_state>;
2132 reg = <0 0x01c16000 0 0x1c0>;
2151 reg = <0 0x01c16200 0 0x170>, /* tx0 */
2152 <0 0x01c16400 0 0x200>, /* rx0 */
2153 <0 0x01c16a00 0 0x1f0>, /* pcs */
2154 <0 0x01c16600 0 0x170>, /* tx1 */
2155 <0 0x01c16800 0 0x200>, /* rx1 */
2156 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2160 #phy-cells = <0>;
2162 #clock-cells = <0>;
2170 reg = <0 0x01d84000 0 0x3000>;
2181 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2203 <0 0>,
2204 <0 0>,
2206 <0 0>,
2207 <0 0>,
2208 <0 0>,
2209 <0 0>;
2211 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2212 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2220 reg = <0 0x01d87000 0 0x1000>;
2227 resets = <&ufs_mem_hc 0>;
2232 #phy-cells = <0>;
2239 reg = <0 0x01dc4000 0 0x24000>;
2242 qcom,ee = <0>;
2246 iommus = <&apps_smmu 0x592 0x0000>,
2247 <&apps_smmu 0x598 0x0000>,
2248 <&apps_smmu 0x599 0x0000>,
2249 <&apps_smmu 0x59f 0x0000>,
2250 <&apps_smmu 0x586 0x0011>,
2251 <&apps_smmu 0x596 0x0011>;
2256 reg = <0 0x01dfa000 0 0x6000>;
2259 iommus = <&apps_smmu 0x592 0x0000>,
2260 <&apps_smmu 0x598 0x0000>,
2261 <&apps_smmu 0x599 0x0000>,
2262 <&apps_smmu 0x59f 0x0000>,
2263 <&apps_smmu 0x586 0x0011>,
2264 <&apps_smmu 0x596 0x0011>;
2265 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2271 reg = <0x0 0x01f40000 0x0 0x40000>;
2277 reg = <0 0x03240000 0 0x1000>;
2287 #clock-cells = <0>;
2292 pinctrl-0 = <&wsa_swr_active>;
2298 reg = <0 0x03250000 0 0x2000>;
2307 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2308 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2309 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2310 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2314 #size-cells = <0>;
2321 reg = <0 0x03300000 0 0x30000>;
2331 reg = <0 0x03370000 0 0x1000>;
2338 #clock-cells = <0>;
2345 pinctrl-0 = <&rx_swr_active>;
2347 reg = <0 0x03200000 0 0x1000>;
2358 #clock-cells = <0>;
2364 reg = <0 0x03210000 0 0x2000>;
2371 qcom,din-ports = <0>;
2374 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2375 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2376 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2377 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2378 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2379 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2380 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2381 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2382 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2386 #size-cells = <0>;
2391 pinctrl-0 = <&tx_swr_active>;
2393 reg = <0 0x03220000 0 0x1000>;
2404 #clock-cells = <0>;
2411 reg = <0 0x03230000 0 0x2000>;
2422 qcom,dout-ports = <0>;
2423 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2424 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2425 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2426 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2427 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2428 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2429 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2430 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2431 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2434 #size-cells = <0>;
2439 reg = <0 0x03380000 0 0x40000>;
2449 reg = <0 0x033c0000 0x0 0x20000>,
2450 <0 0x03550000 0x0 0x10000>;
2453 gpio-ranges = <&lpass_tlmm 0 0 14>;
2588 reg = <0 0x03d00000 0 0x40000>;
2593 iommus = <&adreno_smmu 0 0x401>;
2614 opp-supported-hw = <0xa>;
2620 opp-supported-hw = <0xb>;
2626 opp-supported-hw = <0xf>;
2632 opp-supported-hw = <0xf>;
2638 opp-supported-hw = <0xf>;
2644 opp-supported-hw = <0xf>;
2650 opp-supported-hw = <0xf>;
2658 reg = <0 0x03d6a000 0 0x30000>,
2659 <0 0x3de0000 0 0x10000>,
2660 <0 0xb290000 0 0x10000>,
2661 <0 0xb490000 0 0x10000>;
2679 iommus = <&adreno_smmu 5 0x400>;
2697 reg = <0 0x03d90000 0 0x9000>;
2712 reg = <0 0x03da0000 0 0x10000>;
2736 reg = <0 0x05c00000 0 0x4000>;
2739 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2757 qcom,smem-states = <&smp2p_slpi_out 0>;
2778 #size-cells = <0>;
2783 iommus = <&apps_smmu 0x0541 0x0>;
2789 iommus = <&apps_smmu 0x0542 0x0>;
2795 iommus = <&apps_smmu 0x0543 0x0>;
2804 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
2821 reg = <0 0x06004000 0 0x1000>;
2837 #size-cells = <0>;
2857 reg = <0 0x06005000 0 0x1000>;
2881 reg = <0 0x06041000 0 0x1000>;
2896 #size-cells = <0>;
2916 reg = <0 0x06042000 0 0x1000>;
2931 #size-cells = <0>;
2944 reg = <0 0x06045000 0 0x1000>;
2959 #size-cells = <0>;
2961 port@0 {
2962 reg = <0>;
2979 reg = <0 0x06046000 0 0x1000>;
3003 reg = <0 0x06048000 0 0x1000>;
3020 reg = <0 0x0684c000 0 0x1000>;
3036 arm,primecell-periphid = <0x000bb908>;
3038 reg = <0 0x06b04000 0 0x1000>;
3053 #size-cells = <0>;
3066 reg = <0 0x06b05000 0 0x1000>;
3091 reg = <0 0x06b06000 0 0x1000>;
3115 reg = <0 0x06c08000 0 0x1000>;
3131 reg = <0 0x06c0b000 0 0x1000>;
3146 #size-cells = <0>;
3159 reg = <0 0x06c2d000 0 0x1000>;
3174 #size-cells = <0>;
3187 reg = <0 0x07040000 0 0x1000>;
3206 reg = <0 0x07140000 0 0x1000>;
3225 reg = <0 0x07240000 0 0x1000>;
3244 reg = <0 0x07340000 0 0x1000>;
3263 reg = <0 0x07440000 0 0x1000>;
3282 reg = <0 0x07540000 0 0x1000>;
3301 reg = <0 0x07640000 0 0x1000>;
3320 reg = <0 0x07740000 0 0x1000>;
3339 reg = <0 0x07800000 0 0x1000>;
3354 #size-cells = <0>;
3356 port@0 {
3357 reg = <0>;
3416 reg = <0 0x07810000 0 0x1000>;
3440 reg = <0 0x08300000 0 0x10000>;
3443 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3459 qcom,smem-states = <&smp2p_cdsp_out 0>;
3480 #size-cells = <0>;
3485 iommus = <&apps_smmu 0x1001 0x0460>;
3491 iommus = <&apps_smmu 0x1002 0x0460>;
3497 iommus = <&apps_smmu 0x1003 0x0460>;
3503 iommus = <&apps_smmu 0x1004 0x0460>;
3509 iommus = <&apps_smmu 0x1005 0x0460>;
3515 iommus = <&apps_smmu 0x1006 0x0460>;
3521 iommus = <&apps_smmu 0x1007 0x0460>;
3527 iommus = <&apps_smmu 0x1008 0x0460>;
3538 reg = <0 0x088e3000 0 0x400>;
3540 #phy-cells = <0>;
3551 reg = <0 0x088e4000 0 0x400>;
3553 #phy-cells = <0>;
3563 reg = <0 0x088e9000 0 0x200>,
3564 <0 0x088e8000 0 0x40>,
3565 <0 0x088ea000 0 0x200>;
3581 reg = <0 0x088e9200 0 0x200>,
3582 <0 0x088e9400 0 0x200>,
3583 <0 0x088e9c00 0 0x400>,
3584 <0 0x088e9600 0 0x200>,
3585 <0 0x088e9800 0 0x200>,
3586 <0 0x088e9a00 0 0x100>;
3587 #clock-cells = <0>;
3588 #phy-cells = <0>;
3595 reg = <0 0x088ea200 0 0x200>,
3596 <0 0x088ea400 0 0x200>,
3597 <0 0x088eaa00 0 0x200>,
3598 <0 0x088ea600 0 0x200>,
3599 <0 0x088ea800 0 0x200>;
3600 #phy-cells = <0>;
3607 reg = <0 0x088eb000 0 0x200>;
3624 reg = <0 0x088eb200 0 0x200>,
3625 <0 0x088eb400 0 0x200>,
3626 <0 0x088eb800 0 0x800>;
3627 #clock-cells = <0>;
3628 #phy-cells = <0>;
3637 reg = <0 0x08804000 0 0x1000>;
3647 iommus = <&apps_smmu 0x4a0 0x0>;
3648 qcom,dll-config = <0x0007642c>;
3649 qcom,ddr-config = <0x80040868>;
3682 reg = <0 0x09091000 0 0x1000>;
3744 reg = <0 0x090b6400 0 0x600>;
3804 reg = <0 0x090c0000 0 0x4200>;
3811 reg = <0 0x09100000 0 0xb4000>;
3818 reg = <0 0x09990000 0 0x1600>;
3825 reg = <0 0x0a6f8800 0 0x400>;
3862 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3863 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3868 reg = <0 0x0a600000 0 0xcd00>;
3870 iommus = <&apps_smmu 0x0 0x0>;
3880 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
3881 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
3882 <0 0x09600000 0 0x50000>;
3889 reg = <0 0x0a8f8800 0 0x400>;
3926 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3927 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3932 reg = <0 0x0a800000 0 0xcd00>;
3934 iommus = <&apps_smmu 0x20 0>;
3944 reg = <0 0x0aa00000 0 0x100000>;
3957 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
3958 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
3961 iommus = <&apps_smmu 0x2100 0x0400>;
4005 reg = <0 0x0abf0000 0 0x10000>;
4020 #size-cells = <0>;
4022 reg = <0 0x0ac4f000 0 0x1000>;
4037 pinctrl-0 = <&cci0_default>;
4043 cci0_i2c0: i2c-bus@0 {
4044 reg = <0>;
4047 #size-cells = <0>;
4054 #size-cells = <0>;
4061 #size-cells = <0>;
4063 reg = <0 0x0ac50000 0 0x1000>;
4078 pinctrl-0 = <&cci1_default>;
4084 cci1_i2c0: i2c-bus@0 {
4085 reg = <0>;
4088 #size-cells = <0>;
4095 #size-cells = <0>;
4103 reg = <0 0x0ac6a000 0 0x2000>,
4104 <0 0x0ac6c000 0 0x2000>,
4105 <0 0x0ac6e000 0 0x1000>,
4106 <0 0x0ac70000 0 0x1000>,
4107 <0 0x0ac72000 0 0x1000>,
4108 <0 0x0ac74000 0 0x1000>,
4109 <0 0x0acb4000 0 0xd000>,
4110 <0 0x0acc3000 0 0xd000>,
4111 <0 0x0acd9000 0 0x2200>,
4112 <0 0x0acdb200 0 0x2200>;
4233 iommus = <&apps_smmu 0x800 0x400>,
4234 <&apps_smmu 0x801 0x400>,
4235 <&apps_smmu 0x840 0x400>,
4236 <&apps_smmu 0x841 0x400>,
4237 <&apps_smmu 0xc00 0x400>,
4238 <&apps_smmu 0xc01 0x400>,
4239 <&apps_smmu 0xc40 0x400>,
4240 <&apps_smmu 0xc41 0x400>;
4242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4243 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4244 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4245 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4253 #size-cells = <0>;
4255 port@0 {
4256 reg = <0>;
4283 reg = <0 0x0ad00000 0 0x10000>;
4299 reg = <0 0x0ae00000 0 0x1000>;
4302 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4303 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4318 iommus = <&apps_smmu 0x820 0x402>;
4328 reg = <0 0x0ae01000 0 0x8f000>,
4329 <0 0x0aeb0000 0 0x2008>;
4345 interrupts = <0>;
4349 #size-cells = <0>;
4351 port@0 {
4352 reg = <0>;
4394 reg = <0 0x0ae94000 0 0x400>;
4414 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4424 #size-cells = <0>;
4428 #size-cells = <0>;
4430 port@0 {
4431 reg = <0>;
4466 reg = <0 0x0ae94400 0 0x200>,
4467 <0 0x0ae94600 0 0x280>,
4468 <0 0x0ae94900 0 0x260>;
4474 #phy-cells = <0>;
4486 reg = <0 0x0ae96000 0 0x400>;
4506 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4516 #size-cells = <0>;
4520 #size-cells = <0>;
4522 port@0 {
4523 reg = <0>;
4539 reg = <0 0x0ae96400 0 0x200>,
4540 <0 0x0ae96600 0 0x280>,
4541 <0 0x0ae96900 0 0x260>;
4547 #phy-cells = <0>;
4559 reg = <0 0x0af00000 0 0x10000>;
4563 <&mdss_dsi0_phy 0>,
4565 <&mdss_dsi1_phy 0>,
4567 <&dp_phy 0>,
4583 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4584 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4593 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4594 <0 0x0c222000 0 0x1ff>; /* SROT */
4604 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4605 <0 0x0c223000 0 0x1ff>; /* SROT */
4615 reg = <0 0x0c300000 0 0x400>;
4622 #clock-cells = <0>;
4627 reg = <0 0x0c3f0000 0 0x400>;
4632 reg = <0x0 0x0c440000 0x0 0x0001100>,
4633 <0x0 0x0c600000 0x0 0x2000000>,
4634 <0x0 0x0e600000 0x0 0x0100000>,
4635 <0x0 0x0e700000 0x0 0x00a0000>,
4636 <0x0 0x0c40a000 0x0 0x0026000>;
4640 qcom,ee = <0>;
4641 qcom,channel = <0>;
4643 #size-cells = <0>;
4650 reg = <0 0x0f100000 0 0x300000>,
4651 <0 0x0f500000 0 0x300000>,
4652 <0 0x0f900000 0 0x300000>;
4659 gpio-ranges = <&tlmm 0 0 181>;
5407 reg = <0 0x15000000 0 0x100000>;
5513 reg = <0 0x17300000 0 0x100>;
5516 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5534 qcom,smem-states = <&smp2p_adsp_out 0>;
5554 #size-cells = <0>;
5569 #size-cells = <0>;
5586 #size-cells = <0>;
5588 iommus = <&apps_smmu 0x1801 0x0>;
5598 #sound-dai-cells = <0>;
5609 #size-cells = <0>;
5614 iommus = <&apps_smmu 0x1803 0x0>;
5620 iommus = <&apps_smmu 0x1804 0x0>;
5626 iommus = <&apps_smmu 0x1805 0x0>;
5636 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5637 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5643 reg = <0 0x17c10000 0 0x1000>;
5645 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5651 ranges = <0 0 0 0x20000000>;
5653 reg = <0x0 0x17c20000 0x0 0x1000>;
5657 frame-number = <0>;
5660 reg = <0x17c21000 0x1000>,
5661 <0x17c22000 0x1000>;
5667 reg = <0x17c23000 0x1000>;
5674 reg = <0x17c25000 0x1000>;
5681 reg = <0x17c27000 0x1000>;
5688 reg = <0x17c29000 0x1000>;
5695 reg = <0x17c2b000 0x1000>;
5702 reg = <0x17c2d000 0x1000>;
5710 reg = <0x0 0x18200000 0x0 0x10000>,
5711 <0x0 0x18210000 0x0 0x10000>,
5712 <0x0 0x18220000 0x0 0x10000>;
5713 reg-names = "drv-0", "drv-1", "drv-2";
5717 qcom,tcs-offset = <0xd00>;
5787 reg = <0 0x18590000 0 0x1000>;
5797 reg = <0 0x18591000 0 0x1000>,
5798 <0 0x18592000 0 0x1000>,
5799 <0 0x18593000 0 0x1000>;
5808 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6362 thermal-sensors = <&tsens0 0>;
6432 thermal-sensors = <&tsens1 0>;