Lines Matching +full:0 +full:x0ae94600

39   "^display-controller@[0-9a-f]+$":
45   "^displayport-controller@[0-9a-f]+$":
53   "^dsi@[0-9a-f]+$":
61   "^phy@[0-9a-f]+$":
83         reg = <0x0ae00000 0x1000>;
86         interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
87                         <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
104         iommus = <&apps_smmu 0x2800 0x402>;
112             reg = <0x0ae01000 0x8f000>,
113                   <0x0aeb0000 0x2008>;
136             interrupts = <0>;
140                 #size-cells = <0>;
142                 port@0 {
143                     reg = <0>;
189             reg = <0x0ae94000 0x400>;
210             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
219             #size-cells = <0>;
223                 #size-cells = <0>;
225                 port@0 {
226                     reg = <0>;
266             reg = <0x0ae94400 0x200>,
267                   <0x0ae94600 0x280>,
268                   <0x0ae94900 0x260>;
274             #phy-cells = <0>;
284             reg = <0x0ae96000 0x400>;
305             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
314             #size-cells = <0>;
318                 #size-cells = <0>;
320                 port@0 {
321                     reg = <0>;
337             reg = <0x0ae96400 0x200>,
338                   <0x0ae96600 0x280>,
339                   <0x0ae96900 0x260>;
345             #phy-cells = <0>;