| /openbmc/u-boot/arch/arm/include/asm/arch-mx7/ |
| H A D | crm_regs.h | 15 #define CCM_GPR0_OFFSET 0x0
16 #define CCM_OBSERVE0_OFFSET 0x0400
17 #define CCM_SCTRL0_OFFSET 0x0800
18 #define CCM_CCGR0_OFFSET 0x4000
19 #define CCM_ROOT0_TARGET_OFFSET 0x8000
58 struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
60 struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
65 uint32_t ctrl_24m; /* offset 0x0000 */
69 uint32_t rcosc_config0; /* offset 0x0010 */
73 uint32_t rcosc_config1; /* offset 0x0020 */
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | cavium-mdio.txt | 15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | config.h | 13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
48 #define GICD_BASE 0x06000000
49 #define GICR_BASE 0x06100000
52 #define SMMU_BASE 0x05000000 /* GR0 Base */
69 #define CCI_MN_BASE 0x04000000
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/amlogic/ |
| H A D | amlogic-t7-a311d2-khadas-vim4.dts | 18 memory@0 {
20 reg = <0x0 0x0 0x2 0x0>; /* 8 GB */
30 reg = <0x0 0x05000000 0x0 0x300000>;
36 reg = <0x0 0x05300000 0x0 0x2000000>;
45 #clock-cells = <0>;
|
| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | cpu_sun50i_h6.h | 11 #define SUNXI_SRAM_C_BASE 0x00028000
12 #define SUNXI_SRAM_A2_BASE 0x00100000
14 #define SUNXI_DE3_BASE 0x01000000
15 #define SUNXI_SS_BASE 0x01904000
16 #define SUNXI_EMCE_BASE 0x01905000
18 #define SUNXI_SRAMC_BASE 0x03000000
19 #define SUNXI_CCM_BASE 0x03001000
20 #define SUNXI_DMA_BASE 0x03002000
21 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
22 #define SUNXI_SIDC_BASE 0x03006000
[all …]
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| /openbmc/linux/drivers/net/ethernet/ibm/emac/ |
| H A D | tah.h | 52 #define TAH_MR_CVR 0x80000000
53 #define TAH_MR_SR 0x40000000
54 #define TAH_MR_ST_256 0x01000000
55 #define TAH_MR_ST_512 0x02000000
56 #define TAH_MR_ST_768 0x03000000
57 #define TAH_MR_ST_1024 0x04000000
58 #define TAH_MR_ST_1280 0x05000000
59 #define TAH_MR_ST_1536 0x06000000
60 #define TAH_MR_TFS_16KB 0x00000000
61 #define TAH_MR_TFS_2KB 0x00200000
[all …]
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | reg_8xx.h | 29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
[all …]
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| /openbmc/linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm53016-dlink-dwl-8610ap.dts | 13 memory@0 {
16 reg = <0x00000000 0x08000000>,
17 <0x88000000 0x08000000>;
26 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
66 * Flash memory at 0x1e000000-0x1fffffff
72 reg = <0x1e080000 0x00020000>;
112 trx@0 {
114 reg = <0x00000000 0x02800000>;
121 reg = <0x02800000 0x02800000>;
128 reg = <0x05000000 0x03000000>;
|
| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | gen7_renderstate.c | 11 0x0000000c,
12 0x00000010,
13 0x00000018,
14 0x000001ec,
19 0x69040000,
20 0x61010008,
21 0x00000000,
22 0x00000001, /* reloc */
23 0x00000001, /* reloc */
24 0x00000000,
[all …]
|
| H A D | gen6_renderstate.c | 11 0x00000020,
12 0x00000024,
13 0x0000002c,
14 0x000001e0,
15 0x000001e4,
20 0x69040000,
21 0x790d0001,
22 0x00000000,
23 0x00000000,
24 0x78180000,
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | exynos-srom.yaml | 35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
53 typically 0 as this is the start of the bank.
77 Tacp: Page mode access cycle at Page mode (0 - 15)
78 Tcah: Address holding time after CSn (0 - 15)
79 Tcoh: Chip selection hold on OEn (0 - 15)
80 Tacc: Access cycle (0 - 31, the actual time is N + 1)
81 Tcos: Chip selection set-up before OEn (0 - 15)
82 Tacs: Address set-up before CSn (0 - 15)
99 reg = <0x12560000 0x14>;
[all …]
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | cache.h | 67 #define CACHECRBA 0x80000823 /* Cache configuration register address */
68 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
69 #define L2CACHE_512KB 0x00 /* 512KB */
70 #define L2CACHE_256KB 0x01 /* 256KB */
71 #define L2CACHE_1MB 0x02 /* 1MB */
72 #define L2CACHE_NONE 0x03 /* NONE */
73 #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
88 #define IDC_ENABLE 0x02000000 /* Cache enable */
89 #define IDC_DISABLE 0x04000000 /* Cache disable */
90 #define IDC_LDLCK 0x06000000 /* Load and lock */
[all …]
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| /openbmc/linux/arch/sh/include/mach-common/mach/ |
| H A D | urquell.h | 6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | elf.h | 25 #define EF_ARM_EABI_MASK 0xff000000
26 #define EF_ARM_EABI_UNKNOWN 0x00000000
27 #define EF_ARM_EABI_VER1 0x01000000
28 #define EF_ARM_EABI_VER2 0x02000000
29 #define EF_ARM_EABI_VER3 0x03000000
30 #define EF_ARM_EABI_VER4 0x04000000
31 #define EF_ARM_EABI_VER5 0x05000000
33 #define EF_ARM_BE8 0x00800000 /* ABI 4,5 */
34 #define EF_ARM_LE8 0x00400000 /* ABI 4,5 */
35 #define EF_ARM_MAVERICK_FLOAT 0x00000800 /* ABI 0 */
[all …]
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| /openbmc/qemu/hw/sparc/ |
| H A D | sun4m.c | 74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
78 #define PROM_VADDR 0xffd00000
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
83 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
131 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { in DECLARE_CLASS_CHECKERS()
142 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); in fw_cfg_boot_set()
[all …]
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| /openbmc/linux/arch/sh/boards/ |
| H A D | board-urquell.c | 32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
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| /openbmc/qemu/hw/arm/ |
| H A D | exynos4_boards.c | 39 #define SMDK_LAN9118_BASE_ADDR 0x05000000
54 [EXYNOS4_BOARD_NURI] = 0xD33,
55 [EXYNOS4_BOARD_SMDKC210] = 0xB16,
85 sysbus_mmio_map(s, 0, base); in lan9215_init()
86 sysbus_connect_irq(s, 0, irq); in lan9215_init()
122 EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100; in exynos4_boards_init_common()
139 arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo); in nuri_init()
149 arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo); in smdkc210_init()
|
| /openbmc/linux/drivers/pinctrl/visconti/ |
| H A D | pinctrl-tmpv7700.c | 15 #define tmpv7700_MAGIC_NUM 0x4932f70e
18 #define REG_KEY_CTRL 0x0000
19 #define REG_KEY_CMD 0x0004
20 #define REG_PINMUX1 0x3000
21 #define REG_PINMUX2 0x3004
22 #define REG_PINMUX3 0x3008
23 #define REG_PINMUX4 0x300c
24 #define REG_PINMUX5 0x3010
25 #define REG_IOSET 0x3014
26 #define REG_IO_VSEL 0x3018
[all …]
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| /openbmc/u-boot/board/espt/ |
| H A D | lowlevel_init.S | 168 PACR_A: .long 0xFFEF0000
169 PBCR_A: .long 0xFFEF0002
170 PCCR_A: .long 0xFFEF0004
171 PDCR_A: .long 0xFFEF0006
172 PECR_A: .long 0xFFEF0008
173 PFCR_A: .long 0xFFEF000A
174 PGCR_A: .long 0xFFEF000C
175 PHCR_A: .long 0xFFEF000E
176 PICR_A: .long 0xFFEF0010
177 PJCR_A: .long 0xFFEF0012
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ti/ |
| H A D | k3-udma.yaml | 56 for source thread IDs (rx): 0 - 0x7fff
57 for destination thread IDs (tx): 0x8000 - 0xffff
153 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
159 reg = <0x0 0x31150000 0x0 0x100>,
160 <0x0 0x34000000 0x0 0x100000>,
161 <0x0 0x35000000 0x0 0x100000>;
172 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
173 <0x2>; /* TX_CHAN */
174 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
175 <0x5>; /* RX_CHAN */
[all …]
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| /openbmc/u-boot/include/ |
| H A D | sym53c8xx.h | 14 #define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
16 #define SCNTL1 0x01 /* no reset */
17 #define ISCON 0x10 /* connected to scsi */
18 #define CRST 0x08 /* force reset */
19 #define IARB 0x02 /* immediate arbitration */
21 #define SCNTL2 0x02 /* no disconnect expected */
22 #define SDU 0x80 /* cmd: disconnect will raise error */
23 #define CHM 0x40 /* sta: chained mode */
24 #define WSS 0x08 /* sta: wide scsi send [W]*/
25 #define WSR 0x01 /* sta: wide scsi received [W]*/
[all …]
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| /openbmc/linux/arch/arm/vdso/ |
| H A D | vdsomunge.c | 49 ((((x) & 0x00ff) << 8) | \
50 (((x) & 0xff00) >> 8))
53 ((((x) & 0x000000ff) << 24) | \
54 (((x) & 0x0000ff00) << 8) | \
55 (((x) & 0x00ff0000) >> 8) | \
56 (((x) & 0xff000000) >> 24))
68 #define EF_ARM_EABI_VER5 0x05000000
72 #define EF_ARM_ABI_FLOAT_SOFT 0x200
76 #define EF_ARM_ABI_FLOAT_HARD 0x400
130 argv0 = argv[0]; in main()
[all …]
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| /openbmc/linux/drivers/edac/ |
| H A D | fsl_ddr_edac.c | 62 return sprintf(data, "0x%08x", in fsl_mc_inject_data_hi_show()
72 return sprintf(data, "0x%08x", in fsl_mc_inject_data_lo_show()
82 return sprintf(data, "0x%08x", in fsl_mc_inject_ctrl_show()
96 rc = kstrtoul(data, 0, &val); in fsl_mc_inject_data_hi_store()
103 return 0; in fsl_mc_inject_data_hi_store()
116 rc = kstrtoul(data, 0, &val); in fsl_mc_inject_data_lo_store()
123 return 0; in fsl_mc_inject_data_lo_store()
136 rc = kstrtoul(data, 0, &val); in fsl_mc_inject_ctrl_store()
143 return 0; in fsl_mc_inject_ctrl_store()
175 /* [0:31] [32:63] */
[all …]
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | pxa3xx-gcu.c | 40 #define REG_GCCR 0x00
46 #define REG_GCISCR 0x04
47 #define REG_GCIECR 0x08
48 #define REG_GCRBBR 0x20
49 #define REG_GCRBLR 0x24
50 #define REG_GCRBHR 0x28
51 #define REG_GCRBTR 0x2C
52 #define REG_GCRBEXHR 0x30
54 #define IE_EOB (1 << 0)
56 #define IE_ALL 0xff
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/qcom/ |
| H A D | msm8992-lg-bullhead.dtsi | 26 qcom,msm-id = <251 0>, <252 0>;
27 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
47 reg = <0x0 0x1ff00000 0x0 0x40000>;
48 console-size = <0x10000>;
49 record-size = <0x10000>;
50 ftrace-size = <0x10000>;
51 pmsg-size = <0x20000>;
55 reg = <0 0x03400000 0 0xc00000>;
60 reg = <0x0 0x05000000 0x0 0x1a00000>;
71 pm8994_regulators: regulators-0 {
|