Lines Matching +full:0 +full:x05000000

67 #define CACHECRBA       0x80000823      /* Cache configuration register address */
68 #define L2CACHE_MASK	0x03	/* Mask for 2 L2 Cache bits */
69 #define L2CACHE_512KB	0x00	/* 512KB */
70 #define L2CACHE_256KB	0x01	/* 256KB */
71 #define L2CACHE_1MB	0x02	/* 1MB */
72 #define L2CACHE_NONE	0x03	/* NONE */
73 #define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
88 #define	IDC_ENABLE	0x02000000	/* Cache enable */
89 #define IDC_DISABLE	0x04000000	/* Cache disable */
90 #define IDC_LDLCK	0x06000000	/* Load and lock */
91 #define IDC_UNLINE	0x08000000	/* Unlock line */
92 #define IDC_UNALL	0x0a000000	/* Unlock all */
93 #define IDC_INVALL	0x0c000000	/* Invalidate all */
95 #define DC_FLINE	0x0e000000	/* Flush data cache line */
96 #define DC_SFWT		0x01000000	/* Set forced writethrough mode */
97 #define DC_CFWT		0x03000000	/* Clear forced writethrough mode */
98 #define DC_SLES		0x05000000	/* Set little endian swap mode */
99 #define DC_CLES		0x07000000	/* Clear little endian swap mode */
103 #define IDC_ENABLED	0x80000000	/* Cache is enabled */
104 #define IDC_CERR1	0x00200000	/* Cache error 1 */
105 #define IDC_CERR2	0x00100000	/* Cache error 2 */
106 #define IDC_CERR3	0x00080000	/* Cache error 3 */
108 #define DC_DFWT		0x40000000	/* Data cache is forced write through */
109 #define DC_LES		0x20000000	/* Caches are little endian mode */