1aaf9128aSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
25ac072e1SKuninori Morimoto /*
35ac072e1SKuninori Morimoto * Renesas Technology Corp. SH7786 Urquell Support.
45ac072e1SKuninori Morimoto *
55ac072e1SKuninori Morimoto * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
6dea3cf1cSPaul Mundt * Copyright (C) 2009, 2010 Paul Mundt
76e979381SKuninori Morimoto *
86e979381SKuninori Morimoto * Based on board-sh7785lcr.c
95ac072e1SKuninori Morimoto * Copyright (C) 2008 Yoshihiro Shimoda
105ac072e1SKuninori Morimoto */
115ac072e1SKuninori Morimoto #include <linux/init.h>
125ac072e1SKuninori Morimoto #include <linux/platform_device.h>
135ac072e1SKuninori Morimoto #include <linux/fb.h>
14929ef1a1SKuninori Morimoto #include <linux/smc91x.h>
155ac072e1SKuninori Morimoto #include <linux/mtd/physmap.h>
165ac072e1SKuninori Morimoto #include <linux/delay.h>
175ac072e1SKuninori Morimoto #include <linux/gpio.h>
185ac072e1SKuninori Morimoto #include <linux/irq.h>
19dea3cf1cSPaul Mundt #include <linux/clk.h>
204059e43aSPaul Mundt #include <linux/sh_intc.h>
215ac072e1SKuninori Morimoto #include <mach/urquell.h>
225ac072e1SKuninori Morimoto #include <cpu/sh7786.h>
235ac072e1SKuninori Morimoto #include <asm/heartbeat.h>
2487dfb311SMasahiro Yamada #include <linux/sizes.h>
253366e358SPaul Mundt #include <asm/smp-ops.h>
265ac072e1SKuninori Morimoto
271bc57185SKuninori Morimoto /*
281bc57185SKuninori Morimoto * bit 1234 5678
296e979381SKuninori Morimoto *----------------------------
301bc57185SKuninori Morimoto * SW1 0101 0010 -> Pck 33MHz version
311bc57185SKuninori Morimoto * (1101 0010) Pck 66MHz version
321bc57185SKuninori Morimoto * SW2 0x1x xxxx -> little endian
336e979381SKuninori Morimoto * 29bit mode
341bc57185SKuninori Morimoto * SW47 0001 1000 -> CS0 : on-board flash
356e979381SKuninori Morimoto * CS1 : SRAM, registers, LAN, PCMCIA
361bc57185SKuninori Morimoto * 38400 bps for SCIF1
376e979381SKuninori Morimoto *
386e979381SKuninori Morimoto * Address
391bc57185SKuninori Morimoto * 0x00000000 - 0x04000000 (CS0) Nor Flash
401bc57185SKuninori Morimoto * 0x04000000 - 0x04200000 (CS1) SRAM
411bc57185SKuninori Morimoto * 0x05000000 - 0x05800000 (CS1) on board register
421bc57185SKuninori Morimoto * 0x05800000 - 0x06000000 (CS1) LAN91C111
431bc57185SKuninori Morimoto * 0x06000000 - 0x06400000 (CS1) PCMCIA
441bc57185SKuninori Morimoto * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
451bc57185SKuninori Morimoto * 0x10000000 - 0x14000000 (CS4) PCIe
461bc57185SKuninori Morimoto * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
471bc57185SKuninori Morimoto * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
481bc57185SKuninori Morimoto * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash
491bc57185SKuninori Morimoto * 0x1C000000 - (CS7) SH7786 Control register
506e979381SKuninori Morimoto */
516e979381SKuninori Morimoto
526e979381SKuninori Morimoto /* HeartBeat */
53a09d2831SPaul Mundt static struct resource heartbeat_resource = {
545ac072e1SKuninori Morimoto .start = BOARDREG(SLEDR),
555ac072e1SKuninori Morimoto .end = BOARDREG(SLEDR),
56a09d2831SPaul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
575ac072e1SKuninori Morimoto };
585ac072e1SKuninori Morimoto
595ac072e1SKuninori Morimoto static struct platform_device heartbeat_device = {
605ac072e1SKuninori Morimoto .name = "heartbeat",
615ac072e1SKuninori Morimoto .id = -1,
6214965f16SPaul Mundt .num_resources = 1,
63a09d2831SPaul Mundt .resource = &heartbeat_resource,
645ac072e1SKuninori Morimoto };
655ac072e1SKuninori Morimoto
666e979381SKuninori Morimoto /* LAN91C111 */
67929ef1a1SKuninori Morimoto static struct smc91x_platdata smc91x_info = {
68929ef1a1SKuninori Morimoto .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
69929ef1a1SKuninori Morimoto };
70929ef1a1SKuninori Morimoto
71929ef1a1SKuninori Morimoto static struct resource smc91x_eth_resources[] = {
72929ef1a1SKuninori Morimoto [0] = {
73929ef1a1SKuninori Morimoto .name = "SMC91C111" ,
74929ef1a1SKuninori Morimoto .start = 0x05800300,
75929ef1a1SKuninori Morimoto .end = 0x0580030f,
76929ef1a1SKuninori Morimoto .flags = IORESOURCE_MEM,
77929ef1a1SKuninori Morimoto },
78929ef1a1SKuninori Morimoto [1] = {
794059e43aSPaul Mundt .start = evt2irq(0x360),
80929ef1a1SKuninori Morimoto .flags = IORESOURCE_IRQ,
81929ef1a1SKuninori Morimoto },
82929ef1a1SKuninori Morimoto };
83929ef1a1SKuninori Morimoto
84929ef1a1SKuninori Morimoto static struct platform_device smc91x_eth_device = {
85929ef1a1SKuninori Morimoto .name = "smc91x",
86929ef1a1SKuninori Morimoto .num_resources = ARRAY_SIZE(smc91x_eth_resources),
87929ef1a1SKuninori Morimoto .resource = smc91x_eth_resources,
88929ef1a1SKuninori Morimoto .dev = {
89929ef1a1SKuninori Morimoto .platform_data = &smc91x_info,
90929ef1a1SKuninori Morimoto },
91929ef1a1SKuninori Morimoto };
92929ef1a1SKuninori Morimoto
936e979381SKuninori Morimoto /* Nor Flash */
945ac072e1SKuninori Morimoto static struct mtd_partition nor_flash_partitions[] = {
955ac072e1SKuninori Morimoto {
965ac072e1SKuninori Morimoto .name = "loader",
975ac072e1SKuninori Morimoto .offset = 0x00000000,
985ac072e1SKuninori Morimoto .size = SZ_512K,
995ac072e1SKuninori Morimoto .mask_flags = MTD_WRITEABLE, /* Read-only */
1005ac072e1SKuninori Morimoto },
1015ac072e1SKuninori Morimoto {
1025ac072e1SKuninori Morimoto .name = "bootenv",
1035ac072e1SKuninori Morimoto .offset = MTDPART_OFS_APPEND,
1045ac072e1SKuninori Morimoto .size = SZ_512K,
1055ac072e1SKuninori Morimoto .mask_flags = MTD_WRITEABLE, /* Read-only */
1065ac072e1SKuninori Morimoto },
1075ac072e1SKuninori Morimoto {
1085ac072e1SKuninori Morimoto .name = "kernel",
1095ac072e1SKuninori Morimoto .offset = MTDPART_OFS_APPEND,
1105ac072e1SKuninori Morimoto .size = SZ_4M,
1115ac072e1SKuninori Morimoto },
1125ac072e1SKuninori Morimoto {
1135ac072e1SKuninori Morimoto .name = "data",
1145ac072e1SKuninori Morimoto .offset = MTDPART_OFS_APPEND,
1155ac072e1SKuninori Morimoto .size = MTDPART_SIZ_FULL,
1165ac072e1SKuninori Morimoto },
1175ac072e1SKuninori Morimoto };
1185ac072e1SKuninori Morimoto
1195ac072e1SKuninori Morimoto static struct physmap_flash_data nor_flash_data = {
1205ac072e1SKuninori Morimoto .width = 2,
1215ac072e1SKuninori Morimoto .parts = nor_flash_partitions,
1225ac072e1SKuninori Morimoto .nr_parts = ARRAY_SIZE(nor_flash_partitions),
1235ac072e1SKuninori Morimoto };
1245ac072e1SKuninori Morimoto
1255ac072e1SKuninori Morimoto static struct resource nor_flash_resources[] = {
1265ac072e1SKuninori Morimoto [0] = {
1275ac072e1SKuninori Morimoto .start = NOR_FLASH_ADDR,
1285ac072e1SKuninori Morimoto .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
1295ac072e1SKuninori Morimoto .flags = IORESOURCE_MEM,
1305ac072e1SKuninori Morimoto }
1315ac072e1SKuninori Morimoto };
1325ac072e1SKuninori Morimoto
1335ac072e1SKuninori Morimoto static struct platform_device nor_flash_device = {
1345ac072e1SKuninori Morimoto .name = "physmap-flash",
1355ac072e1SKuninori Morimoto .dev = {
1365ac072e1SKuninori Morimoto .platform_data = &nor_flash_data,
1375ac072e1SKuninori Morimoto },
1385ac072e1SKuninori Morimoto .num_resources = ARRAY_SIZE(nor_flash_resources),
1395ac072e1SKuninori Morimoto .resource = nor_flash_resources,
1405ac072e1SKuninori Morimoto };
1415ac072e1SKuninori Morimoto
1425ac072e1SKuninori Morimoto static struct platform_device *urquell_devices[] __initdata = {
1435ac072e1SKuninori Morimoto &heartbeat_device,
144929ef1a1SKuninori Morimoto &smc91x_eth_device,
1455ac072e1SKuninori Morimoto &nor_flash_device,
1465ac072e1SKuninori Morimoto };
1475ac072e1SKuninori Morimoto
urquell_devices_setup(void)1485ac072e1SKuninori Morimoto static int __init urquell_devices_setup(void)
1495ac072e1SKuninori Morimoto {
1505ac072e1SKuninori Morimoto /* USB */
1515ac072e1SKuninori Morimoto gpio_request(GPIO_FN_USB_OVC0, NULL);
1525ac072e1SKuninori Morimoto gpio_request(GPIO_FN_USB_PENC0, NULL);
1535ac072e1SKuninori Morimoto
15471c1d19eSKuninori Morimoto /* enable LAN */
15571c1d19eSKuninori Morimoto __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001,
15671c1d19eSKuninori Morimoto UBOARDREG(IRL2MSKR));
15771c1d19eSKuninori Morimoto
1585ac072e1SKuninori Morimoto return platform_add_devices(urquell_devices,
1595ac072e1SKuninori Morimoto ARRAY_SIZE(urquell_devices));
1605ac072e1SKuninori Morimoto }
1615ac072e1SKuninori Morimoto device_initcall(urquell_devices_setup);
1625ac072e1SKuninori Morimoto
urquell_power_off(void)1635ac072e1SKuninori Morimoto static void urquell_power_off(void)
1645ac072e1SKuninori Morimoto {
1655ac072e1SKuninori Morimoto __raw_writew(0xa5a5, UBOARDREG(SRSTR));
1665ac072e1SKuninori Morimoto }
1675ac072e1SKuninori Morimoto
urquell_init_irq(void)168929ef1a1SKuninori Morimoto static void __init urquell_init_irq(void)
169929ef1a1SKuninori Morimoto {
170929ef1a1SKuninori Morimoto plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
171929ef1a1SKuninori Morimoto }
172929ef1a1SKuninori Morimoto
urquell_mode_pins(void)1735d0e945aSPaul Mundt static int urquell_mode_pins(void)
1745d0e945aSPaul Mundt {
1755d0e945aSPaul Mundt return __raw_readw(UBOARDREG(MDSWMR));
1765d0e945aSPaul Mundt }
1775d0e945aSPaul Mundt
urquell_clk_init(void)178dea3cf1cSPaul Mundt static int urquell_clk_init(void)
179dea3cf1cSPaul Mundt {
180dea3cf1cSPaul Mundt struct clk *clk;
181dea3cf1cSPaul Mundt int ret;
182dea3cf1cSPaul Mundt
183dea3cf1cSPaul Mundt /*
184dea3cf1cSPaul Mundt * Only handle the EXTAL case, anyone interfacing a crystal
185dea3cf1cSPaul Mundt * resonator will need to provide their own input clock.
186dea3cf1cSPaul Mundt */
187dea3cf1cSPaul Mundt if (test_mode_pin(MODE_PIN9))
188dea3cf1cSPaul Mundt return -EINVAL;
189dea3cf1cSPaul Mundt
190dea3cf1cSPaul Mundt clk = clk_get(NULL, "extal");
1917912825dSPaul Mundt if (IS_ERR(clk))
192dea3cf1cSPaul Mundt return PTR_ERR(clk);
193dea3cf1cSPaul Mundt ret = clk_set_rate(clk, 33333333);
194dea3cf1cSPaul Mundt clk_put(clk);
195dea3cf1cSPaul Mundt
196dea3cf1cSPaul Mundt return ret;
197dea3cf1cSPaul Mundt }
198dea3cf1cSPaul Mundt
1995ac072e1SKuninori Morimoto /* Initialize the board */
urquell_setup(char ** cmdline_p)2005ac072e1SKuninori Morimoto static void __init urquell_setup(char **cmdline_p)
2015ac072e1SKuninori Morimoto {
2025ac072e1SKuninori Morimoto printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n");
2035ac072e1SKuninori Morimoto
2045ac072e1SKuninori Morimoto pm_power_off = urquell_power_off;
2053366e358SPaul Mundt
2063366e358SPaul Mundt register_smp_ops(&shx3_smp_ops);
2075ac072e1SKuninori Morimoto }
2085ac072e1SKuninori Morimoto
2095ac072e1SKuninori Morimoto /*
2105ac072e1SKuninori Morimoto * The Machine Vector
2115ac072e1SKuninori Morimoto */
2125ac072e1SKuninori Morimoto static struct sh_machine_vector mv_urquell __initmv = {
2135ac072e1SKuninori Morimoto .mv_name = "Urquell",
2145ac072e1SKuninori Morimoto .mv_setup = urquell_setup,
215929ef1a1SKuninori Morimoto .mv_init_irq = urquell_init_irq,
2165d0e945aSPaul Mundt .mv_mode_pins = urquell_mode_pins,
217dea3cf1cSPaul Mundt .mv_clk_init = urquell_clk_init,
2185ac072e1SKuninori Morimoto };
219