62 	return sprintf(data, "0x%08x",  in fsl_mc_inject_data_hi_show()
72 	return sprintf(data, "0x%08x",  in fsl_mc_inject_data_lo_show()
82 	return sprintf(data, "0x%08x",  in fsl_mc_inject_ctrl_show()
96 		rc = kstrtoul(data, 0, &val);  in fsl_mc_inject_data_hi_store()
103 	return 0;  in fsl_mc_inject_data_hi_store()
116 		rc = kstrtoul(data, 0, &val);  in fsl_mc_inject_data_lo_store()
123 	return 0;  in fsl_mc_inject_data_lo_store()
136 		rc = kstrtoul(data, 0, &val);  in fsl_mc_inject_ctrl_store()
143 	return 0;  in fsl_mc_inject_ctrl_store()
175 	/* [0:31]    [32:63] */
176 	0xf00fe11e, 0xc33c0ff7,	/* Syndrome bit 7 */
177 	0x00ff00ff, 0x00fff0ff,
178 	0x0f0f0f0f, 0x0f0fff00,
179 	0x11113333, 0x7777000f,
180 	0x22224444, 0x8888222f,
181 	0x44448888, 0xffff4441,
182 	0x8888ffff, 0x11118882,
183 	0xffff1111, 0x22221114,	/* Syndrome bit 0 */
194 	u8 ecc = 0;  in calculate_ecc()
198 	for (i = 0; i < 8; i++) {  in calculate_ecc()
201 		bit_cnt = 0;  in calculate_ecc()
203 		for (j = 0; j < 32; j++) {  in calculate_ecc()
223 	u8 syndrome = 0;  in syndrome_from_bit()
256 	for (i = 0; i < 64; i++) {  in sbe_ecc_decode()
264 	for (i = 0; i < 8; i++) {  in sbe_ecc_decode()
265 		if ((syndrome >> i) & 0x1) {  in sbe_ecc_decode()
308 		syndrome &= 0xff;  in fsl_mc_check()
310 		syndrome &= 0xffff;  in fsl_mc_check()
317 	for (row_index = 0; row_index < mci->nr_csrows; row_index++) {  in fsl_mc_check()
337 		if (bad_data_bit >= 0) {  in fsl_mc_check()
342 		if (bad_ecc_bit >= 0) {  in fsl_mc_check()
365 				     row_index, 0, -1,  in fsl_mc_check()
371 				     row_index, 0, -1,  in fsl_mc_check()
408 		case 0x02000000:  in fsl_ddr_init_csrows()
411 		case 0x03000000:  in fsl_ddr_init_csrows()
414 		case 0x07000000:  in fsl_ddr_init_csrows()
417 		case 0x05000000:  in fsl_ddr_init_csrows()
426 		case 0x02000000:  in fsl_ddr_init_csrows()
429 		case 0x03000000:  in fsl_ddr_init_csrows()
432 		case 0x07000000:  in fsl_ddr_init_csrows()
435 		case 0x05000000:  in fsl_ddr_init_csrows()
444 	for (index = 0; index < mci->nr_csrows; index++) {  in fsl_ddr_init_csrows()
449 		dimm = csrow->channels[0]->dimm;  in fsl_ddr_init_csrows()
454 		start = (cs_bnds & 0xffff0000) >> 16;  in fsl_ddr_init_csrows()
455 		end   = (cs_bnds & 0x0000ffff);  in fsl_ddr_init_csrows()
489 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;  in fsl_mc_err_probe()
490 	layers[0].size = 4;  in fsl_mc_err_probe()
491 	layers[0].is_virt_csrow = true;  in fsl_mc_err_probe()
516 	res = of_address_to_resource(op->dev.of_node, 0, &r);  in fsl_mc_err_probe()
566 	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);  in fsl_mc_err_probe()
569 	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);  in fsl_mc_err_probe()
583 					    FSL_MC_ERR_SBE) & 0xff0000;  in fsl_mc_err_probe()
586 		ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);  in fsl_mc_err_probe()
589 		pdata->irq = platform_get_irq(op, 0);  in fsl_mc_err_probe()
594 		if (res < 0) {  in fsl_mc_err_probe()
609 	return 0;  in fsl_mc_err_probe()
624 	edac_dbg(0, "\n");  in fsl_mc_err_remove()
627 		ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);  in fsl_mc_err_remove()
636 	return 0;  in fsl_mc_err_remove()