Lines Matching +full:0 +full:x05000000

15 #define	CCM_GPR0_OFFSET			0x0
16 #define	CCM_OBSERVE0_OFFSET		0x0400
17 #define	CCM_SCTRL0_OFFSET		0x0800
18 #define	CCM_CCGR0_OFFSET		0x4000
19 #define	CCM_ROOT0_TARGET_OFFSET		0x8000
58 	struct mxc_ccm_ccgr ccgr_array[191];	/* offset 0x4000 */
60 	struct mxc_ccm_root_slice root[121];	/* offset 0x8000 */
65 	uint32_t ctrl_24m;			/* offset 0x0000 */
69 	uint32_t rcosc_config0;			/* offset 0x0010 */
73 	uint32_t rcosc_config1;			/* offset 0x0020 */
77 	uint32_t rcosc_config2;			/* offset 0x0030 */
82 	uint32_t osc_32k;			/* offset 0x0050 */
86 	uint32_t pll_arm;			/* offset 0x0060 */
90 	uint32_t pll_ddr;			/* offset 0x0070 */
94 	uint32_t pll_ddr_ss;			/* offset 0x0080 */
96 	uint32_t pll_ddr_num;			/* offset 0x0090 */
98 	uint32_t pll_ddr_denom;			/* offset 0x00a0 */
100 	uint32_t pll_480;			/* offset 0x00b0 */
104 	uint32_t pfd_480a;			/* offset 0x00c0 */
108 	uint32_t pfd_480b;			/* offset 0x00d0 */
112 	uint32_t pll_enet;			/* offset 0x00e0 */
116 	uint32_t pll_audio;			/* offset 0x00f0 */
120 	uint32_t pll_audio_ss;			/* offset 0x0100 */
122 	uint32_t pll_audio_num;			/* offset 0x0110 */
124 	uint32_t pll_audio_denom;		/* offset 0x0120 */
126 	uint32_t pll_video;			/* offset 0x0130 */
130 	uint32_t pll_video_ss;			/* offset 0x0140 */
132 	uint32_t pll_video_num;			/* offset 0x0150 */
134 	uint32_t pll_video_denom;		/* offset 0x0160 */
136 	uint32_t clk_misc0;			/* offset 0x0170 */
140 	uint32_t clk_rsvd;			/* offset 0x0180 */
142 	uint32_t reg_1p0a;			/* offset 0x0200 */
146 	uint32_t reg_1p0d;			/* offsest 0x0210 */
150 	uint32_t reg_hsic_1p2;			/* offset 0x0220 */
154 	uint32_t reg_lpsr_1p0;			/* offset 0x0230 */
158 	uint32_t reg_3p0;			/* offset 0x0240 */
162 	uint32_t reg_snvs;			/* offset 0x0250 */
166 	uint32_t analog_debug_misc0;		/* offset 0x0260 */
170 	uint32_t ref;				/* offset 0x0270 */
175 	uint32_t tempsense0;			/* offset 0x0300 */
179 	uint32_t tempsense1;			/* offset 0x0310 */
183 	uint32_t tempsense_trim;		/* offset 0x0320 */
187 	uint32_t lowpwr_ctrl;			/* offset 0x0330 */
191 	uint32_t snvs_tamper_offset_ctrl;	/* offset 0x0340 */
195 	uint32_t snvs_tamper_pull_ctrl;		/* offset 0x0350 */
199 	uint32_t snvs_test;			/* offset 0x0360 */
203 	uint32_t snvs_tamper_trim_ctrl;		/* offset 0x0370 */
207 	uint32_t snvs_misc_ctrl;		/* offset 0x0380 */
212 	uint32_t misc;				/* offset 0x0400 */
214 	uint32_t adc0;				/* offset 0x0500 */
216 	uint32_t adc1;				/* offset 0x0510 */
218 	uint32_t digprog;			/* offset 0x0800 */
222 #define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK	(0x01 << 17)
224 #define ANADIG_PLL_LOCK					0x80000000
226 #define ANADIG_PLL_ARM_PWDN_MASK			(0x01 << 12)
227 #define ANADIG_PLL_480_PWDN_MASK			(0x01 << 12)
228 #define ANADIG_PLL_DDR_PWDN_MASK			(0x01 << 20)
229 #define ANADIG_PLL_ENET_PWDN_MASK			(0x01 << 5)
230 #define ANADIG_PLL_VIDEO_PWDN_MASK			(0x01 << 12)
233 #define ANATOP_PFD480B_PFD4_FRAC_MASK			0x0000003f
234 #define ANATOP_PFD480B_PFD4_FRAC_320M_VAL		0x0000001B
235 #define ANATOP_PFD480B_PFD4_FRAC_392M_VAL		0x00000016
236 #define ANATOP_PFD480B_PFD4_FRAC_432M_VAL		0x00000014
239 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK		0x7F
240 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT		0
241 #define CCM_ANALOG_PLL_ARM_HALF_LF_MASK			0x80
243 #define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK		0x100
245 #define CCM_ANALOG_PLL_ARM_HALF_CP_MASK			0x200
247 #define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK		0x400
249 #define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK		0x800
251 #define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK		0x1000
253 #define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK		0x2000
255 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK		0xC000
257 #define CCM_ANALOG_PLL_ARM_BYPASS_MASK			0x10000
259 #define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK		0x20000
261 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK		0x40000
263 #define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK			0x80000
265 #define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK	0x100000
267 #define CCM_ANALOG_PLL_ARM_RSVD0_MASK			0x7FE00000
269 #define CCM_ANALOG_PLL_ARM_LOCK_MASK			0x80000000
273 #define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK		0x7F
274 #define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT		0
275 #define CCM_ANALOG_PLL_DDR_HALF_LF_MASK			0x80
277 #define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK		0x100
279 #define CCM_ANALOG_PLL_DDR_HALF_CP_MASK			0x200
281 #define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK		0x400
283 #define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK		0x800
285 #define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK		0x1000
287 #define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK		0x2000
289 #define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK		0xC000
291 #define CCM_ANALOG_PLL_DDR_BYPASS_MASK			0x10000
293 #define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK		0x20000
295 #define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK		0x40000
297 #define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK	0x80000
299 #define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK		0x100000
301 #define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK		0x600000
303 #define CCM_ANALOG_PLL_DDR_RSVD1_MASK			0x7F800000
305 #define CCM_ANALOG_PLL_DDR_LOCK_MASK			0x80000000
309 #define CCM_ANALOG_PLL_480_DIV_SELECT_MASK		0x1
310 #define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT		0
311 #define CCM_ANALOG_PLL_480_RSVD0_MASK			0xE
313 #define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK	0x10
315 #define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK	0x20
317 #define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK	0x40
319 #define CCM_ANALOG_PLL_480_HALF_LF_MASK			0x80
321 #define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK		0x100
323 #define CCM_ANALOG_PLL_480_HALF_CP_MASK			0x200
325 #define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK		0x400
327 #define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK		0x800
329 #define CCM_ANALOG_PLL_480_POWERDOWN_MASK		0x1000
331 #define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK		0x2000
333 #define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK		0xC000
335 #define CCM_ANALOG_PLL_480_BYPASS_MASK			0x10000
337 #define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK	0x20000
339 #define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK		0x40000
341 #define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK		0x80000
343 #define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK		0x100000
345 #define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK		0x200000
347 #define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK		0x400000
349 #define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK		0x800000
351 #define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK		0x1000000
353 #define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK		0x2000000
355 #define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK	0x4000000
357 #define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK	0x8000000
359 #define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK	0x10000000
361 #define CCM_ANALOG_PLL_480_RSVD1_MASK			0x60000000
363 #define CCM_ANALOG_PLL_480_LOCK_MASK			0x80000000
367 #define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK		0x3F
368 #define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT		0
369 #define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK		0x40
371 #define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK	0x80
373 #define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK		0x3F00
375 #define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK		0x4000
377 #define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK	0x8000
379 #define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK		0x3F0000
381 #define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK		0x400000
383 #define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK	0x800000
385 #define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK		0x3F000000
387 #define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK		0x40000000
389 #define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK	0x80000000
392 #define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK		0x3F
393 #define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT		0
394 #define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK		0x40
396 #define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK	0x80
398 #define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK		0x3F00
400 #define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK		0x4000
402 #define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK	0x8000
404 #define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK		0x3F0000
406 #define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK		0x400000
408 #define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK	0x800000
410 #define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK		0x3F000000
412 #define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK		0x40000000
414 #define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK	0x80000000
418 #define CCM_ANALOG_PLL_ENET_HALF_LF_MASK		0x1
419 #define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT		0
420 #define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK		0x2
422 #define CCM_ANALOG_PLL_ENET_HALF_CP_MASK		0x4
424 #define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK		0x8
426 #define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK		0x10
428 #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK		0x20
430 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK	0x40
432 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK	0x80
434 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK	0x100
436 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK	0x200
438 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK	0x400
440 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK	0x800
442 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK	0x1000
444 #define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK	0x2000
446 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK		0xC000
448 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK			0x10000
450 #define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK		0x20000
452 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK		0x40000
454 #define CCM_ANALOG_PLL_ENET_RSVD1_MASK			0x7FF80000
456 #define CCM_ANALOG_PLL_ENET_LOCK_MASK			0x80000000
460 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK     0x7Fu
461 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT    0
463 #define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK        0x80u
465 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK      0x100u
467 #define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK        0x200u
469 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK      0x400u
471 #define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK  0x800u
473 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK      0x1000u
475 #define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK     0x2000u
477 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u
480 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK         0x10000u
482 #define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK  0x20000u
484 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK  0x40000u
486 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u
489 #define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK          0x200000u
491 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK   0xC00000u
494 #define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
496 #define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK          0x7E000000u
499 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK           0x80000000u
502 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu
503 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0
505 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK    0x80u
507 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK  0x100u
509 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK    0x200u
511 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK  0x400u
513 #define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u
515 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK  0x1000u
517 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u
519 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u
522 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK     0x10000u
524 #define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u
526 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u
528 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u
531 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK      0x200000u
533 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u
536 #define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
538 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK      0x7E000000u
541 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK       0x80000000u
544 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu
545 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0
547 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK    0x80u
549 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK  0x100u
551 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK    0x200u
553 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK  0x400u
555 #define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u
557 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK  0x1000u
559 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u
561 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
564 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK     0x10000u
566 #define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u
568 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u
570 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u
573 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK      0x200000u
575 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u
578 #define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
580 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK      0x7E000000u
583 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK       0x80000000u
586 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu
587 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0
589 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK    0x80u
591 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK  0x100u
593 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK    0x200u
595 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK  0x400u
597 #define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u
599 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK  0x1000u
601 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u
603 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
606 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK     0x10000u
608 #define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u
610 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u
612 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u
615 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK      0x200000u
617 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u
620 #define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
622 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK      0x7E000000u
625 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK       0x80000000u
628 #define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK        0x7FFFu
629 #define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT       0
631 #define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK      0x8000u
633 #define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK        0xFFFF0000u
637 #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK          0x3FFFFFFFu
638 #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT         0
640 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK      0xC0000000u
644 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK        0x3FFFFFFFu
645 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT       0
647 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK    0xC0000000u
651 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK     0x7Fu
652 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT    0
654 #define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK        0x80u
656 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK      0x100u
658 #define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK        0x200u
660 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK      0x400u
662 #define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK  0x800u
664 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK      0x1000u
666 #define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK     0x2000u
668 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u
671 #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK         0x10000u
673 #define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK  0x20000u
675 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK  0x40000u
677 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u
680 #define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK          0x200000u
682 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK   0xC00000u
685 #define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
687 #define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK          0x7E000000u
690 #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK           0x80000000u
693 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu
694 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0
696 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK    0x80u
698 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK  0x100u
700 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK    0x200u
702 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK  0x400u
704 #define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u
706 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK  0x1000u
708 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u
710 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u
713 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK     0x10000u
715 #define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u
717 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u
719 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u
722 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK      0x200000u
724 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u
727 #define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
729 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK      0x7E000000u
732 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK       0x80000000u
735 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu
736 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0
738 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK    0x80u
740 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK  0x100u
742 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK    0x200u
744 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK  0x400u
746 #define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u
748 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK  0x1000u
750 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u
752 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
755 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK     0x10000u
757 #define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u
759 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u
761 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u
764 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK      0x200000u
766 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u
769 #define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
771 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK      0x7E000000u
774 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK       0x80000000u
777 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu
778 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0
780 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK    0x80u
782 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK  0x100u
784 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK    0x200u
786 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK  0x400u
788 #define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u
790 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK  0x1000u
792 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u
794 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
797 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK     0x10000u
799 #define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u
801 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u
803 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u
806 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK      0x200000u
808 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u
811 #define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
813 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK      0x7E000000u
816 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK       0x80000000u
819 #define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK        0x7FFFu
820 #define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT       0
822 #define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK      0x8000u
824 #define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK        0xFFFF0000u
828 #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK          0x3FFFFFFFu
829 #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT         0
831 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK      0xC0000000u
835 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK        0x3FFFFFFFu
836 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT       0
838 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK    0xC0000000u
842 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK  0x1Fu
843 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0
845 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK  0x20u
847 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK  0x40u
849 #define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK   0x80u
851 #define CCM_ANALOG_CLK_MISC0_RSVD0_MASK          0xFFFFFF00u
855 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu
856 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0
858 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u
860 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u
862 #define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u
864 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK      0xFFFFFF00u
868 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu
869 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0
871 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u
873 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u
875 #define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u
877 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK      0xFFFFFF00u
881 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu
882 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0
884 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u
886 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u
888 #define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u
890 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK      0xFFFFFF00u
895 #define PMU_REG_1P0A_ENABLE_LINREG_MASK          0x1u
896 #define PMU_REG_1P0A_ENABLE_LINREG_SHIFT         0
897 #define PMU_REG_1P0A_ENABLE_BO_MASK              0x2u
899 #define PMU_REG_1P0A_ENABLE_ILIMIT_MASK          0x4u
901 #define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK        0x8u
903 #define PMU_REG_1P0A_BO_OFFSET_MASK              0x70u
906 #define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK       0x80u
908 #define PMU_REG_1P0A_OUTPUT_TRG_MASK             0x1F00u
911 #define PMU_REG_1P0A_RSVD0_MASK                  0xE000u
914 #define PMU_REG_1P0A_BO_MASK                     0x10000u
916 #define PMU_REG_1P0A_OK_MASK                     0x20000u
918 #define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK     0x40000u
920 #define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK     0x80000u
922 #define PMU_REG_1P0A_REG_TEST_MASK               0xF00000u
925 #define PMU_REG_1P0A_RSVD1_MASK                  0xFF000000u
929 #define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK      0x1u
930 #define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT     0
931 #define PMU_REG_1P0A_SET_ENABLE_BO_MASK          0x2u
933 #define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK      0x4u
935 #define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK    0x8u
937 #define PMU_REG_1P0A_SET_BO_OFFSET_MASK          0x70u
940 #define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK   0x80u
942 #define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK         0x1F00u
945 #define PMU_REG_1P0A_SET_RSVD0_MASK              0xE000u
948 #define PMU_REG_1P0A_SET_BO_MASK                 0x10000u
950 #define PMU_REG_1P0A_SET_OK_MASK                 0x20000u
952 #define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
954 #define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u
956 #define PMU_REG_1P0A_SET_REG_TEST_MASK           0xF00000u
959 #define PMU_REG_1P0A_SET_RSVD1_MASK              0xFF000000u
963 #define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK      0x1u
964 #define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT     0
965 #define PMU_REG_1P0A_CLR_ENABLE_BO_MASK          0x2u
967 #define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK      0x4u
969 #define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK    0x8u
971 #define PMU_REG_1P0A_CLR_BO_OFFSET_MASK          0x70u
974 #define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK   0x80u
976 #define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK         0x1F00u
979 #define PMU_REG_1P0A_CLR_RSVD0_MASK              0xE000u
982 #define PMU_REG_1P0A_CLR_BO_MASK                 0x10000u
984 #define PMU_REG_1P0A_CLR_OK_MASK                 0x20000u
986 #define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
988 #define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
990 #define PMU_REG_1P0A_CLR_REG_TEST_MASK           0xF00000u
993 #define PMU_REG_1P0A_CLR_RSVD1_MASK              0xFF000000u
997 #define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK      0x1u
998 #define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT     0
999 #define PMU_REG_1P0A_TOG_ENABLE_BO_MASK          0x2u
1001 #define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK      0x4u
1003 #define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK    0x8u
1005 #define PMU_REG_1P0A_TOG_BO_OFFSET_MASK          0x70u
1008 #define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK   0x80u
1010 #define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK         0x1F00u
1013 #define PMU_REG_1P0A_TOG_RSVD0_MASK              0xE000u
1016 #define PMU_REG_1P0A_TOG_BO_MASK                 0x10000u
1018 #define PMU_REG_1P0A_TOG_OK_MASK                 0x20000u
1020 #define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
1022 #define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
1024 #define PMU_REG_1P0A_TOG_REG_TEST_MASK           0xF00000u
1027 #define PMU_REG_1P0A_TOG_RSVD1_MASK              0xFF000000u
1031 #define PMU_REG_1P0D_ENABLE_LINREG_MASK          0x1u
1032 #define PMU_REG_1P0D_ENABLE_LINREG_SHIFT         0
1033 #define PMU_REG_1P0D_ENABLE_BO_MASK              0x2u
1035 #define PMU_REG_1P0D_ENABLE_ILIMIT_MASK          0x4u
1037 #define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK        0x8u
1039 #define PMU_REG_1P0D_BO_OFFSET_MASK              0x70u
1042 #define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK       0x80u
1044 #define PMU_REG_1P0D_OUTPUT_TRG_MASK             0x1F00u
1047 #define PMU_REG_1P0D_RSVD0_MASK                  0xE000u
1050 #define PMU_REG_1P0D_BO_MASK                     0x10000u
1052 #define PMU_REG_1P0D_OK_MASK                     0x20000u
1054 #define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK     0x40000u
1056 #define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK     0x80000u
1058 #define PMU_REG_1P0D_REG_TEST_MASK               0xF00000u
1061 #define PMU_REG_1P0D_RSVD1_MASK                  0x7F000000u
1064 #define PMU_REG_1P0D_OVERRIDE_MASK               0x80000000u
1067 #define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK      0x1u
1068 #define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT     0
1069 #define PMU_REG_1P0D_SET_ENABLE_BO_MASK          0x2u
1071 #define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK      0x4u
1073 #define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK    0x8u
1075 #define PMU_REG_1P0D_SET_BO_OFFSET_MASK          0x70u
1078 #define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK   0x80u
1080 #define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK         0x1F00u
1083 #define PMU_REG_1P0D_SET_RSVD0_MASK              0xE000u
1086 #define PMU_REG_1P0D_SET_BO_MASK                 0x10000u
1088 #define PMU_REG_1P0D_SET_OK_MASK                 0x20000u
1090 #define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
1092 #define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u
1094 #define PMU_REG_1P0D_SET_REG_TEST_MASK           0xF00000u
1097 #define PMU_REG_1P0D_SET_RSVD1_MASK              0x7F000000u
1100 #define PMU_REG_1P0D_SET_OVERRIDE_MASK           0x80000000u
1103 #define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK      0x1u
1104 #define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT     0
1105 #define PMU_REG_1P0D_CLR_ENABLE_BO_MASK          0x2u
1107 #define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK      0x4u
1109 #define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK    0x8u
1111 #define PMU_REG_1P0D_CLR_BO_OFFSET_MASK          0x70u
1114 #define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK   0x80u
1116 #define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK         0x1F00u
1119 #define PMU_REG_1P0D_CLR_RSVD0_MASK              0xE000u
1122 #define PMU_REG_1P0D_CLR_BO_MASK                 0x10000u
1124 #define PMU_REG_1P0D_CLR_OK_MASK                 0x20000u
1126 #define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
1128 #define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
1130 #define PMU_REG_1P0D_CLR_REG_TEST_MASK           0xF00000u
1133 #define PMU_REG_1P0D_CLR_RSVD1_MASK              0x7F000000u
1136 #define PMU_REG_1P0D_CLR_OVERRIDE_MASK           0x80000000u
1139 #define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK      0x1u
1140 #define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT     0
1141 #define PMU_REG_1P0D_TOG_ENABLE_BO_MASK          0x2u
1143 #define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK      0x4u
1145 #define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK    0x8u
1147 #define PMU_REG_1P0D_TOG_BO_OFFSET_MASK          0x70u
1150 #define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK   0x80u
1152 #define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK         0x1F00u
1155 #define PMU_REG_1P0D_TOG_RSVD0_MASK              0xE000u
1158 #define PMU_REG_1P0D_TOG_BO_MASK                 0x10000u
1160 #define PMU_REG_1P0D_TOG_OK_MASK                 0x20000u
1162 #define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
1164 #define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
1166 #define PMU_REG_1P0D_TOG_REG_TEST_MASK           0xF00000u
1169 #define PMU_REG_1P0D_TOG_RSVD1_MASK              0x7F000000u
1172 #define PMU_REG_1P0D_TOG_OVERRIDE_MASK           0x80000000u
1175 #define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK      0x1u
1176 #define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT     0
1177 #define PMU_REG_HSIC_1P2_ENABLE_BO_MASK          0x2u
1179 #define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK      0x4u
1181 #define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK    0x8u
1183 #define PMU_REG_HSIC_1P2_BO_OFFSET_MASK          0x70u
1186 #define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK   0x80u
1188 #define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK         0x1F00u
1191 #define PMU_REG_HSIC_1P2_RSVD0_MASK              0xE000u
1194 #define PMU_REG_HSIC_1P2_BO_MASK                 0x10000u
1196 #define PMU_REG_HSIC_1P2_OK_MASK                 0x20000u
1198 #define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u
1200 #define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u
1202 #define PMU_REG_HSIC_1P2_REG_TEST_MASK           0xF00000u
1205 #define PMU_REG_HSIC_1P2_RSVD1_MASK              0x7F000000u
1208 #define PMU_REG_HSIC_1P2_OVERRIDE_MASK           0x80000000u
1211 #define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK  0x1u
1212 #define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0
1213 #define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK      0x2u
1215 #define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK  0x4u
1217 #define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u
1219 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK      0x70u
1222 #define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u
1224 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK     0x1F00u
1227 #define PMU_REG_HSIC_1P2_SET_RSVD0_MASK          0xE000u
1230 #define PMU_REG_HSIC_1P2_SET_BO_MASK             0x10000u
1232 #define PMU_REG_HSIC_1P2_SET_OK_MASK             0x20000u
1234 #define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
1236 #define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u
1238 #define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK       0xF00000u
1241 #define PMU_REG_HSIC_1P2_SET_RSVD1_MASK          0x7F000000u
1244 #define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK       0x80000000u
1247 #define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK  0x1u
1248 #define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0
1249 #define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK      0x2u
1251 #define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK  0x4u
1253 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u
1255 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK      0x70u
1258 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
1260 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK     0x1F00u
1263 #define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK          0xE000u
1266 #define PMU_REG_HSIC_1P2_CLR_BO_MASK             0x10000u
1268 #define PMU_REG_HSIC_1P2_CLR_OK_MASK             0x20000u
1270 #define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
1272 #define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
1274 #define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK       0xF00000u
1277 #define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK          0x7F000000u
1280 #define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK       0x80000000u
1283 #define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK  0x1u
1284 #define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0
1285 #define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK      0x2u
1287 #define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK  0x4u
1289 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u
1291 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK      0x70u
1294 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
1296 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK     0x1F00u
1299 #define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK          0xE000u
1302 #define PMU_REG_HSIC_1P2_TOG_BO_MASK             0x10000u
1304 #define PMU_REG_HSIC_1P2_TOG_OK_MASK             0x20000u
1306 #define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
1308 #define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
1310 #define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK       0xF00000u
1313 #define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK          0x7F000000u
1316 #define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK       0x80000000u
1319 #define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK      0x1u
1320 #define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT     0
1321 #define PMU_REG_LPSR_1P0_ENABLE_BO_MASK          0x2u
1323 #define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK      0x4u
1325 #define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK    0x8u
1327 #define PMU_REG_LPSR_1P0_BO_OFFSET_MASK          0x70u
1330 #define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK   0x80u
1332 #define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK         0x1F00u
1335 #define PMU_REG_LPSR_1P0_RSVD0_MASK              0xE000u
1338 #define PMU_REG_LPSR_1P0_BO_MASK                 0x10000u
1340 #define PMU_REG_LPSR_1P0_OK_MASK                 0x20000u
1342 #define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u
1344 #define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u
1346 #define PMU_REG_LPSR_1P0_REG_TEST_MASK           0xF00000u
1349 #define PMU_REG_LPSR_1P0_RSVD1_MASK              0xFF000000u
1353 #define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK  0x1u
1354 #define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0
1355 #define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK      0x2u
1357 #define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK  0x4u
1359 #define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u
1361 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK      0x70u
1364 #define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u
1366 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK     0x1F00u
1369 #define PMU_REG_LPSR_1P0_SET_RSVD0_MASK          0xE000u
1372 #define PMU_REG_LPSR_1P0_SET_BO_MASK             0x10000u
1374 #define PMU_REG_LPSR_1P0_SET_OK_MASK             0x20000u
1376 #define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
1378 #define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u
1380 #define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK       0xF00000u
1383 #define PMU_REG_LPSR_1P0_SET_RSVD1_MASK          0xFF000000u
1387 #define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK  0x1u
1388 #define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0
1389 #define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK      0x2u
1391 #define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK  0x4u
1393 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u
1395 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK      0x70u
1398 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
1400 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK     0x1F00u
1403 #define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK          0xE000u
1406 #define PMU_REG_LPSR_1P0_CLR_BO_MASK             0x10000u
1408 #define PMU_REG_LPSR_1P0_CLR_OK_MASK             0x20000u
1410 #define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
1412 #define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
1414 #define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK       0xF00000u
1417 #define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK          0xFF000000u
1421 #define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK  0x1u
1422 #define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0
1423 #define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK      0x2u
1425 #define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK  0x4u
1427 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u
1429 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK      0x70u
1432 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
1434 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK     0x1F00u
1437 #define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK          0xE000u
1440 #define PMU_REG_LPSR_1P0_TOG_BO_MASK             0x10000u
1442 #define PMU_REG_LPSR_1P0_TOG_OK_MASK             0x20000u
1444 #define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
1446 #define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
1448 #define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK       0xF00000u
1451 #define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK          0xFF000000u
1455 #define PMU_REG_3P0_ENABLE_LINREG_MASK           0x1u
1456 #define PMU_REG_3P0_ENABLE_LINREG_SHIFT          0
1457 #define PMU_REG_3P0_ENABLE_BO_MASK               0x2u
1459 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK           0x4u
1461 #define PMU_REG_3P0_RSVD0_MASK                   0x8u
1463 #define PMU_REG_3P0_BO_OFFSET_MASK               0x70u
1466 #define PMU_REG_3P0_VBUS_SEL_MASK                0x80u
1468 #define PMU_REG_3P0_OUTPUT_TRG_MASK              0x1F00u
1471 #define PMU_REG_3P0_RSVD1_MASK                   0xE000u
1474 #define PMU_REG_3P0_BO_VDD3P0_MASK               0x10000u
1476 #define PMU_REG_3P0_OK_VDD3P0_MASK               0x20000u
1478 #define PMU_REG_3P0_REG_TEST_MASK                0x3C0000u
1481 #define PMU_REG_3P0_RSVD2_MASK                   0xFFC00000u
1485 #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK       0x1u
1486 #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT      0
1487 #define PMU_REG_3P0_SET_ENABLE_BO_MASK           0x2u
1489 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK       0x4u
1491 #define PMU_REG_3P0_SET_RSVD0_MASK               0x8u
1493 #define PMU_REG_3P0_SET_BO_OFFSET_MASK           0x70u
1496 #define PMU_REG_3P0_SET_VBUS_SEL_MASK            0x80u
1498 #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK          0x1F00u
1501 #define PMU_REG_3P0_SET_RSVD1_MASK               0xE000u
1504 #define PMU_REG_3P0_SET_BO_VDD3P0_MASK           0x10000u
1506 #define PMU_REG_3P0_SET_OK_VDD3P0_MASK           0x20000u
1508 #define PMU_REG_3P0_SET_REG_TEST_MASK            0x3C0000u
1511 #define PMU_REG_3P0_SET_RSVD2_MASK               0xFFC00000u
1515 #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK       0x1u
1516 #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT      0
1517 #define PMU_REG_3P0_CLR_ENABLE_BO_MASK           0x2u
1519 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK       0x4u
1521 #define PMU_REG_3P0_CLR_RSVD0_MASK               0x8u
1523 #define PMU_REG_3P0_CLR_BO_OFFSET_MASK           0x70u
1526 #define PMU_REG_3P0_CLR_VBUS_SEL_MASK            0x80u
1528 #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK          0x1F00u
1531 #define PMU_REG_3P0_CLR_RSVD1_MASK               0xE000u
1534 #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK           0x10000u
1536 #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK           0x20000u
1538 #define PMU_REG_3P0_CLR_REG_TEST_MASK            0x3C0000u
1541 #define PMU_REG_3P0_CLR_RSVD2_MASK               0xFFC00000u
1545 #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK       0x1u
1546 #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT      0
1547 #define PMU_REG_3P0_TOG_ENABLE_BO_MASK           0x2u
1549 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK       0x4u
1551 #define PMU_REG_3P0_TOG_RSVD0_MASK               0x8u
1553 #define PMU_REG_3P0_TOG_BO_OFFSET_MASK           0x70u
1556 #define PMU_REG_3P0_TOG_VBUS_SEL_MASK            0x80u
1558 #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK          0x1F00u
1561 #define PMU_REG_3P0_TOG_RSVD1_MASK               0xE000u
1564 #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK           0x10000u
1566 #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK           0x20000u
1568 #define PMU_REG_3P0_TOG_REG_TEST_MASK            0x3C0000u
1571 #define PMU_REG_3P0_TOG_RSVD2_MASK               0xFFC00000u
1575 #define PMU_REF_REFTOP_PWD_MASK                  0x1u
1576 #define PMU_REF_REFTOP_PWD_SHIFT                 0
1577 #define PMU_REF_REFTOP_PWDVBGUP_MASK             0x2u
1579 #define PMU_REF_REFTOP_LOWPOWER_MASK             0x4u
1581 #define PMU_REF_REFTOP_SELFBIASOFF_MASK          0x8u
1583 #define PMU_REF_REFTOP_VBGADJ_MASK               0x70u
1586 #define PMU_REF_REFTOP_VBGUP_MASK                0x80u
1588 #define PMU_REF_REFTOP_BIAS_TST_MASK             0x300u
1591 #define PMU_REF_LPBG_SEL_MASK                    0x400u
1593 #define PMU_REF_LPBG_TEST_MASK                   0x800u
1595 #define PMU_REF_REFTOP_IBIAS_OFF_MASK            0x1000u
1597 #define PMU_REF_REFTOP_LINREGREF_EN_MASK         0x2000u
1599 #define PMU_REF_RSVD1_MASK                       0xFFFFC000u
1603 #define PMU_REF_SET_REFTOP_PWD_MASK              0x1u
1604 #define PMU_REF_SET_REFTOP_PWD_SHIFT             0
1605 #define PMU_REF_SET_REFTOP_PWDVBGUP_MASK         0x2u
1607 #define PMU_REF_SET_REFTOP_LOWPOWER_MASK         0x4u
1609 #define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK      0x8u
1611 #define PMU_REF_SET_REFTOP_VBGADJ_MASK           0x70u
1614 #define PMU_REF_SET_REFTOP_VBGUP_MASK            0x80u
1616 #define PMU_REF_SET_REFTOP_BIAS_TST_MASK         0x300u
1619 #define PMU_REF_SET_LPBG_SEL_MASK                0x400u
1621 #define PMU_REF_SET_LPBG_TEST_MASK               0x800u
1623 #define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK        0x1000u
1625 #define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK     0x2000u
1627 #define PMU_REF_SET_RSVD1_MASK                   0xFFFFC000u
1631 #define PMU_REF_CLR_REFTOP_PWD_MASK              0x1u
1632 #define PMU_REF_CLR_REFTOP_PWD_SHIFT             0
1633 #define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK         0x2u
1635 #define PMU_REF_CLR_REFTOP_LOWPOWER_MASK         0x4u
1637 #define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK      0x8u
1639 #define PMU_REF_CLR_REFTOP_VBGADJ_MASK           0x70u
1642 #define PMU_REF_CLR_REFTOP_VBGUP_MASK            0x80u
1644 #define PMU_REF_CLR_REFTOP_BIAS_TST_MASK         0x300u
1647 #define PMU_REF_CLR_LPBG_SEL_MASK                0x400u
1649 #define PMU_REF_CLR_LPBG_TEST_MASK               0x800u
1651 #define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK        0x1000u
1653 #define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK     0x2000u
1655 #define PMU_REF_CLR_RSVD1_MASK                   0xFFFFC000u
1659 #define PMU_REF_TOG_REFTOP_PWD_MASK              0x1u
1660 #define PMU_REF_TOG_REFTOP_PWD_SHIFT             0
1661 #define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK         0x2u
1663 #define PMU_REF_TOG_REFTOP_LOWPOWER_MASK         0x4u
1665 #define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK      0x8u
1667 #define PMU_REF_TOG_REFTOP_VBGADJ_MASK           0x70u
1670 #define PMU_REF_TOG_REFTOP_VBGUP_MASK            0x80u
1672 #define PMU_REF_TOG_REFTOP_BIAS_TST_MASK         0x300u
1675 #define PMU_REF_TOG_LPBG_SEL_MASK                0x400u
1677 #define PMU_REF_TOG_LPBG_TEST_MASK               0x800u
1679 #define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK        0x1000u
1681 #define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK     0x2000u
1683 #define PMU_REF_TOG_RSVD1_MASK                   0xFFFFC000u
1687 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK    0x3u
1688 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT   0
1690 #define PMU_LOWPWR_CTRL_RSVD0_MASK               0xFCu
1693 #define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK          0x100u
1695 #define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK          0x200u
1697 #define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK         0x400u
1699 #define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK     0x800u
1701 #define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK         0x1000u
1703 #define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK         0x2000u
1705 #define PMU_LOWPWR_CTRL_CONTROL0_MASK            0xFFC000u
1708 #define PMU_LOWPWR_CTRL_CONTROL1_MASK            0xFF000000u
1712 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u
1713 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0
1715 #define PMU_LOWPWR_CTRL_SET_RSVD0_MASK           0xFCu
1718 #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK      0x100u
1720 #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK      0x200u
1722 #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK     0x400u
1724 #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u
1726 #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK     0x1000u
1728 #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK     0x2000u
1730 #define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK        0xFFC000u
1733 #define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK        0xFF000000u
1737 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u
1738 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0
1740 #define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK           0xFCu
1743 #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK      0x100u
1745 #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK      0x200u
1747 #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK     0x400u
1749 #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u
1751 #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK     0x1000u
1753 #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK     0x2000u
1755 #define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK        0xFFC000u
1758 #define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK        0xFF000000u
1762 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u
1763 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0
1765 #define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK           0xFCu
1768 #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK      0x100u
1770 #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK      0x200u
1772 #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK     0x400u
1774 #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u
1776 #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK     0x1000u
1778 #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK     0x2000u
1780 #define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK        0xFFC000u
1783 #define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK        0xFF000000u
1789 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu
1790 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0
1792 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u
1795 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u
1798 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK  0xF8000000u
1802 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu
1803 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0
1805 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u
1808 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u
1811 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u
1815 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu
1816 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0
1818 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u
1821 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u
1824 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u
1828 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu
1829 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0
1831 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u
1834 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u
1837 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u
1841 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu
1842 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0
1844 #define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u
1846 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u
1848 #define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u
1850 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK  0xF000u
1853 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u
1857 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu
1858 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0
1860 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u
1862 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u
1864 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u
1866 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u
1869 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u
1873 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu
1874 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0
1876 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u
1878 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u
1880 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u
1882 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u
1885 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u
1889 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu
1890 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0
1892 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u
1894 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u
1896 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u
1898 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u
1901 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u
1905 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu
1906 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0
1908 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u
1911 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u
1913 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u
1916 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u
1919 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u
1922 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u
1925 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u
1929 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu
1930 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0
1932 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u
1935 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u
1937 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u
1940 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u
1943 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u
1946 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u
1949 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u
1953 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu
1954 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0
1956 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u
1959 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u
1961 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u
1964 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u
1967 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u
1970 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u
1973 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u
1977 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu
1978 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0
1980 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u
1983 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u
1985 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u
1988 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u
1991 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u
1994 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u
1997 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u
2002 #define CCM_GPR(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
2003 #define CCM_OBSERVE(i)		(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
2004 #define CCM_SCTRL(i)		(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
2005 #define CCM_CCGR(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i))
2006 #define CCM_ROOT_TARGET(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
2008 #define CCM_GPR_SET(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
2009 #define CCM_OBSERVE_SET(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
2010 #define CCM_SCTRL_SET(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
2011 #define CCM_CCGR_SET(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
2012 #define CCM_ROOT_TARGET_SET(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
2014 #define CCM_GPR_CLR(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
2015 #define CCM_OBSERVE_CLR(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
2016 #define CCM_SCTRL_CLR(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
2017 #define CCM_CCGR_CLR(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
2018 #define CCM_ROOT_TARGET_CLR(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
2020 #define CCM_GPR_TOGGLE(i)	(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
2021 #define CCM_OBSERVE_TOGGLE(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
2022 #define CCM_SCTRL_TOGGLE(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
2023 #define CCM_CCGR_TOGGLE(i)	(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
2024 #define CCM_ROOT_TARGET_TOGGLE(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
2056 #define CCM_CLK_ON_MSK	0x03
2057 #define CCM_CLK_ON_N_N	0x00 /* Domain clocks not needed */
2058 #define CCM_CLK_ON_R_W	0x02 /* Domain clocks needed when in RUN and WAIT */
2063 #define CCM_ROOT_TGT_POST_DIV_SHIFT	0
2067 #define CCM_ROOT_TGT_POST_DIV_MSK	0x3F
2068 #define CCM_ROOT_TGT_PRE_DIV_MSK	(0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT)
2069 #define CCM_ROOT_TGT_MUX_MSK		(0x07 << CCM_ROOT_TGT_MUX_SHIFT)
2070 #define CCM_ROOT_TGT_ENABLE_MSK		(0x01 << CCM_ROOT_TGT_ENABLE_SHIFT)
2080 #define CLK_ROOT_ON		0x10000000
2081 #define CLK_ROOT_OFF		0x0
2082 #define CLK_ROOT_ENABLE_MASK	0x10000000
2085 #define CLK_ROOT_ALT0		0x00000000
2086 #define CLK_ROOT_ALT1		0x01000000
2087 #define CLK_ROOT_ALT2		0x02000000
2088 #define CLK_ROOT_ALT3		0x03000000
2089 #define CLK_ROOT_ALT4		0x04000000
2090 #define CLK_ROOT_ALT5		0x05000000
2091 #define CLK_ROOT_ALT6		0x06000000
2092 #define CLK_ROOT_ALT7		0x07000000
2095 #define DRAM_CLK_ROOT_POST_DIV_MASK	0x00000007
2096 #define CLK_ROOT_POST_DIV_MASK	0x0000003f
2097 #define CLK_ROOT_POST_DIV_SHIFT	0
2100 #define CLK_ROOT_AUTO_DIV_MASK	0x00000700
2104 #define CLK_ROOT_AUTO_EN_MASK	0x00001000
2105 #define CLK_ROOT_AUTO_EN	0x00001000
2107 #define CLK_ROOT_PRE_DIV_MASK	0x00070000
2111 #define CLK_ROOT_MUX_MASK	0x07000000
2114 #define CLK_ROOT_EN_MASK	0x10000000
2116 #define CLK_ROOT_AUTO_ON	0x00001000
2117 #define CLK_ROOT_AUTO_OFF	0x0
2120 #define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2121 #define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK		0x01000000
2122 #define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK		0x03000000
2123 #define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2124 #define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x05000000
2125 #define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x02000000
2126 #define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
2127 #define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2130 #define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2131 #define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x04000000
2132 #define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2133 #define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x03000000
2134 #define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x02000000
2135 #define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x05000000
2136 #define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x06000000
2137 #define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2140 #define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2141 #define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x04000000
2142 #define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
2143 #define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x03000000
2144 #define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x02000000
2145 #define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x05000000
2146 #define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x06000000
2147 #define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2150 #define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2151 #define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2152 #define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK		0x01000000
2153 #define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK			0x04000000
2154 #define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
2155 #define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x03000000
2156 #define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
2157 #define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2160 #define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2161 #define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2162 #define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK		0x01000000
2163 #define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x04000000
2164 #define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x05000000
2165 #define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x03000000
2166 #define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x06000000
2167 #define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
2170 #define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2171 #define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2172 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x04000000
2173 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x01000000
2174 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x07000000
2175 #define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x03000000
2176 #define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
2177 #define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2180 #define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK		0x00000000
2181 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x02000000
2182 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK	0x03000000
2183 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK	0x01000000
2184 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK	0x04000000
2185 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK		0x05000000
2186 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK	0x06000000
2187 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x07000000
2190 #define AHB_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2191 #define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2192 #define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK			0x03000000
2193 #define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK			0x01000000
2194 #define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
2195 #define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
2196 #define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
2197 #define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK			0x05000000
2200 #define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK		0x00000000
2201 #define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT	0x01000000
2204 #define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK		0x00000000
2205 #define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT		0x01000000
2208 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2209 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x01000000
2210 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK	0x02000000
2211 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK		0x05000000
2212 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK	0x03000000
2213 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x06000000
2214 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
2215 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK	0x04000000
2218 #define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2219 #define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x01000000
2220 #define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x02000000
2221 #define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x05000000
2222 #define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x07000000
2223 #define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
2224 #define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x04000000
2225 #define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x06000000
2228 #define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2229 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x01000000
2230 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK			0x03000000
2231 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x04000000
2232 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK			0x05000000
2233 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
2234 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
2235 #define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x02000000
2238 #define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2239 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x04000000
2240 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x02000000
2241 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK		0x06000000
2242 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x03000000
2243 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK		0x07000000
2244 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x05000000
2245 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x01000000
2248 #define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2249 #define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x07000000
2250 #define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x02000000
2251 #define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2252 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1			0x03000000
2253 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2			0x04000000
2254 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
2255 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4			0x06000000
2258 #define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2259 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2260 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x03000000
2261 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK		0x01000000
2262 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK		0x04000000
2263 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK		0x05000000
2264 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK		0x06000000
2265 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
2268 #define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2269 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x02000000
2270 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
2271 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK		0x04000000
2272 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK		0x01000000
2273 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2274 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2275 #define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3			0x03000000
2278 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK		0x00000000
2279 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x05000000
2280 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK	0x03000000
2281 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK	0x04000000
2282 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK		0x02000000
2283 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK		0x01000000
2284 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK	0x07000000
2285 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK	0x06000000
2288 #define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2289 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x05000000
2290 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK	0x03000000
2291 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK	0x04000000
2292 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK		0x02000000
2293 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK		0x01000000
2294 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x07000000
2295 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2298 #define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2299 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x02000000
2300 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK	0x01000000
2301 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK		0x03000000
2302 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2303 #define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK			0x04000000
2304 #define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2			0x05000000
2305 #define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3			0x07000000
2308 #define SAI1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2309 #define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2310 #define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2311 #define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
2312 #define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
2313 #define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x02000000
2314 #define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
2315 #define SAI1_CLK_ROOT_FROM_EXT_CLK_2				0x07000000
2318 #define SAI2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2319 #define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2320 #define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2321 #define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
2322 #define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
2323 #define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x02000000
2324 #define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
2325 #define SAI2_CLK_ROOT_FROM_EXT_CLK_2				0x07000000
2328 #define SAI3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2329 #define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2330 #define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2331 #define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
2332 #define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
2333 #define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x02000000
2334 #define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
2335 #define SAI3_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
2338 #define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2339 #define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2340 #define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2341 #define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
2342 #define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
2343 #define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x02000000
2344 #define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
2345 #define SPDIF_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
2348 #define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2349 #define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x04000000
2350 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x01000000
2351 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
2352 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK		0x03000000
2353 #define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
2354 #define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2355 #define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4			0x07000000
2358 #define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2359 #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2360 #define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x02000000
2361 #define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
2362 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1			0x03000000
2363 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2			0x04000000
2364 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
2365 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4			0x06000000
2368 #define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2369 #define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x04000000
2370 #define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x01000000
2371 #define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
2372 #define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK		0x03000000
2373 #define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
2374 #define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2375 #define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4			0x07000000
2378 #define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2379 #define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2380 #define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x02000000
2381 #define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
2382 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1			0x03000000
2383 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2			0x04000000
2384 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
2385 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4			0x06000000
2388 #define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2389 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x04000000
2390 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK		0x07000000
2391 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK	0x03000000
2392 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK	0x02000000
2393 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK	0x01000000
2394 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
2395 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2398 #define EIM_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2399 #define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2400 #define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK			0x02000000
2401 #define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK			0x04000000
2402 #define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK			0x01000000
2403 #define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK			0x05000000
2404 #define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
2405 #define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK			0x07000000
2408 #define NAND_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2409 #define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2410 #define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x01000000
2411 #define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x03000000
2412 #define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK			0x04000000
2413 #define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x05000000
2414 #define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
2415 #define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
2418 #define QSPI_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2419 #define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2420 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
2421 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK			0x04000000
2422 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x01000000
2423 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
2424 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
2425 #define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
2428 #define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2429 #define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2430 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x01000000
2431 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
2432 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x04000000
2433 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
2434 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
2435 #define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
2438 #define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2439 #define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2440 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x01000000
2441 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
2442 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x04000000
2443 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
2444 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
2445 #define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
2448 #define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2449 #define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2450 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x01000000
2451 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
2452 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x04000000
2453 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
2454 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
2455 #define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
2458 #define CAN1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2459 #define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2460 #define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x03000000
2461 #define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
2462 #define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x04000000
2463 #define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x05000000
2464 #define CAN1_CLK_ROOT_FROM_EXT_CLK_1				0x06000000
2465 #define CAN1_CLK_ROOT_FROM_EXT_CLK_4				0x07000000
2468 #define CAN2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2469 #define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2470 #define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x03000000
2471 #define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
2472 #define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x04000000
2473 #define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x05000000
2474 #define CAN2_CLK_ROOT_FROM_EXT_CLK_1				0x06000000
2475 #define CAN2_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
2478 #define I2C1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2479 #define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2480 #define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
2481 #define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x07000000
2482 #define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
2483 #define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
2484 #define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
2485 #define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x06000000
2488 #define I2C2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2489 #define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2490 #define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
2491 #define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x07000000
2492 #define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
2493 #define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
2494 #define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
2495 #define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x06000000
2498 #define I2C3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2499 #define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2500 #define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
2501 #define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x07000000
2502 #define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
2503 #define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
2504 #define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
2505 #define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x06000000
2508 #define I2C4_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2509 #define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2510 #define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
2511 #define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x07000000
2512 #define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
2513 #define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
2514 #define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
2515 #define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x06000000
2518 #define UART1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2519 #define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2520 #define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2521 #define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
2522 #define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2523 #define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2524 #define UART1_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
2525 #define UART1_CLK_ROOT_FROM_EXT_CLK_4				0x06000000
2528 #define UART2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2529 #define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2530 #define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2531 #define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
2532 #define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2533 #define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2534 #define UART2_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
2535 #define UART2_CLK_ROOT_FROM_EXT_CLK_3				0x06000000
2538 #define UART3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2539 #define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2540 #define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2541 #define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
2542 #define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2543 #define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2544 #define UART3_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
2545 #define UART3_CLK_ROOT_FROM_EXT_CLK_4				0x06000000
2548 #define UART4_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2549 #define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2550 #define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2551 #define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
2552 #define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2553 #define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2554 #define UART4_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
2555 #define UART4_CLK_ROOT_FROM_EXT_CLK_3				0x06000000
2558 #define UART5_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2559 #define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2560 #define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2561 #define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
2562 #define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2563 #define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2564 #define UART5_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
2565 #define UART5_CLK_ROOT_FROM_EXT_CLK_4				0x06000000
2568 #define UART6_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2569 #define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2570 #define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2571 #define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
2572 #define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2573 #define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2574 #define UART6_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
2575 #define UART6_CLK_ROOT_FROM_EXT_CLK_3				0x06000000
2578 #define UART7_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2579 #define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2580 #define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2581 #define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
2582 #define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2583 #define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2584 #define UART7_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
2585 #define UART7_CLK_ROOT_FROM_EXT_CLK_4				0x06000000
2588 #define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2589 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2590 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2591 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x03000000
2592 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
2593 #define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
2594 #define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2595 #define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2598 #define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2599 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2600 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2601 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x03000000
2602 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
2603 #define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
2604 #define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2605 #define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2608 #define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2609 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2610 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2611 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x03000000
2612 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
2613 #define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
2614 #define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2615 #define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2618 #define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2619 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
2620 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
2621 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x03000000
2622 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
2623 #define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
2624 #define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
2625 #define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2628 #define PWM1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2629 #define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2630 #define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2631 #define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2632 #define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
2633 #define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
2634 #define PWM1_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
2635 #define PWM1_CLK_ROOT_FROM_EXT_CLK_1				0x05000000
2638 #define PWM2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2639 #define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2640 #define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2641 #define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2642 #define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
2643 #define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
2644 #define PWM2_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
2645 #define PWM2_CLK_ROOT_FROM_EXT_CLK_1				0x05000000
2648 #define PWM3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2649 #define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2650 #define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2651 #define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2652 #define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
2653 #define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
2654 #define PWM3_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
2655 #define PWM3_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
2658 #define PWM4_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2659 #define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2660 #define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2661 #define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2662 #define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
2663 #define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
2664 #define PWM4_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
2665 #define PWM4_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
2668 #define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2669 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2670 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2671 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2672 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x04000000
2673 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
2674 #define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK			0x06000000
2675 #define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
2678 #define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2679 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2680 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2681 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2682 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x04000000
2683 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
2684 #define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK			0x06000000
2685 #define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
2688 #define SIM1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2689 #define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2690 #define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2691 #define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2692 #define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
2693 #define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
2694 #define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x05000000
2695 #define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x04000000
2698 #define SIM2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2699 #define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2700 #define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2701 #define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2702 #define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
2703 #define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
2704 #define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
2705 #define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x04000000
2708 #define GPT1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2709 #define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x02000000
2710 #define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2711 #define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2712 #define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
2713 #define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
2714 #define GPT1_CLK_ROOT_FROM_REF_1M_CLK				0x05000000
2715 #define GPT1_CLK_ROOT_FROM_EXT_CLK_1				0x07000000
2718 #define GPT2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2719 #define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x02000000
2720 #define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2721 #define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2722 #define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
2723 #define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
2724 #define GPT2_CLK_ROOT_FROM_REF_1M_CLK				0x05000000
2725 #define GPT2_CLK_ROOT_FROM_EXT_CLK_2				0x07000000
2728 #define GPT3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2729 #define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x02000000
2730 #define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2731 #define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2732 #define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
2733 #define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
2734 #define GPT3_CLK_ROOT_FROM_REF_1M_CLK				0x05000000
2735 #define GPT3_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
2738 #define GPT4_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2739 #define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x02000000
2740 #define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
2741 #define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
2742 #define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
2743 #define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
2744 #define GPT4_CLK_ROOT_FROM_REF_1M_CLK				0x05000000
2745 #define GPT4_CLK_ROOT_FROM_EXT_CLK_4				0x07000000
2748 #define TRACE_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2749 #define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2750 #define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2751 #define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2752 #define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
2753 #define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x05000000
2754 #define TRACE_CLK_ROOT_FROM_EXT_CLK_1				0x06000000
2755 #define TRACE_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
2758 #define WDOG_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2759 #define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2760 #define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2761 #define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK		0x07000000
2762 #define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2763 #define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
2764 #define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x05000000
2765 #define WDOG_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
2768 #define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2769 #define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2770 #define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2771 #define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2772 #define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
2773 #define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
2774 #define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2775 #define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2778 #define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
2779 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
2780 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
2781 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
2782 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
2783 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
2784 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
2785 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
2788 #define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
2789 #define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
2790 #define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x04000000
2791 #define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
2792 #define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
2793 #define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x06000000
2794 #define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x01000000
2795 #define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x03000000
2798 #define IPP_DO_CLKO1_FROM_OSC_24M_CLK				0x00000000
2799 #define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK		0x06000000
2800 #define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK			0x01000000
2801 #define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK			0x02000000
2802 #define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK			0x03000000
2803 #define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK			0x04000000
2804 #define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK		0x05000000
2805 #define IPP_DO_CLKO1_FROM_REF_1M_CLK				0x07000000
2808 #define IPP_DO_CLKO2_FROM_OSC_24M_CLK				0x00000000
2809 #define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK			0x01000000
2810 #define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK			0x02000000
2811 #define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK			0x03000000
2812 #define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK			0x04000000
2813 #define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK			0x05000000
2814 #define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK			0x06000000
2815 #define IPP_DO_CLKO2_FROM_OSC_32K_CLK				0x07000000