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/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dconfig.h13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
48 #define GICD_BASE 0x06000000
49 #define GICR_BASE 0x06100000
52 #define SMMU_BASE 0x05000000 /* GR0 Base */
69 #define CCI_MN_BASE 0x04000000
[all …]
H A Dimmap_lsch3.h12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
[all …]
H A Dimmap_lsch2.h11 #define CONFIG_SYS_IMMR 0x01000000
12 #define CONFIG_SYS_DCSRBAR 0x20000000
13 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
14 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
17 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
18 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dimx-sata.yaml77 reg = <0x02200000 0x4000>;
78 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull.dtsi58 reg = <0x02200000 0x100000>;
63 reg = <0x02280000 0x4000>;
73 reg = <0x02284000 0x4000>;
80 reg = <0x02290000 0x4000>;
86 reg = <0x02288000 0x4000>;
H A Dimx6q.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
165 reg = <0x00900000 0x40000>;
166 ranges = <0 0x00900000 0x40000>;
176 #size-cells = <0>;
178 reg = <0x02018000 0x4000>;
179 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
192 reg = <0x02200000 0x4000>;
193 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
[all …]
H A Dimx6sl.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
86 #clock-cells = <0>;
92 #clock-cells = <0>;
100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
105 #phy-cells = <0>;
117 reg = <0x00900000 0x20000>;
118 ranges = <0 0x00900000 0x20000>;
128 reg = <0x00a01000 0x1000>,
[all …]
H A Dimx6sx.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dconfig.h9 #define OCRAM_BASE_ADDR 0x10000000
10 #define OCRAM_SIZE 0x00010000
11 #define OCRAM_BASE_S_ADDR 0x10010000
12 #define OCRAM_S_SIZE 0x00010000
14 #define CONFIG_SYS_IMMR 0x01000000
15 #define CONFIG_SYS_DCSRBAR 0x20000000
17 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
18 #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
20 #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
21 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dcoredump.c16 .start = 0xe003b400,
17 .len = 0x00003bff,
24 .start = 0x00800000,
25 .len = 0x0005ffff,
29 .start = 0x00900000,
30 .len = 0x00013fff,
34 .start = 0x02200000,
35 .len = 0x0004ffff,
39 .start = 0x02300000,
40 .len = 0x0004ffff,
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dcoredump.c16 .start = 0x00800000,
17 .len = 0x0004ffff,
21 .start = 0x00900000,
22 .len = 0x00037fff,
26 .start = 0x02200000,
27 .len = 0x0003ffff,
31 .start = 0x00400000,
32 .len = 0x00067fff,
36 .start = 0xe0000000,
37 .len = 0x0015ffff,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h11 #define ROMCP_ARB_BASE_ADDR 0x00000000
12 #define ROMCP_ARB_END_ADDR 0x000FFFFF
15 #define GPU_2D_ARB_BASE_ADDR 0x02200000
16 #define GPU_2D_ARB_END_ADDR 0x02203FFF
17 #define OPENVG_ARB_BASE_ADDR 0x02204000
18 #define OPENVG_ARB_END_ADDR 0x02207FFF
20 #define CAAM_ARB_BASE_ADDR 0x00100000
21 #define CAAM_ARB_END_ADDR 0x00107FFF
22 #define GPU_ARB_BASE_ADDR 0x01800000
23 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/openbmc/u-boot/include/configs/
H A Dsocfpga_common.h20 #define PHYS_SDRAM_1 0x0
25 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
26 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
28 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
29 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
75 * that the address here is incremented by 0x400 from the Base address
76 * selected in QSys, since the SPI registers are at offset +0x400.
77 * #define CONFIG_SYS_SPI_BASE 0xff240400
96 * L4 OSC1 Timer 0
102 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
[all …]
/openbmc/u-boot/include/
H A Dfsl_qe.h20 #define QE_DATAONLY_BASE 0
37 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
38 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
39 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
40 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
50 #define QE_CR_FLG 0x00010000
51 #define QE_RESET 0x80000000
52 #define QE_INIT_TX_RX 0x00000000
53 #define QE_INIT_RX 0x00000001
54 #define QE_INIT_TX 0x00000002
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx6.h84 #define FSL_IMX6_MMDC_ADDR 0x10000000
85 #define FSL_IMX6_MMDC_SIZE 0xF0000000
86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88 #define FSL_IMX6_IPU_2_ADDR 0x02800000
89 #define FSL_IMX6_IPU_2_SIZE 0x400000
90 #define FSL_IMX6_IPU_1_ADDR 0x02400000
91 #define FSL_IMX6_IPU_1_SIZE 0x400000
92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/openbmc/linux/arch/arm/net/
H A Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6q.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
160 reg = <0x00900000 0x40000>;
168 #size-cells = <0>;
170 reg = <0x02018000 0x4000>;
171 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
188 reg = <0x02200000 0x4000>;
189 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
199 reg = <0x02204000 0x4000>;
[all …]
H A Dimx6sx.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0>;
94 reg = <0x00a01000 0x1000>,
95 <0x00a00100 0x100>;
101 #size-cells = <0>;
103 ckil: clock@0 {
105 reg = <0>;
106 #clock-cells = <0>;
114 #clock-cells = <0>;
[all …]
H A Dimx6ull.dtsi53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0>;
90 reg = <0x00a01000 0x1000>,
91 <0x00a02000 0x100>;
96 #size-cells = <0>;
98 ckil: clock@0 {
100 reg = <0>;
101 #clock-cells = <0>;
109 #clock-cells = <0>;
[all …]
/openbmc/linux/include/soc/fsl/qe/
H A Dqe.h32 QE_CLK_NONE = 0,
131 return 0; in cpm_muram_dma()
227 return 0; in qe_alive_during_sleep()
271 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
284 __be32 traps[16]; /* Trap addresses, 0 == ignore */
328 #define BD_STATUS_MASK 0xffff0000
329 #define BD_LENGTH_MASK 0x0000ffff
337 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
338 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
339 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc105 tcg_debug_assert(slot >= 0 && slot <= 1);
109 #define TCG_CT_CONST_ZERO 0x100
110 #define TCG_CT_CONST_S12 0x200
111 #define TCG_CT_CONST_N12 0x400
112 #define TCG_CT_CONST_M12 0x800
113 #define TCG_CT_CONST_J12 0x1000
114 #define TCG_CT_CONST_S5 0x2000
115 #define TCG_CT_CONST_CMP_VI 0x4000
117 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
119 #define ALL_DVECTOR_REG_GROUPS 0x5555555500000000
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]