Lines Matching +full:0 +full:x02200000
11 #define CONFIG_SYS_IMMR 0x01000000
12 #define CONFIG_SYS_DCSRBAR 0x20000000
13 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
14 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
17 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
18 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
22 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
23 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
24 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
25 #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
26 #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
27 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
28 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
29 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
30 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
31 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
32 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
33 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
34 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
35 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
36 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
37 #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
38 #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
39 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
40 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
41 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
42 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
43 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
46 #define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
47 #define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
49 #define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
50 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
51 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
57 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
59 #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
61 #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
62 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000
63 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
69 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
71 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
73 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
74 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
75 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
76 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000)
78 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
80 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
81 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
83 #define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000)
84 #define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000)
85 #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000)
86 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000)
88 #define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000)
90 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
92 #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000)
94 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
96 #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
97 #define QMAN_CQSIDR_REG 0x20a80
99 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
100 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
101 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
104 #define PCIE_LUT_BASE 0xC0000
106 #define PCIE_LUT_BASE 0x10000
108 #define PCIE_LUT_LCTRL0 0x7F8
109 #define PCIE_LUT_DBG 0x7FC
112 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
113 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
114 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
115 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
116 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
117 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
118 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
119 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
120 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
121 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
122 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
123 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
124 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
126 #define TP_ITYP_AV 0x00000001 /* Initiator available */
127 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
128 #define TP_ITYP_TYPE_ARM 0x0
129 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
130 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
131 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
132 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
133 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
134 #define TY_ITYP_VER_A7 0x1
135 #define TY_ITYP_VER_A53 0x2
136 #define TY_ITYP_VER_A57 0x3
137 #define TY_ITYP_VER_A72 0x4
139 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
140 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
159 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
163 #define CONFIG_SYS_CCSRBAR 0x01000000
167 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
171 #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
190 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
191 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
192 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
193 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
194 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
195 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
196 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
198 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
204 #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
205 #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
207 #define FSL_SEC_JR1_OFFSET 0x720000ull
208 #define FSL_SEC_JR2_OFFSET 0x730000ull
209 #define FSL_SEC_JR3_OFFSET 0x740000ull
220 #define DCFG_DCSR_PORCR1 0x0
221 #define DCFG_DCSR_ECCCR2 0x524
226 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
228 u8 res_008[0x20-0x8];
232 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F
234 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F
236 u8 res_02c[0x70-0x2c];
238 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000
239 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000
240 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000
241 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000
242 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000
243 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000
244 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000
245 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
246 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000
247 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
248 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
249 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
256 u8 res_08c[0x94-0x8c];
259 u8 res_09c[0xa0-0x9c];
263 u8 res_0ac[0xb0-0xac];
266 u8 res_0b8[0xc0-0xb8];
268 u8 res_0c4[0xc8-0xc4];
270 u8 res_0cc[0xd4-0xcc];
272 u8 res_0d8[0xdc-0xd8];
274 u8 res_0e0[0xe4-0xe0];
276 u8 res_0e8[0x100-0xe8];
279 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
281 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
282 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
284 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
285 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
287 #define RCW_SB_EN_MASK 0x00200000
289 u8 res_140[0x200-0x140];
291 u8 res_210[0x300-0x210];
293 u8 res_310[0x400-0x310];
295 u8 res_430[0x500-0x430];
320 u8 res_544[0x550-0x544];
322 u8 res_560[0x570-0x560];
336 u8 res_5a0[0x600-0x5a0];
342 u8 res_60c[0x610-0x60c];
354 u8 res_63c[0x658-0x63c];
357 u8 res_660[0x678-0x660];
361 u8 res_680[0x700-0x680];
365 u8 res_708[0x740-0x708]; /* add more registers when needed */
371 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
373 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
378 #define SCFG_QSPI_CLKSEL 0x40100000
379 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
380 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
381 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002
382 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000
383 #define SCFG_USBPWRFAULT_SHARED 0x00000001
384 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002
387 #define SCFG_USBPWRFAULT_USB1_SHIFT 0
389 #define SCFG_BASE 0x01570000
390 #define SCFG_USB3PRM1CR_USB1 0x070
391 #define SCFG_USB3PRM2CR_USB1 0x074
392 #define SCFG_USB3PRM1CR_USB2 0x07C
393 #define SCFG_USB3PRM2CR_USB2 0x080
394 #define SCFG_USB3PRM1CR_USB3 0x088
395 #define SCFG_USB3PRM2CR_USB3 0x08c
396 #define SCFG_USB_TXVREFTUNE 0x9
397 #define SCFG_USB_SQRXTUNE_MASK 0x7
398 #define SCFG_USB_PCSTXSWINGFULL 0x47
399 #define SCFG_USB_PHY1 0x084F0000
400 #define SCFG_USB_PHY2 0x08500000
401 #define SCFG_USB_PHY3 0x08510000
402 #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c
403 #define USB_PHY_RX_EQ_VAL_1 0x0000
404 #define USB_PHY_RX_EQ_VAL_2 0x0080
405 #define USB_PHY_RX_EQ_VAL_3 0x0380
406 #define USB_PHY_RX_EQ_VAL_4 0x0b80
408 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
409 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
410 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
411 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
416 #define SCFG_RGMIIPCR_SETSP_100M 0
418 #define SCFG_RGMIIPCR_SETFD BIT(0)
438 u8 res_000[0x100-0x000];
441 u8 res_108[0x114-0x108];
450 u8 res_140[0x158-0x140];
453 u8 res_160[0x164 - 0x160];
458 u8 res_174[0x180 - 0x174];
460 u8 res_184[0x188-0x184];
463 u8 res_190[0x1a4-0x190];
465 u8 res_1a8[0x1ac-0x1a8];
467 u8 res_1b0[0x204-0x1b0];
469 u8 res_208[0x220-0x208];
479 u8 res_244[0x400-0x244];
489 u8 res_424[0x434 - 0x424];
501 u8 res_460[0x484 - 0x460];
503 u8 res_468[0x600 - 0x488];
505 u8 res_610[0x680-0x610];
507 u8 res_684[0x1000-0x684];
510 u8 res_1008[0x2000-0x1008];
513 u8 res_2008[0x3000-0x2008];
522 u8 res_004[0x0c];
524 u8 res_014[0x0c];
526 u8 res_040[0x780]; /* 0x100 */
529 u8 res_804[0x1c];
531 u8 res_840[0x1c0];
532 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
533 u8 res_a04[0x1fc];
534 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
535 u8 res_c04[0x1c];
536 u32 plldgsr; /* 0xc20 DDR PLL General Status */
537 u8 res_c24[0x3dc];
557 #define SRDS_RSTCTL_RST 0x80000000
558 #define SRDS_RSTCTL_RSTDONE 0x40000000
559 #define SRDS_RSTCTL_RSTERR 0x20000000
560 #define SRDS_RSTCTL_SWRST 0x10000000
561 #define SRDS_RSTCTL_SDEN 0x00000020
562 #define SRDS_RSTCTL_SDRST_B 0x00000040
563 #define SRDS_RSTCTL_PLLRST_B 0x00000080
564 u32 pllcr0; /* PLL Control Register 0 */
565 #define SRDS_PLLCR0_POFF 0x80000000
566 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
567 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
568 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
569 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
570 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
571 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
572 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
573 #define SRDS_PLLCR0_PLL_LCK 0x00800000
574 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
575 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
576 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
577 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
578 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
579 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
580 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
582 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
583 u32 res_0c; /* 0x00c */
586 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */
587 u8 res_1c[0x20-0x1c];
589 u8 res_40[0x90-0x40];
590 u32 srdstcalcr; /* 0x90 TX Calibration Control */
591 u8 res_94[0xa0-0x94];
592 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
593 u8 res_a4[0xb0-0xa4];
594 u32 srdsgr0; /* 0xb0 General Register 0 */
595 u8 res_b4[0x100-0xb4];
597 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */
598 u8 res_104[0x120-0x104];
600 u8 res_180[0x200-0x180];
601 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */
602 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */
603 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */
604 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */
605 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */
606 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */
607 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */
608 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */
609 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */
610 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */
611 u32 srdspccra; /* 0x228 Protocol Configuration A */
612 u32 srdspccrb; /* 0x22c Protocol Configuration B */
613 u8 res_230[0x800-0x230];
615 u32 gcr0; /* 0x800 General Control Register 0 */
616 u32 gcr1; /* 0x804 General Control Register 1 */
617 u32 gcr2; /* 0x808 General Control Register 2 */
619 u32 recr0; /* 0x810 Receive Equalization Control */
621 u32 tecr0; /* 0x818 Transmit Equalization Control */
623 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
624 u8 res_824[0x83c-0x824];
627 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */
629 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */
630 u8 res_1004[0x1040-0x1004];
632 u8 res_10c0[0x1800-0x10c0];
634 u8 res_1800[0x1804-0x1800];
635 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */
636 u8 res_1808[0x180c-0x1808];
637 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */
639 u8 res_1840[0x1880-0x1840];
641 u8 res_1880[0x1884-0x1880];
642 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */
643 u8 res_1888[0x188c-0x1888];
644 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */
646 u8 res_18a0[0x1980-0x18a0];
648 u8 res_1980[0x1984-0x1980];
649 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */
650 u8 res_1988[0x198c-0x1988];
651 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */
653 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
667 #define SMMU_SCR0 (SMMU_BASE + 0x0)
668 #define SMMU_SCR1 (SMMU_BASE + 0x4)
669 #define SMMU_SCR2 (SMMU_BASE + 0x8)
670 #define SMMU_SACR (SMMU_BASE + 0x10)
671 #define SMMU_IDR0 (SMMU_BASE + 0x20)
672 #define SMMU_IDR1 (SMMU_BASE + 0x24)
674 #define SMMU_NSCR0 (SMMU_BASE + 0x400)
675 #define SMMU_NSCR2 (SMMU_BASE + 0x408)
676 #define SMMU_NSACR (SMMU_BASE + 0x410)
678 #define SCR0_CLIENTPD_MASK 0x00000001
679 #define SCR0_USFCFG_MASK 0x00000400
682 #define RCW_SRC_MASK (0xFF800000)
686 #define RCW_SRC_NAND_MASK (0x100)
687 #define RCW_SRC_NAND_VAL (0x100)
688 #define NAND_RESERVED_MASK (0xFC)
689 #define NAND_RESERVED_1 (0x0)
690 #define NAND_RESERVED_2 (0x80)
693 #define RCW_SRC_NOR_MASK (0x1F0)
694 #define NOR_8B_VAL (0x10)
695 #define NOR_16B_VAL (0x20)
696 #define SD_VAL (0x40)
697 #define QSPI_VAL1 (0x44)
698 #define QSPI_VAL2 (0x45)