Lines Matching +full:0 +full:x02200000
105 tcg_debug_assert(slot >= 0 && slot <= 1);
109 #define TCG_CT_CONST_ZERO 0x100
110 #define TCG_CT_CONST_S12 0x200
111 #define TCG_CT_CONST_N12 0x400
112 #define TCG_CT_CONST_M12 0x800
113 #define TCG_CT_CONST_J12 0x1000
114 #define TCG_CT_CONST_S5 0x2000
115 #define TCG_CT_CONST_CMP_VI 0x4000
117 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
119 #define ALL_DVECTOR_REG_GROUPS 0x5555555500000000
120 #define ALL_QVECTOR_REG_GROUPS 0x1111111100000000
128 #define V_OPIVV (0x0 << 12)
129 #define V_OPFVV (0x1 << 12)
130 #define V_OPMVV (0x2 << 12)
131 #define V_OPIVI (0x3 << 12)
132 #define V_OPIVX (0x4 << 12)
133 #define V_OPFVF (0x5 << 12)
134 #define V_OPMVX (0x6 << 12)
135 #define V_OPCFG (0x7 << 12)
137 /* NF <= 7 && NF >= 0 */
139 #define V_UNIT_STRIDE (0x0 << 20)
140 #define V_UNIT_STRIDE_WHOLE_REG (0x8 << 20)
143 VLMUL_M1 = 0, /* LMUL=1 */
154 OPC_ADD = 0x33,
155 OPC_ADDI = 0x13,
156 OPC_AND = 0x7033,
157 OPC_ANDI = 0x7013,
158 OPC_AUIPC = 0x17,
159 OPC_BEQ = 0x63,
160 OPC_BGE = 0x5063,
161 OPC_BGEU = 0x7063,
162 OPC_BLT = 0x4063,
163 OPC_BLTU = 0x6063,
164 OPC_BNE = 0x1063,
165 OPC_DIV = 0x2004033,
166 OPC_DIVU = 0x2005033,
167 OPC_JAL = 0x6f,
168 OPC_JALR = 0x67,
169 OPC_LB = 0x3,
170 OPC_LBU = 0x4003,
171 OPC_LD = 0x3003,
172 OPC_LH = 0x1003,
173 OPC_LHU = 0x5003,
174 OPC_LUI = 0x37,
175 OPC_LW = 0x2003,
176 OPC_LWU = 0x6003,
177 OPC_MUL = 0x2000033,
178 OPC_MULH = 0x2001033,
179 OPC_MULHSU = 0x2002033,
180 OPC_MULHU = 0x2003033,
181 OPC_OR = 0x6033,
182 OPC_ORI = 0x6013,
183 OPC_REM = 0x2006033,
184 OPC_REMU = 0x2007033,
185 OPC_SB = 0x23,
186 OPC_SD = 0x3023,
187 OPC_SH = 0x1023,
188 OPC_SLL = 0x1033,
189 OPC_SLLI = 0x1013,
190 OPC_SLT = 0x2033,
191 OPC_SLTI = 0x2013,
192 OPC_SLTIU = 0x3013,
193 OPC_SLTU = 0x3033,
194 OPC_SRA = 0x40005033,
195 OPC_SRAI = 0x40005013,
196 OPC_SRL = 0x5033,
197 OPC_SRLI = 0x5013,
198 OPC_SUB = 0x40000033,
199 OPC_SW = 0x2023,
200 OPC_XOR = 0x4033,
201 OPC_XORI = 0x4013,
203 OPC_ADDIW = 0x1b,
204 OPC_ADDW = 0x3b,
205 OPC_DIVUW = 0x200503b,
206 OPC_DIVW = 0x200403b,
207 OPC_MULW = 0x200003b,
208 OPC_REMUW = 0x200703b,
209 OPC_REMW = 0x200603b,
210 OPC_SLLIW = 0x101b,
211 OPC_SLLW = 0x103b,
212 OPC_SRAIW = 0x4000501b,
213 OPC_SRAW = 0x4000503b,
214 OPC_SRLIW = 0x501b,
215 OPC_SRLW = 0x503b,
216 OPC_SUBW = 0x4000003b,
218 OPC_FENCE = 0x0000000f,
219 OPC_NOP = OPC_ADDI, /* nop = addi r0,r0,0 */
222 OPC_ADD_UW = 0x0800003b,
225 OPC_ANDN = 0x40007033,
226 OPC_CLZ = 0x60001013,
227 OPC_CLZW = 0x6000101b,
228 OPC_CPOP = 0x60201013,
229 OPC_CPOPW = 0x6020101b,
230 OPC_CTZ = 0x60101013,
231 OPC_CTZW = 0x6010101b,
232 OPC_ORN = 0x40006033,
233 OPC_REV8 = 0x6b805013,
234 OPC_ROL = 0x60001033,
235 OPC_ROLW = 0x6000103b,
236 OPC_ROR = 0x60005033,
237 OPC_RORW = 0x6000503b,
238 OPC_RORI = 0x60005013,
239 OPC_RORIW = 0x6000501b,
240 OPC_SEXT_B = 0x60401013,
241 OPC_SEXT_H = 0x60501013,
242 OPC_XNOR = 0x40004033,
243 OPC_ZEXT_H = 0x0800403b,
246 OPC_CZERO_EQZ = 0x0e005033,
247 OPC_CZERO_NEZ = 0x0e007033,
250 OPC_VSETVLI = 0x57 | V_OPCFG,
251 OPC_VSETIVLI = 0xc0000057 | V_OPCFG,
252 OPC_VSETVL = 0x80000057 | V_OPCFG,
254 OPC_VLE8_V = 0x7 | V_UNIT_STRIDE,
255 OPC_VLE16_V = 0x5007 | V_UNIT_STRIDE,
256 OPC_VLE32_V = 0x6007 | V_UNIT_STRIDE,
257 OPC_VLE64_V = 0x7007 | V_UNIT_STRIDE,
258 OPC_VSE8_V = 0x27 | V_UNIT_STRIDE,
259 OPC_VSE16_V = 0x5027 | V_UNIT_STRIDE,
260 OPC_VSE32_V = 0x6027 | V_UNIT_STRIDE,
261 OPC_VSE64_V = 0x7027 | V_UNIT_STRIDE,
263 OPC_VL1RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(0),
264 OPC_VL2RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1),
265 OPC_VL4RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3),
266 OPC_VL8RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7),
268 OPC_VS1R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(0),
269 OPC_VS2R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1),
270 OPC_VS4R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3),
271 OPC_VS8R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7),
273 OPC_VMERGE_VIM = 0x5c000057 | V_OPIVI,
274 OPC_VMERGE_VVM = 0x5c000057 | V_OPIVV,
276 OPC_VADD_VV = 0x57 | V_OPIVV,
277 OPC_VADD_VI = 0x57 | V_OPIVI,
278 OPC_VSUB_VV = 0x8000057 | V_OPIVV,
279 OPC_VRSUB_VI = 0xc000057 | V_OPIVI,
280 OPC_VAND_VV = 0x24000057 | V_OPIVV,
281 OPC_VAND_VI = 0x24000057 | V_OPIVI,
282 OPC_VOR_VV = 0x28000057 | V_OPIVV,
283 OPC_VOR_VI = 0x28000057 | V_OPIVI,
284 OPC_VXOR_VV = 0x2c000057 | V_OPIVV,
285 OPC_VXOR_VI = 0x2c000057 | V_OPIVI,
287 OPC_VMUL_VV = 0x94000057 | V_OPMVV,
288 OPC_VSADD_VV = 0x84000057 | V_OPIVV,
289 OPC_VSADD_VI = 0x84000057 | V_OPIVI,
290 OPC_VSSUB_VV = 0x8c000057 | V_OPIVV,
291 OPC_VSSUB_VI = 0x8c000057 | V_OPIVI,
292 OPC_VSADDU_VV = 0x80000057 | V_OPIVV,
293 OPC_VSADDU_VI = 0x80000057 | V_OPIVI,
294 OPC_VSSUBU_VV = 0x88000057 | V_OPIVV,
295 OPC_VSSUBU_VI = 0x88000057 | V_OPIVI,
297 OPC_VMAX_VV = 0x1c000057 | V_OPIVV,
298 OPC_VMAX_VI = 0x1c000057 | V_OPIVI,
299 OPC_VMAXU_VV = 0x18000057 | V_OPIVV,
300 OPC_VMAXU_VI = 0x18000057 | V_OPIVI,
301 OPC_VMIN_VV = 0x14000057 | V_OPIVV,
302 OPC_VMIN_VI = 0x14000057 | V_OPIVI,
303 OPC_VMINU_VV = 0x10000057 | V_OPIVV,
304 OPC_VMINU_VI = 0x10000057 | V_OPIVI,
306 OPC_VMSEQ_VV = 0x60000057 | V_OPIVV,
307 OPC_VMSEQ_VI = 0x60000057 | V_OPIVI,
308 OPC_VMSEQ_VX = 0x60000057 | V_OPIVX,
309 OPC_VMSNE_VV = 0x64000057 | V_OPIVV,
310 OPC_VMSNE_VI = 0x64000057 | V_OPIVI,
311 OPC_VMSNE_VX = 0x64000057 | V_OPIVX,
313 OPC_VMSLTU_VV = 0x68000057 | V_OPIVV,
314 OPC_VMSLTU_VX = 0x68000057 | V_OPIVX,
315 OPC_VMSLT_VV = 0x6c000057 | V_OPIVV,
316 OPC_VMSLT_VX = 0x6c000057 | V_OPIVX,
317 OPC_VMSLEU_VV = 0x70000057 | V_OPIVV,
318 OPC_VMSLEU_VX = 0x70000057 | V_OPIVX,
319 OPC_VMSLE_VV = 0x74000057 | V_OPIVV,
320 OPC_VMSLE_VX = 0x74000057 | V_OPIVX,
322 OPC_VMSLEU_VI = 0x70000057 | V_OPIVI,
323 OPC_VMSLE_VI = 0x74000057 | V_OPIVI,
324 OPC_VMSGTU_VI = 0x78000057 | V_OPIVI,
325 OPC_VMSGTU_VX = 0x78000057 | V_OPIVX,
326 OPC_VMSGT_VI = 0x7c000057 | V_OPIVI,
327 OPC_VMSGT_VX = 0x7c000057 | V_OPIVX,
329 OPC_VSLL_VV = 0x94000057 | V_OPIVV,
330 OPC_VSLL_VI = 0x94000057 | V_OPIVI,
331 OPC_VSLL_VX = 0x94000057 | V_OPIVX,
332 OPC_VSRL_VV = 0xa0000057 | V_OPIVV,
333 OPC_VSRL_VI = 0xa0000057 | V_OPIVI,
334 OPC_VSRL_VX = 0xa0000057 | V_OPIVX,
335 OPC_VSRA_VV = 0xa4000057 | V_OPIVV,
336 OPC_VSRA_VI = 0xa4000057 | V_OPIVI,
337 OPC_VSRA_VX = 0xa4000057 | V_OPIVX,
339 OPC_VMV_V_V = 0x5e000057 | V_OPIVV,
340 OPC_VMV_V_I = 0x5e000057 | V_OPIVI,
341 OPC_VMV_V_X = 0x5e000057 | V_OPIVX,
343 OPC_VMVNR_V = 0x9e000057 | V_OPIVI,
374 [TCG_COND_LEU] = { OPC_VMSLEU_VI, 0, 15, false },
375 [TCG_COND_GTU] = { OPC_VMSGTU_VI, 0, 15, false },
387 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
395 * Sign extended from 12 bits: [-0x800, 0x7ff].
398 if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
402 * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
405 if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
409 * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
413 if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
417 * Inverse of sign extended from 12 bits: ~[-0x800, 0x7ff].
420 if ((ct & TCG_CT_CONST_J12) && ~val >= -0x800 && ~val <= 0x7ff) {
424 * Sign extended from 5 bits: [-0x10, 0x0f].
427 if ((ct & TCG_CT_CONST_S5) && val >= -0x10 && val <= 0x0f) {
438 return 0;
449 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
456 return (imm & 0xfff) << 20;
461 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
468 int32_t ret = 0;
470 ret |= (imm & 0xFE0) << 20;
471 ret |= (imm & 0x1F) << 7;
478 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
485 int32_t ret = 0;
487 ret |= (imm & 0x1000) << 19;
488 ret |= (imm & 0x7e0) << 20;
489 ret |= (imm & 0x1e) << 7;
490 ret |= (imm & 0x800) >> 4;
497 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
504 return imm & 0xfffff000;
509 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
516 int32_t ret = 0;
518 ret |= (imm & 0x0007fe) << (21 - 1);
519 ret |= (imm & 0x000800) << (20 - 11);
520 ret |= (imm & 0x0ff000) << (12 - 12);
521 ret |= (imm & 0x100000) << (31 - 20);
528 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
537 return opc | (rd & 0x1f) << 7 | (imm & 0x1f) << 15 |
538 (vs2 & 0x1f) << 20 | (vm << 25);
546 return opc | (d & 0x1f) << 7 | (s1 & 0x1f) << 15 |
547 (s2 & 0x1f) << 20 | (vm << 25);
561 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (vtype & 0x7ff) << 20;
567 return opc | (rd & 0x1f) << 7 | (uimm & 0x1f) << 15 | (vtype & 0x3ff) << 20;
613 for (i = 0; i < count; ++i) {
627 tcg_debug_assert((offset & 1) == 0);
628 if (offset == sextreg(offset, 0, 12)) {
641 tcg_debug_assert((offset & 1) == 0);
642 if (offset == sextreg(offset, 0, 20)) {
654 int32_t lo = sextreg(offset, 0, 12);
658 src_rw[0] |= encode_uimm20(hi);
669 tcg_debug_assert(addend == 0);
688 * and vm=0 (vm = false) means vector masking ENABLED.
779 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
786 int nf = 1 << MAX(lmul, 0);
806 lo = sextreg(val, 0, 12);
815 if (lo != 0) {
823 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
824 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
833 if (tmp == sextreg(tmp, 0, 20)) {
850 } else if (tmp == sextreg(tmp, 0, 12)) {
857 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0);
858 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
859 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
876 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
902 tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0);
912 tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0);
921 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
944 intptr_t imm12 = sextreg(offset, 0, 12);
950 imm12 = sextreg(diff, 0, 12);
990 if (offset == sextreg(offset, 0, 12)) {
998 tcg_out32(s, encode_v(opc, data, addr, 0, true));
1082 if (val == 0) {
1102 if (cbl && cbh && bh == -1 && bl != 0) {
1104 bh = 0;
1112 } else if (bh != 0 || ah == rl) {
1118 /* Note that tcg optimization should eliminate the bl == 0 case. */
1139 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
1154 tcg_out_opc_vx(s, OPC_VMV_V_X, dst, 0, src);
1172 if (arg == 0 || arg == -1) {
1177 tcg_out_opc_vi(s, OPC_VMV_V_I, dst, 0, arg);
1205 tcg_debug_assert(op != 0);
1213 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0);
1214 tcg_out_opc_branch(s, op, arg1, arg2, 0);
1224 int flags = 0;
1246 * is constrained to signed 12-bit, and 0x800 is representable in the
1260 tcg_debug_assert(arg2 <= 0x7ff);
1261 if (++arg2 == 0x800) {
1284 } else if (arg2 == 0) {
1328 /* Intermediate result is zero/non-zero: test != 0. */
1332 /* Intermediate result is zero/non-zero: test == 0. */
1347 /* For LT/GE comparison against 0, replicate the sign bit. */
1348 if (c2 && arg2 == 0) {
1365 /* If intermediate result is zero/non-zero: test != 0. */
1371 /* Produce the 0/-1 result. */
1383 if (val1 == 0) {
1392 if (val2 == 0) {
1433 tcg_debug_assert(op != 0);
1443 tcg_out_opc_imm(s, OPC_ADDI, ret, val, 0);
1484 if (!(cpuinfo & CPUINFO_ZICOND) && (!c_cmp2 || cmp2 == 0)) {
1509 tcg_out_opc_imm(s, insn, ret, src1, 0);
1517 tcg_out_movcond(s, TCG_COND_EQ, ret, src1, 0, true,
1553 tcg_out_opc_vi(s, OPC_VMV_V_I, ret, 0, val2);
1588 tcg_debug_assert((offset & 1) == 0);
1589 if (offset == sextreg(offset, 0, 20)) {
1594 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
1595 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
1600 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
1618 insn |= 0x02200000;
1621 insn |= 0x01200000;
1624 insn |= 0x02100000;
1627 insn |= 0x02200000;
1638 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
1658 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1676 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1748 if (compare_mask == sextreg(compare_mask, 0, 12)) {
1764 ldst->label_ptr[0] = s->code_ptr;
1765 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
1791 tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12));
1794 ldst->label_ptr[0] = s->code_ptr;
1795 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
1798 if (guest_base != 0) {
1826 tcg_debug_assert((opc & MO_BSWAP) == 0);
1830 tcg_out_opc_imm(s, OPC_LBU, val, base, 0);
1833 tcg_out_opc_imm(s, OPC_LB, val, base, 0);
1836 tcg_out_opc_imm(s, OPC_LHU, val, base, 0);
1839 tcg_out_opc_imm(s, OPC_LH, val, base, 0);
1843 tcg_out_opc_imm(s, OPC_LWU, val, base, 0);
1848 tcg_out_opc_imm(s, OPC_LW, val, base, 0);
1851 tcg_out_opc_imm(s, OPC_LD, val, base, 0);
1878 tcg_debug_assert((opc & MO_BSWAP) == 0);
1882 tcg_out_opc_store(s, OPC_SB, base, val, 0);
1885 tcg_out_opc_store(s, OPC_SH, base, val, 0);
1888 tcg_out_opc_store(s, OPC_SW, base, val, 0);
1891 tcg_out_opc_store(s, OPC_SD, base, val, 0);
1919 if (a0 == 0) {
1936 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1948 if (offset == sextreg(offset, 0, 20)) {
1961 TCGArg a0 = args[0];
1968 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1972 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
1973 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
2150 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f);
2157 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f);
2165 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f);
2172 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f);
2180 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f);
2187 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f);
2195 tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f);
2202 tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f);
2210 tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f);
2217 tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f);
2224 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
2227 a2 = 0;
2230 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
2239 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
2248 tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0);
2251 tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0);
2372 a0 = args[0];
2417 tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0);
2507 tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0);
2514 tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0);
2521 -1, true, 0, true);
2576 return 0;
2794 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
2805 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2816 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2817 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
2819 /* Return path for goto_ptr. Set return value to 0 */
2825 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2831 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
2844 asm(".insn r 0x57, 7, 0x40, %0, zero, %1" : "=r"(tmp) : "r"(vtype));
2845 return tmp != 0;
2869 if (lmul < 0 && (lmul < -3 || !vtype_check(vtype))) {
2877 /* rd != 0 and rs1 == 0 uses vlmax */
2899 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2900 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2916 s->reserved_regs = 0;
2965 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2973 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2977 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
2978 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
2979 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
2980 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
2981 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
2982 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
2983 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
2984 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
2985 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
2986 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
2987 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
2988 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */