183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 223608e23SJason Liu /* 323608e23SJason Liu * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 423608e23SJason Liu */ 523608e23SJason Liu 623608e23SJason Liu #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ 723608e23SJason Liu #define __ASM_ARCH_MX6_IMX_REGS_H__ 823608e23SJason Liu 98e99ecd7SBenoît Thébaudeau #define ARCH_MXC 108e99ecd7SBenoît Thébaudeau 1123608e23SJason Liu #define ROMCP_ARB_BASE_ADDR 0x00000000 1223608e23SJason Liu #define ROMCP_ARB_END_ADDR 0x000FFFFF 1325b4aa14SFabio Estevam 1425b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 1525b4aa14SFabio Estevam #define GPU_2D_ARB_BASE_ADDR 0x02200000 1625b4aa14SFabio Estevam #define GPU_2D_ARB_END_ADDR 0x02203FFF 1725b4aa14SFabio Estevam #define OPENVG_ARB_BASE_ADDR 0x02204000 1825b4aa14SFabio Estevam #define OPENVG_ARB_END_ADDR 0x02207FFF 19290e7cfdSFabio Estevam #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 2005d54b82SFabio Estevam #define CAAM_ARB_BASE_ADDR 0x00100000 2105d54b82SFabio Estevam #define CAAM_ARB_END_ADDR 0x00107FFF 2205d54b82SFabio Estevam #define GPU_ARB_BASE_ADDR 0x01800000 2305d54b82SFabio Estevam #define GPU_ARB_END_ADDR 0x01803FFF 2405d54b82SFabio Estevam #define APBH_DMA_ARB_BASE_ADDR 0x01804000 2505d54b82SFabio Estevam #define APBH_DMA_ARB_END_ADDR 0x0180BFFF 2605d54b82SFabio Estevam #define M4_BOOTROM_BASE_ADDR 0x007F8000 2705d54b82SFabio Estevam 2856612bf6SPeng Fan #elif !defined(CONFIG_MX6SLL) 2923608e23SJason Liu #define CAAM_ARB_BASE_ADDR 0x00100000 3023608e23SJason Liu #define CAAM_ARB_END_ADDR 0x00103FFF 3123608e23SJason Liu #define APBH_DMA_ARB_BASE_ADDR 0x00110000 3223608e23SJason Liu #define APBH_DMA_ARB_END_ADDR 0x00117FFF 3323608e23SJason Liu #define HDMI_ARB_BASE_ADDR 0x00120000 3423608e23SJason Liu #define HDMI_ARB_END_ADDR 0x00128FFF 3523608e23SJason Liu #define GPU_3D_ARB_BASE_ADDR 0x00130000 3623608e23SJason Liu #define GPU_3D_ARB_END_ADDR 0x00133FFF 3723608e23SJason Liu #define GPU_2D_ARB_BASE_ADDR 0x00134000 3823608e23SJason Liu #define GPU_2D_ARB_END_ADDR 0x00137FFF 3923608e23SJason Liu #define DTCP_ARB_BASE_ADDR 0x00138000 4023608e23SJason Liu #define DTCP_ARB_END_ADDR 0x0013BFFF 4125b4aa14SFabio Estevam #endif /* CONFIG_MX6SL */ 4299193e30SStefan Roese 4399193e30SStefan Roese #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 4499193e30SStefan Roese #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 4599193e30SStefan Roese #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 4699193e30SStefan Roese 4723608e23SJason Liu /* GPV - PL301 configuration ports */ 48290e7cfdSFabio Estevam #if (defined(CONFIG_MX6SX) || \ 49290e7cfdSFabio Estevam defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ 5056612bf6SPeng Fan defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)) 5125b4aa14SFabio Estevam #define GPV2_BASE_ADDR 0x00D00000 5205d54b82SFabio Estevam #define GPV3_BASE_ADDR 0x00E00000 5305d54b82SFabio Estevam #define GPV4_BASE_ADDR 0x00F00000 5405d54b82SFabio Estevam #define GPV5_BASE_ADDR 0x01000000 5505d54b82SFabio Estevam #define GPV6_BASE_ADDR 0x01100000 5605d54b82SFabio Estevam #define PCIE_ARB_BASE_ADDR 0x08000000 5705d54b82SFabio Estevam #define PCIE_ARB_END_ADDR 0x08FFFFFF 5805d54b82SFabio Estevam 5905d54b82SFabio Estevam #else 6056612bf6SPeng Fan #define GPV2_BASE_ADDR 0x00200000 6123608e23SJason Liu #define GPV3_BASE_ADDR 0x00300000 6223608e23SJason Liu #define GPV4_BASE_ADDR 0x00800000 6305d54b82SFabio Estevam #define PCIE_ARB_BASE_ADDR 0x01000000 6405d54b82SFabio Estevam #define PCIE_ARB_END_ADDR 0x01FFFFFF 6505d54b82SFabio Estevam #endif 6605d54b82SFabio Estevam 6723608e23SJason Liu #define IRAM_BASE_ADDR 0x00900000 6823608e23SJason Liu #define SCU_BASE_ADDR 0x00A00000 6923608e23SJason Liu #define IC_INTERFACES_BASE_ADDR 0x00A00100 7023608e23SJason Liu #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 7123608e23SJason Liu #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 7223608e23SJason Liu #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 736d73c234SFabio Estevam #define L2_PL310_BASE 0x00A02000 7423608e23SJason Liu #define GPV0_BASE_ADDR 0x00B00000 7523608e23SJason Liu #define GPV1_BASE_ADDR 0x00C00000 7623608e23SJason Liu 7723608e23SJason Liu #define AIPS1_ARB_BASE_ADDR 0x02000000 7823608e23SJason Liu #define AIPS1_ARB_END_ADDR 0x020FFFFF 7923608e23SJason Liu #define AIPS2_ARB_BASE_ADDR 0x02100000 8023608e23SJason Liu #define AIPS2_ARB_END_ADDR 0x021FFFFF 81bc32fc69SPeng Fan /* AIPS3 only on i.MX6SX */ 82e8cdeefcSYe.Li #define AIPS3_ARB_BASE_ADDR 0x02200000 83e8cdeefcSYe.Li #define AIPS3_ARB_END_ADDR 0x022FFFFF 84bc32fc69SPeng Fan #ifdef CONFIG_MX6SX 8505d54b82SFabio Estevam #define WEIM_ARB_BASE_ADDR 0x50000000 8605d54b82SFabio Estevam #define WEIM_ARB_END_ADDR 0x57FFFFFF 87b93ab2eeSPeng Fan #define QSPI0_AMBA_BASE 0x60000000 88b93ab2eeSPeng Fan #define QSPI0_AMBA_END 0x6FFFFFFF 89b93ab2eeSPeng Fan #define QSPI1_AMBA_BASE 0x70000000 90b93ab2eeSPeng Fan #define QSPI1_AMBA_END 0x7FFFFFFF 91290e7cfdSFabio Estevam #elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 92bc32fc69SPeng Fan #define WEIM_ARB_BASE_ADDR 0x50000000 93bc32fc69SPeng Fan #define WEIM_ARB_END_ADDR 0x57FFFFFF 94bc32fc69SPeng Fan #define QSPI0_AMBA_BASE 0x60000000 95bc32fc69SPeng Fan #define QSPI0_AMBA_END 0x6FFFFFFF 9656612bf6SPeng Fan #elif !defined(CONFIG_MX6SLL) 9723608e23SJason Liu #define SATA_ARB_BASE_ADDR 0x02200000 9823608e23SJason Liu #define SATA_ARB_END_ADDR 0x02203FFF 9923608e23SJason Liu #define OPENVG_ARB_BASE_ADDR 0x02204000 10023608e23SJason Liu #define OPENVG_ARB_END_ADDR 0x02207FFF 10123608e23SJason Liu #define HSI_ARB_BASE_ADDR 0x02208000 10223608e23SJason Liu #define HSI_ARB_END_ADDR 0x0220BFFF 10323608e23SJason Liu #define IPU1_ARB_BASE_ADDR 0x02400000 10423608e23SJason Liu #define IPU1_ARB_END_ADDR 0x027FFFFF 10523608e23SJason Liu #define IPU2_ARB_BASE_ADDR 0x02800000 10623608e23SJason Liu #define IPU2_ARB_END_ADDR 0x02BFFFFF 10723608e23SJason Liu #define WEIM_ARB_BASE_ADDR 0x08000000 10823608e23SJason Liu #define WEIM_ARB_END_ADDR 0x0FFFFFFF 10905d54b82SFabio Estevam #endif 11023608e23SJason Liu 11156612bf6SPeng Fan #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ 112290e7cfdSFabio Estevam defined(CONFIG_MX6SX) || \ 113290e7cfdSFabio Estevam defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 11425b4aa14SFabio Estevam #define MMDC0_ARB_BASE_ADDR 0x80000000 11525b4aa14SFabio Estevam #define MMDC0_ARB_END_ADDR 0xFFFFFFFF 11625b4aa14SFabio Estevam #define MMDC1_ARB_BASE_ADDR 0xC0000000 11725b4aa14SFabio Estevam #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 11825b4aa14SFabio Estevam #else 11923608e23SJason Liu #define MMDC0_ARB_BASE_ADDR 0x10000000 12023608e23SJason Liu #define MMDC0_ARB_END_ADDR 0x7FFFFFFF 12123608e23SJason Liu #define MMDC1_ARB_BASE_ADDR 0x80000000 12223608e23SJason Liu #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 12325b4aa14SFabio Estevam #endif 12423608e23SJason Liu 12505d54b82SFabio Estevam #ifndef CONFIG_MX6SX 12605d4df1dSFabio Estevam #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR 12705d4df1dSFabio Estevam #define IPU_SOC_OFFSET 0x00200000 12805d54b82SFabio Estevam #endif 12905d4df1dSFabio Estevam 13023608e23SJason Liu /* Defines for Blocks connected via AIPS (SkyBlue) */ 13123608e23SJason Liu #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 13223608e23SJason Liu #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 13350a082a8SAdrian Alonso #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR 13423608e23SJason Liu #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 13523608e23SJason Liu #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 13650a082a8SAdrian Alonso #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR 13723608e23SJason Liu 13823608e23SJason Liu #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) 13923608e23SJason Liu #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) 14023608e23SJason Liu #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) 14123608e23SJason Liu #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) 14223608e23SJason Liu #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) 14356612bf6SPeng Fan 14456612bf6SPeng Fan #define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 14556612bf6SPeng Fan #define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 14656612bf6SPeng Fan #define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 14756612bf6SPeng Fan #define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 14856612bf6SPeng Fan #define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 14956612bf6SPeng Fan #define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 15056612bf6SPeng Fan #define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 15156612bf6SPeng Fan #define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 15256612bf6SPeng Fan #define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) 15356612bf6SPeng Fan 15405d54b82SFabio Estevam #ifndef CONFIG_MX6SX 15523608e23SJason Liu #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) 15605d54b82SFabio Estevam #endif 15756612bf6SPeng Fan #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) 15823608e23SJason Liu #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) 15923608e23SJason Liu #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) 16051560f0bSStefan Roese #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) 16123608e23SJason Liu #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) 16223608e23SJason Liu #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) 16323608e23SJason Liu #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) 16423608e23SJason Liu #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) 16525b4aa14SFabio Estevam 16605d54b82SFabio Estevam #ifndef CONFIG_MX6SX 16723608e23SJason Liu #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) 16823608e23SJason Liu #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) 16905d54b82SFabio Estevam #endif 17023608e23SJason Liu #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) 17123608e23SJason Liu 17223608e23SJason Liu #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) 17323608e23SJason Liu #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) 17423608e23SJason Liu #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) 17523608e23SJason Liu #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) 17623608e23SJason Liu #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) 17723608e23SJason Liu #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) 17823608e23SJason Liu #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 17956612bf6SPeng Fan /* QOSC on i.MX6SLL */ 18056612bf6SPeng Fan #define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) 18123608e23SJason Liu #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) 18223608e23SJason Liu #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) 18323608e23SJason Liu #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) 18423608e23SJason Liu #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) 18523608e23SJason Liu #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) 18623608e23SJason Liu #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) 18707e1c0aeSPeng Fan #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 18823608e23SJason Liu #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) 18923608e23SJason Liu #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 19023608e23SJason Liu #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) 19123608e23SJason Liu #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) 19223608e23SJason Liu #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) 1933f467529SWolfgang Grandegger #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) 1943f467529SWolfgang Grandegger #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) 1953f467529SWolfgang Grandegger #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) 19623608e23SJason Liu #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) 19723608e23SJason Liu #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) 19823608e23SJason Liu #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) 19923608e23SJason Liu #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) 20023608e23SJason Liu #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) 20123608e23SJason Liu #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) 20223608e23SJason Liu #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) 20356612bf6SPeng Fan #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 20456612bf6SPeng Fan #ifdef CONFIG_MX6SLL 20556612bf6SPeng Fan #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 20656612bf6SPeng Fan #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 20756612bf6SPeng Fan #define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 20856612bf6SPeng Fan #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 20956612bf6SPeng Fan #define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 21056612bf6SPeng Fan #elif defined(CONFIG_MX6SL) 21125b4aa14SFabio Estevam #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 21225b4aa14SFabio Estevam #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 21325b4aa14SFabio Estevam #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 21456612bf6SPeng Fan #elif defined(CONFIG_MX6SX) 21505d54b82SFabio Estevam #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 21605d54b82SFabio Estevam #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 21705d54b82SFabio Estevam #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) 21805d54b82SFabio Estevam #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) 21905d54b82SFabio Estevam #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 22005d54b82SFabio Estevam #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) 22125b4aa14SFabio Estevam #else 22223608e23SJason Liu #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) 22323608e23SJason Liu #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) 22423608e23SJason Liu #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) 22525b4aa14SFabio Estevam #endif 22623608e23SJason Liu 22756612bf6SPeng Fan #define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 22856612bf6SPeng Fan #define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) 22956612bf6SPeng Fan 23023608e23SJason Liu #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) 23123608e23SJason Liu #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) 23250a082a8SAdrian Alonso #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) 23350a082a8SAdrian Alonso #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) 2347adafc14SAnatolij Gustschin #if defined(CONFIG_MX6UL) 2357adafc14SAnatolij Gustschin #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 2367adafc14SAnatolij Gustschin #else 23723608e23SJason Liu #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) 2387adafc14SAnatolij Gustschin #endif 23923608e23SJason Liu #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) 2400200020bSRaul Cardenas 241e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_SEC_OFFSET 0 242e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ 243e99d7193SAlex Porosanu CONFIG_SYS_FSL_SEC_OFFSET) 244e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 245e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ 246e99d7193SAlex Porosanu CONFIG_SYS_FSL_JR0_OFFSET) 247e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 2480200020bSRaul Cardenas 2495546ad07SYe.Li #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) 2505546ad07SYe.Li #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) 25125b4aa14SFabio Estevam 25223608e23SJason Liu #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) 25325b4aa14SFabio Estevam #ifdef CONFIG_MX6SL 25425b4aa14SFabio Estevam #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 25525b4aa14SFabio Estevam #else 25623608e23SJason Liu #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) 25725b4aa14SFabio Estevam #endif 25825b4aa14SFabio Estevam 25923608e23SJason Liu #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) 26023608e23SJason Liu #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) 26123608e23SJason Liu #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) 26223608e23SJason Liu #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) 26323608e23SJason Liu #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) 26423608e23SJason Liu #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) 26523608e23SJason Liu #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) 26623608e23SJason Liu #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) 26723608e23SJason Liu #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) 26856612bf6SPeng Fan /* i.MX6SL/SLL */ 26925b4aa14SFabio Estevam #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 270290e7cfdSFabio Estevam #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 271bc32fc69SPeng Fan #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) 27225b4aa14SFabio Estevam #else 273bc32fc69SPeng Fan /* i.MX6SX */ 274bc32fc69SPeng Fan #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 27525b4aa14SFabio Estevam #endif 276bc32fc69SPeng Fan /* i.MX6DQ/SDL */ 277bc32fc69SPeng Fan #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) 27825b4aa14SFabio Estevam 27923608e23SJason Liu #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) 28023608e23SJason Liu #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) 28123608e23SJason Liu #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) 28256612bf6SPeng Fan #ifdef CONFIG_MX6SLL 28356612bf6SPeng Fan #define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 28456612bf6SPeng Fan #define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 28556612bf6SPeng Fan #endif 28623608e23SJason Liu #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) 28723608e23SJason Liu #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 288b1ce1fb5SPeng Fan #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 289bdfb2d4dSPeng Fan #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) 29005d54b82SFabio Estevam #ifdef CONFIG_MX6SX 29105d54b82SFabio Estevam #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 29205d54b82SFabio Estevam #else 29323608e23SJason Liu #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) 29405d54b82SFabio Estevam #endif 29523608e23SJason Liu #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) 296290e7cfdSFabio Estevam #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 29746718353SStefan Agner #define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 298bc32fc69SPeng Fan #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 2999999fc09SFabio Estevam #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 300bc32fc69SPeng Fan #elif defined(CONFIG_MX6SX) 30105d54b82SFabio Estevam #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 30223608e23SJason Liu #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) 30305d54b82SFabio Estevam #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 304b93ab2eeSPeng Fan #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 305b93ab2eeSPeng Fan #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 30605d54b82SFabio Estevam #else 307bc32fc69SPeng Fan #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) 30823608e23SJason Liu #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) 30923608e23SJason Liu #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) 31023608e23SJason Liu #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 31105d54b82SFabio Estevam #endif 312bc32fc69SPeng Fan #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) 31323608e23SJason Liu #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) 31423608e23SJason Liu #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) 31523608e23SJason Liu #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) 31623608e23SJason Liu #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) 31721a26940SHeiko Schocher #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 31823608e23SJason Liu #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) 31923608e23SJason Liu #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 32056612bf6SPeng Fan /* i.MX6SLL */ 32156612bf6SPeng Fan #define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) 32223608e23SJason Liu 32305d54b82SFabio Estevam #ifdef CONFIG_MX6SX 32405d54b82SFabio Estevam #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) 32505d54b82SFabio Estevam #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) 32605d54b82SFabio Estevam #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) 32705d54b82SFabio Estevam #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) 32805d54b82SFabio Estevam #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) 32905d54b82SFabio Estevam #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) 33005d54b82SFabio Estevam #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) 33105d54b82SFabio Estevam #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) 33205d54b82SFabio Estevam #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) 33305d54b82SFabio Estevam #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 33405d54b82SFabio Estevam #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 33505d54b82SFabio Estevam #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 33605d54b82SFabio Estevam #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 33705d54b82SFabio Estevam #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 33805d54b82SFabio Estevam #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 33905d54b82SFabio Estevam #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) 34005d54b82SFabio Estevam #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) 34105d54b82SFabio Estevam #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) 34205d54b82SFabio Estevam #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) 34305d54b82SFabio Estevam #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) 34405d54b82SFabio Estevam #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) 34505d54b82SFabio Estevam #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) 346290e7cfdSFabio Estevam #elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 347bdfb2d4dSPeng Fan #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) 348bdfb2d4dSPeng Fan #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) 349bdfb2d4dSPeng Fan #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) 350bdfb2d4dSPeng Fan #define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 351bdfb2d4dSPeng Fan #define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) 352bdfb2d4dSPeng Fan #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) 353bdfb2d4dSPeng Fan #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) 35405d54b82SFabio Estevam #endif 355e1f0715fSFabio Estevam 356e1f0715fSFabio Estevam #define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000) 357e1f0715fSFabio Estevam 358b1ce1fb5SPeng Fan /* Only for i.MX6SX */ 359b1ce1fb5SPeng Fan #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) 360b1ce1fb5SPeng Fan #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) 361bc32fc69SPeng Fan #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) 362bc32fc69SPeng Fan 363290e7cfdSFabio Estevam #if !(defined(CONFIG_MX6SX) || \ 364290e7cfdSFabio Estevam defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ 36556612bf6SPeng Fan defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)) 36623608e23SJason Liu #define IRAM_SIZE 0x00040000 36705d54b82SFabio Estevam #else 36805d54b82SFabio Estevam #define IRAM_SIZE 0x00020000 36905d54b82SFabio Estevam #endif 37028774cbaSTroy Kisky #define FEC_QUIRK_ENET_MAC 37123608e23SJason Liu 372552a848eSStefano Babic #include <asm/mach-imx/regs-lcdif.h> 37323608e23SJason Liu #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 37423608e23SJason Liu #include <asm/types.h> 37523608e23SJason Liu 376b1ce1fb5SPeng Fan /* only for i.MX6SX/UL */ 37723ecca2cSFabio Estevam #define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \ 3780c890879SPeng Fan MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) 37956612bf6SPeng Fan #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \ 38056612bf6SPeng Fan MX6SLL_LCDIF_BASE_ADDR : \ 38156612bf6SPeng Fan (is_cpu_type(MXC_CPU_MX6SL)) ? \ 38256612bf6SPeng Fan MX6SL_LCDIF_BASE_ADDR : \ 38356612bf6SPeng Fan ((is_cpu_type(MXC_CPU_MX6UL)) ? \ 384bdfb2d4dSPeng Fan MX6UL_LCDIF1_BASE_ADDR : \ 385bdfb2d4dSPeng Fan ((is_mx6ull()) ? \ 38656612bf6SPeng Fan MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) 387b1ce1fb5SPeng Fan 388b1ce1fb5SPeng Fan 389be252b65SFabio Estevam extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 39023608e23SJason Liu 391a76df709SGabriel Huau #define SRC_SCR_CORE_1_RESET_OFFSET 14 392a76df709SGabriel Huau #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET) 393a76df709SGabriel Huau #define SRC_SCR_CORE_2_RESET_OFFSET 15 394a76df709SGabriel Huau #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET) 395a76df709SGabriel Huau #define SRC_SCR_CORE_3_RESET_OFFSET 16 396a76df709SGabriel Huau #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET) 397a76df709SGabriel Huau #define SRC_SCR_CORE_1_ENABLE_OFFSET 22 398a76df709SGabriel Huau #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET) 399a76df709SGabriel Huau #define SRC_SCR_CORE_2_ENABLE_OFFSET 23 400a76df709SGabriel Huau #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET) 401a76df709SGabriel Huau #define SRC_SCR_CORE_3_ENABLE_OFFSET 24 402a76df709SGabriel Huau #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) 403a76df709SGabriel Huau 404613e0106SPeng Fan struct rdc_regs { 405613e0106SPeng Fan u32 vir; /* Version information */ 406613e0106SPeng Fan u32 reserved1[8]; 407613e0106SPeng Fan u32 stat; /* Status */ 408613e0106SPeng Fan u32 intctrl; /* Interrupt and Control */ 409613e0106SPeng Fan u32 intstat; /* Interrupt Status */ 410613e0106SPeng Fan u32 reserved2[116]; 411613e0106SPeng Fan u32 mda[32]; /* Master Domain Assignment */ 412613e0106SPeng Fan u32 reserved3[96]; 413613e0106SPeng Fan u32 pdap[104]; /* Peripheral Domain Access Permissions */ 414613e0106SPeng Fan u32 reserved4[88]; 415613e0106SPeng Fan struct { 416613e0106SPeng Fan u32 mrsa; /* Memory Region Start Address */ 417613e0106SPeng Fan u32 mrea; /* Memory Region End Address */ 418613e0106SPeng Fan u32 mrc; /* Memory Region Control */ 419613e0106SPeng Fan u32 mrvs; /* Memory Region Violation Status */ 420613e0106SPeng Fan } mem_region[55]; 421613e0106SPeng Fan }; 422613e0106SPeng Fan 423613e0106SPeng Fan struct rdc_sema_regs { 424613e0106SPeng Fan u8 gate[64]; /* Gate */ 425613e0106SPeng Fan u16 rstgt; /* Reset Gate */ 426613e0106SPeng Fan }; 427613e0106SPeng Fan 428573960acSFabio Estevam /* WEIM registers */ 429573960acSFabio Estevam struct weim { 430573960acSFabio Estevam u32 cs0gcr1; 431573960acSFabio Estevam u32 cs0gcr2; 432573960acSFabio Estevam u32 cs0rcr1; 433573960acSFabio Estevam u32 cs0rcr2; 434573960acSFabio Estevam u32 cs0wcr1; 435573960acSFabio Estevam u32 cs0wcr2; 436573960acSFabio Estevam 437573960acSFabio Estevam u32 cs1gcr1; 438573960acSFabio Estevam u32 cs1gcr2; 439573960acSFabio Estevam u32 cs1rcr1; 440573960acSFabio Estevam u32 cs1rcr2; 441573960acSFabio Estevam u32 cs1wcr1; 442573960acSFabio Estevam u32 cs1wcr2; 443573960acSFabio Estevam 444573960acSFabio Estevam u32 cs2gcr1; 445573960acSFabio Estevam u32 cs2gcr2; 446573960acSFabio Estevam u32 cs2rcr1; 447573960acSFabio Estevam u32 cs2rcr2; 448573960acSFabio Estevam u32 cs2wcr1; 449573960acSFabio Estevam u32 cs2wcr2; 450573960acSFabio Estevam 451573960acSFabio Estevam u32 cs3gcr1; 452573960acSFabio Estevam u32 cs3gcr2; 453573960acSFabio Estevam u32 cs3rcr1; 454573960acSFabio Estevam u32 cs3rcr2; 455573960acSFabio Estevam u32 cs3wcr1; 456573960acSFabio Estevam u32 cs3wcr2; 457573960acSFabio Estevam 458573960acSFabio Estevam u32 unused[12]; 459573960acSFabio Estevam 460573960acSFabio Estevam u32 wcr; 461573960acSFabio Estevam u32 wiar; 462573960acSFabio Estevam u32 ear; 463573960acSFabio Estevam }; 464573960acSFabio Estevam 46523608e23SJason Liu /* System Reset Controller (SRC) */ 46623608e23SJason Liu struct src { 46723608e23SJason Liu u32 scr; 46823608e23SJason Liu u32 sbmr1; 46923608e23SJason Liu u32 srsr; 47023608e23SJason Liu u32 reserved1[2]; 47123608e23SJason Liu u32 sisr; 47223608e23SJason Liu u32 simr; 47323608e23SJason Liu u32 sbmr2; 47423608e23SJason Liu u32 gpr1; 47523608e23SJason Liu u32 gpr2; 47623608e23SJason Liu u32 gpr3; 47723608e23SJason Liu u32 gpr4; 47823608e23SJason Liu u32 gpr5; 47923608e23SJason Liu u32 gpr6; 48023608e23SJason Liu u32 gpr7; 48123608e23SJason Liu u32 gpr8; 48223608e23SJason Liu u32 gpr9; 48323608e23SJason Liu u32 gpr10; 48423608e23SJason Liu }; 48523608e23SJason Liu 4867b54f5a8SJagan Teki #define src_base ((struct src *)SRC_BASE_ADDR) 4877b54f5a8SJagan Teki 4888cf22313SPeng Fan #define SRC_M4_REG_OFFSET 0 4898cf22313SPeng Fan #define SRC_M4_ENABLE_OFFSET 22 4908cf22313SPeng Fan #define SRC_M4_ENABLE_MASK BIT(22) 4918cf22313SPeng Fan #define SRC_M4C_NON_SCLR_RST_OFFSET 4 4928cf22313SPeng Fan #define SRC_M4C_NON_SCLR_RST_MASK BIT(4) 4930623d375SPeng Fan 4943a217731SFabio Estevam /* GPR1 bitfields */ 495d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) 496d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) 497d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) 498d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) 499d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) 500d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_DPI_OFF BIT(24) 501d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) 5023a217731SFabio Estevam #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 5033a217731SFabio Estevam #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) 504d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) 505d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) 506d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) 507d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) 508d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) 509d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_USB_EXP_MODE BIT(15) 510d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_PCIE_INT BIT(14) 5114a4d3a7dSHeiko Schocher #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 5124a4d3a7dSHeiko Schocher #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) 513d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_GINT BIT(12) 514d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) 515d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) 516d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) 517d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) 518d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ACT_CS3 BIT(9) 519d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) 520d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ACT_CS2 BIT(6) 521d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) 522d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ACT_CS1 BIT(3) 523d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS0_OFFSET (1) 524d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) 525d62f2f8cSHeiko Schocher #define IOMUXC_GPR1_ACT_CS0 BIT(0) 5263a217731SFabio Estevam 527a83e1b7bSEric Nelson /* GPR3 bitfields */ 528a83e1b7bSEric Nelson #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 529a83e1b7bSEric Nelson #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) 530a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 531a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) 532a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 533a83e1b7bSEric Nelson #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) 534a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 535a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) 536a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 537a83e1b7bSEric Nelson #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) 538a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 539a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) 540a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 541a83e1b7bSEric Nelson #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) 542a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 543a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) 544a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 545a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) 546a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 547a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) 548a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 549a83e1b7bSEric Nelson #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) 550a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 551a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) 552a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 553a83e1b7bSEric Nelson #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) 554a83e1b7bSEric Nelson #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 555a83e1b7bSEric Nelson #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) 556a83e1b7bSEric Nelson 557a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 558a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 559a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 560a83e1b7bSEric Nelson #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 561a83e1b7bSEric Nelson 562a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 563a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) 564a83e1b7bSEric Nelson 565a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 566a83e1b7bSEric Nelson #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) 567a83e1b7bSEric Nelson 568a83e1b7bSEric Nelson #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 569a83e1b7bSEric Nelson #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) 570a83e1b7bSEric Nelson 571a83e1b7bSEric Nelson #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 572a83e1b7bSEric Nelson #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) 573a83e1b7bSEric Nelson 574d62f2f8cSHeiko Schocher /* gpr12 bitfields */ 575d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) 576d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) 577d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) 578d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) 579d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) 580d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) 581d62f2f8cSHeiko Schocher #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) 582a83e1b7bSEric Nelson 583de710a14SEric Nelson struct iomuxc { 584290e7cfdSFabio Estevam #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) 585aeadf065SFabio Estevam u8 reserved[0x4000]; 586aeadf065SFabio Estevam #endif 587de710a14SEric Nelson u32 gpr[14]; 588de710a14SEric Nelson }; 589de710a14SEric Nelson 590ac17dcf6SFabio Estevam struct gpc { 591ac17dcf6SFabio Estevam u32 cntr; 592ac17dcf6SFabio Estevam u32 pgr; 593ac17dcf6SFabio Estevam u32 imr1; 594ac17dcf6SFabio Estevam u32 imr2; 595ac17dcf6SFabio Estevam u32 imr3; 596ac17dcf6SFabio Estevam u32 imr4; 597ac17dcf6SFabio Estevam u32 isr1; 598ac17dcf6SFabio Estevam u32 isr2; 599ac17dcf6SFabio Estevam u32 isr3; 600ac17dcf6SFabio Estevam u32 isr4; 601ac17dcf6SFabio Estevam }; 602ac17dcf6SFabio Estevam 603de710a14SEric Nelson #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 604de710a14SEric Nelson #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) 605de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 606de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) 607de710a14SEric Nelson 608de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 609de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 610de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 611de710a14SEric Nelson #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) 612de710a14SEric Nelson #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 613de710a14SEric Nelson #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 614de710a14SEric Nelson 615de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 616de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 617de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 618de710a14SEric Nelson #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) 619de710a14SEric Nelson 620de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 621de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 622de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 623de710a14SEric Nelson #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) 624de710a14SEric Nelson 625de710a14SEric Nelson #define IOMUXC_GPR2_BITMAP_SPWG 0 626de710a14SEric Nelson #define IOMUXC_GPR2_BITMAP_JEIDA 1 627de710a14SEric Nelson 628de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 629de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 630de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 631de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) 632de710a14SEric Nelson 633de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_18 0 634de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_24 1 635de710a14SEric Nelson 636de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 637de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 638de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 639de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) 640de710a14SEric Nelson 641de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 642de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 643de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 644de710a14SEric Nelson #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) 645de710a14SEric Nelson 646de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 647de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 648de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 649de710a14SEric Nelson #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) 650de710a14SEric Nelson 651de710a14SEric Nelson #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 652de710a14SEric Nelson #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) 653de710a14SEric Nelson 654de710a14SEric Nelson #define IOMUXC_GPR2_MODE_DISABLED 0 655de710a14SEric Nelson #define IOMUXC_GPR2_MODE_ENABLED_DI0 1 6567aa1e8bbSPierre Aubert #define IOMUXC_GPR2_MODE_ENABLED_DI1 3 657de710a14SEric Nelson 658de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 659de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 660de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 661de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 662de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) 663de710a14SEric Nelson 664de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 665de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 666de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 667de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 668de710a14SEric Nelson #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) 669de710a14SEric Nelson 670d5c37c9cSEric Nelson /* ECSPI registers */ 671d5c37c9cSEric Nelson struct cspi_regs { 672d5c37c9cSEric Nelson u32 rxdata; 673d5c37c9cSEric Nelson u32 txdata; 674d5c37c9cSEric Nelson u32 ctrl; 675d5c37c9cSEric Nelson u32 cfg; 676d5c37c9cSEric Nelson u32 intr; 677d5c37c9cSEric Nelson u32 dma; 678d5c37c9cSEric Nelson u32 stat; 679d5c37c9cSEric Nelson u32 period; 680d5c37c9cSEric Nelson }; 681d5c37c9cSEric Nelson 682d5c37c9cSEric Nelson /* 683d5c37c9cSEric Nelson * CSPI register definitions 684d5c37c9cSEric Nelson */ 685d5c37c9cSEric Nelson #define MXC_ECSPI 686d5c37c9cSEric Nelson #define MXC_CSPICTRL_EN (1 << 0) 687d5c37c9cSEric Nelson #define MXC_CSPICTRL_MODE (1 << 1) 688d5c37c9cSEric Nelson #define MXC_CSPICTRL_XCH (1 << 2) 6890f1411bcSFabio Estevam #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 690d5c37c9cSEric Nelson #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 691d5c37c9cSEric Nelson #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 692d5c37c9cSEric Nelson #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 693d5c37c9cSEric Nelson #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 694d5c37c9cSEric Nelson #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 695d5c37c9cSEric Nelson #define MXC_CSPICTRL_MAXBITS 0xfff 696d5c37c9cSEric Nelson #define MXC_CSPICTRL_TC (1 << 7) 697d5c37c9cSEric Nelson #define MXC_CSPICTRL_RXOVF (1 << 6) 698d5c37c9cSEric Nelson #define MXC_CSPIPERIOD_32KHZ (1 << 15) 699d5c37c9cSEric Nelson #define MAX_SPI_BYTES 32 700a0ae0091SHeiko Schocher #define SPI_MAX_NUM 4 701d5c37c9cSEric Nelson 702d5c37c9cSEric Nelson /* Bit position inside CTRL register to be associated with SS */ 703d5c37c9cSEric Nelson #define MXC_CSPICTRL_CHAN 18 704d5c37c9cSEric Nelson 705d5c37c9cSEric Nelson /* Bit position inside CON register to be associated with SS */ 706d7cbcc76SMarkus Niebel #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 707d7cbcc76SMarkus Niebel #define MXC_CSPICON_POL 4 /* SCLK polarity */ 708d7cbcc76SMarkus Niebel #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 709d7cbcc76SMarkus Niebel #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 71056612bf6SPeng Fan #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ 711290e7cfdSFabio Estevam defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 71225b4aa14SFabio Estevam #define MXC_SPI_BASE_ADDRESSES \ 71325b4aa14SFabio Estevam ECSPI1_BASE_ADDR, \ 71425b4aa14SFabio Estevam ECSPI2_BASE_ADDR, \ 71525b4aa14SFabio Estevam ECSPI3_BASE_ADDR, \ 71625b4aa14SFabio Estevam ECSPI4_BASE_ADDR 71725b4aa14SFabio Estevam #else 718d5c37c9cSEric Nelson #define MXC_SPI_BASE_ADDRESSES \ 719d5c37c9cSEric Nelson ECSPI1_BASE_ADDR, \ 720d5c37c9cSEric Nelson ECSPI2_BASE_ADDR, \ 721d5c37c9cSEric Nelson ECSPI3_BASE_ADDR, \ 722d5c37c9cSEric Nelson ECSPI4_BASE_ADDR, \ 723d5c37c9cSEric Nelson ECSPI5_BASE_ADDR 72425b4aa14SFabio Estevam #endif 725d5c37c9cSEric Nelson 7268f3ff11cSBenoît Thébaudeau struct ocotp_regs { 72723608e23SJason Liu u32 ctrl; 72823608e23SJason Liu u32 ctrl_set; 72923608e23SJason Liu u32 ctrl_clr; 73023608e23SJason Liu u32 ctrl_tog; 73123608e23SJason Liu u32 timing; 73223608e23SJason Liu u32 rsvd0[3]; 73323608e23SJason Liu u32 data; 73423608e23SJason Liu u32 rsvd1[3]; 73523608e23SJason Liu u32 read_ctrl; 73623608e23SJason Liu u32 rsvd2[3]; 7378f3ff11cSBenoît Thébaudeau u32 read_fuse_data; 73823608e23SJason Liu u32 rsvd3[3]; 7398f3ff11cSBenoît Thébaudeau u32 sw_sticky; 74023608e23SJason Liu u32 rsvd4[3]; 74123608e23SJason Liu u32 scs; 74223608e23SJason Liu u32 scs_set; 74323608e23SJason Liu u32 scs_clr; 74423608e23SJason Liu u32 scs_tog; 74523608e23SJason Liu u32 crc_addr; 74623608e23SJason Liu u32 rsvd5[3]; 74723608e23SJason Liu u32 crc_value; 74823608e23SJason Liu u32 rsvd6[3]; 74923608e23SJason Liu u32 version; 750bd2e27c0SJason Liu u32 rsvd7[0xdb]; 75123608e23SJason Liu 7527296a023SPeng Fan /* fuse banks */ 75323608e23SJason Liu struct fuse_bank { 75423608e23SJason Liu u32 fuse_regs[0x20]; 7557296a023SPeng Fan } bank[0]; 75623608e23SJason Liu }; 75723608e23SJason Liu 7586adbd302SBenoît Thébaudeau struct fuse_bank0_regs { 7596adbd302SBenoît Thébaudeau u32 lock; 7606adbd302SBenoît Thébaudeau u32 rsvd0[3]; 7616adbd302SBenoît Thébaudeau u32 uid_low; 7626adbd302SBenoît Thébaudeau u32 rsvd1[3]; 7636adbd302SBenoît Thébaudeau u32 uid_high; 764b83c709eSStefano Babic u32 rsvd2[3]; 7651730af1bSPeng Fan u32 cfg2; 7661730af1bSPeng Fan u32 rsvd3[3]; 7671730af1bSPeng Fan u32 cfg3; 7681730af1bSPeng Fan u32 rsvd4[3]; 7691730af1bSPeng Fan u32 cfg4; 7701730af1bSPeng Fan u32 rsvd5[3]; 771b83c709eSStefano Babic u32 cfg5; 772b83c709eSStefano Babic u32 rsvd6[3]; 7731730af1bSPeng Fan u32 cfg6; 7741730af1bSPeng Fan u32 rsvd7[3]; 7756adbd302SBenoît Thébaudeau }; 7766adbd302SBenoît Thébaudeau 777d43e0ab4STim Harvey struct fuse_bank1_regs { 778d43e0ab4STim Harvey u32 mem0; 779d43e0ab4STim Harvey u32 rsvd0[3]; 780d43e0ab4STim Harvey u32 mem1; 781d43e0ab4STim Harvey u32 rsvd1[3]; 782d43e0ab4STim Harvey u32 mem2; 783d43e0ab4STim Harvey u32 rsvd2[3]; 784d43e0ab4STim Harvey u32 mem3; 785d43e0ab4STim Harvey u32 rsvd3[3]; 786d43e0ab4STim Harvey u32 mem4; 787d43e0ab4STim Harvey u32 rsvd4[3]; 788d43e0ab4STim Harvey u32 ana0; 789d43e0ab4STim Harvey u32 rsvd5[3]; 790d43e0ab4STim Harvey u32 ana1; 791d43e0ab4STim Harvey u32 rsvd6[3]; 792d43e0ab4STim Harvey u32 ana2; 793d43e0ab4STim Harvey u32 rsvd7[3]; 794d43e0ab4STim Harvey }; 795d43e0ab4STim Harvey 79605d54b82SFabio Estevam struct fuse_bank4_regs { 79705d54b82SFabio Estevam u32 sjc_resp_low; 79805d54b82SFabio Estevam u32 rsvd0[3]; 79905d54b82SFabio Estevam u32 sjc_resp_high; 80005d54b82SFabio Estevam u32 rsvd1[3]; 801d4d1dd67SYe Li u32 mac_addr0; 80205d54b82SFabio Estevam u32 rsvd2[3]; 803d4d1dd67SYe Li u32 mac_addr1; 80405d54b82SFabio Estevam u32 rsvd3[3]; 805d4d1dd67SYe Li u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/ 80605d54b82SFabio Estevam u32 rsvd4[7]; 80705d54b82SFabio Estevam u32 gp1; 808bc32fc69SPeng Fan u32 rsvd5[3]; 809bc32fc69SPeng Fan u32 gp2; 810bc32fc69SPeng Fan u32 rsvd6[3]; 81105d54b82SFabio Estevam }; 81223608e23SJason Liu 813f2f77458SJason Liu struct aipstz_regs { 814f2f77458SJason Liu u32 mprot0; 815f2f77458SJason Liu u32 mprot1; 816f2f77458SJason Liu u32 rsvd[0xe]; 817f2f77458SJason Liu u32 opacr0; 818f2f77458SJason Liu u32 opacr1; 819f2f77458SJason Liu u32 opacr2; 820f2f77458SJason Liu u32 opacr3; 821f2f77458SJason Liu u32 opacr4; 822f2f77458SJason Liu }; 823f2f77458SJason Liu 824a7683867SFabio Estevam struct anatop_regs { 825a7683867SFabio Estevam u32 pll_sys; /* 0x000 */ 826a7683867SFabio Estevam u32 pll_sys_set; /* 0x004 */ 827a7683867SFabio Estevam u32 pll_sys_clr; /* 0x008 */ 828a7683867SFabio Estevam u32 pll_sys_tog; /* 0x00c */ 829a7683867SFabio Estevam u32 usb1_pll_480_ctrl; /* 0x010 */ 830a7683867SFabio Estevam u32 usb1_pll_480_ctrl_set; /* 0x014 */ 831a7683867SFabio Estevam u32 usb1_pll_480_ctrl_clr; /* 0x018 */ 832a7683867SFabio Estevam u32 usb1_pll_480_ctrl_tog; /* 0x01c */ 833a7683867SFabio Estevam u32 usb2_pll_480_ctrl; /* 0x020 */ 834a7683867SFabio Estevam u32 usb2_pll_480_ctrl_set; /* 0x024 */ 835a7683867SFabio Estevam u32 usb2_pll_480_ctrl_clr; /* 0x028 */ 836a7683867SFabio Estevam u32 usb2_pll_480_ctrl_tog; /* 0x02c */ 837a7683867SFabio Estevam u32 pll_528; /* 0x030 */ 838a7683867SFabio Estevam u32 pll_528_set; /* 0x034 */ 839a7683867SFabio Estevam u32 pll_528_clr; /* 0x038 */ 840a7683867SFabio Estevam u32 pll_528_tog; /* 0x03c */ 841a7683867SFabio Estevam u32 pll_528_ss; /* 0x040 */ 842a7683867SFabio Estevam u32 rsvd0[3]; 843a7683867SFabio Estevam u32 pll_528_num; /* 0x050 */ 844a7683867SFabio Estevam u32 rsvd1[3]; 845a7683867SFabio Estevam u32 pll_528_denom; /* 0x060 */ 846a7683867SFabio Estevam u32 rsvd2[3]; 847a7683867SFabio Estevam u32 pll_audio; /* 0x070 */ 848a7683867SFabio Estevam u32 pll_audio_set; /* 0x074 */ 849a7683867SFabio Estevam u32 pll_audio_clr; /* 0x078 */ 850a7683867SFabio Estevam u32 pll_audio_tog; /* 0x07c */ 851a7683867SFabio Estevam u32 pll_audio_num; /* 0x080 */ 852a7683867SFabio Estevam u32 rsvd3[3]; 853a7683867SFabio Estevam u32 pll_audio_denom; /* 0x090 */ 854a7683867SFabio Estevam u32 rsvd4[3]; 855a7683867SFabio Estevam u32 pll_video; /* 0x0a0 */ 856a7683867SFabio Estevam u32 pll_video_set; /* 0x0a4 */ 857a7683867SFabio Estevam u32 pll_video_clr; /* 0x0a8 */ 858a7683867SFabio Estevam u32 pll_video_tog; /* 0x0ac */ 859a7683867SFabio Estevam u32 pll_video_num; /* 0x0b0 */ 860a7683867SFabio Estevam u32 rsvd5[3]; 861a7683867SFabio Estevam u32 pll_video_denom; /* 0x0c0 */ 862a7683867SFabio Estevam u32 rsvd6[3]; 863a7683867SFabio Estevam u32 pll_mlb; /* 0x0d0 */ 864a7683867SFabio Estevam u32 pll_mlb_set; /* 0x0d4 */ 865a7683867SFabio Estevam u32 pll_mlb_clr; /* 0x0d8 */ 866a7683867SFabio Estevam u32 pll_mlb_tog; /* 0x0dc */ 867a7683867SFabio Estevam u32 pll_enet; /* 0x0e0 */ 868a7683867SFabio Estevam u32 pll_enet_set; /* 0x0e4 */ 869a7683867SFabio Estevam u32 pll_enet_clr; /* 0x0e8 */ 870a7683867SFabio Estevam u32 pll_enet_tog; /* 0x0ec */ 871a7683867SFabio Estevam u32 pfd_480; /* 0x0f0 */ 872a7683867SFabio Estevam u32 pfd_480_set; /* 0x0f4 */ 873a7683867SFabio Estevam u32 pfd_480_clr; /* 0x0f8 */ 874a7683867SFabio Estevam u32 pfd_480_tog; /* 0x0fc */ 875a7683867SFabio Estevam u32 pfd_528; /* 0x100 */ 876a7683867SFabio Estevam u32 pfd_528_set; /* 0x104 */ 877a7683867SFabio Estevam u32 pfd_528_clr; /* 0x108 */ 878a7683867SFabio Estevam u32 pfd_528_tog; /* 0x10c */ 879a7683867SFabio Estevam u32 reg_1p1; /* 0x110 */ 880a7683867SFabio Estevam u32 reg_1p1_set; /* 0x114 */ 881a7683867SFabio Estevam u32 reg_1p1_clr; /* 0x118 */ 882a7683867SFabio Estevam u32 reg_1p1_tog; /* 0x11c */ 883a7683867SFabio Estevam u32 reg_3p0; /* 0x120 */ 884a7683867SFabio Estevam u32 reg_3p0_set; /* 0x124 */ 885a7683867SFabio Estevam u32 reg_3p0_clr; /* 0x128 */ 886a7683867SFabio Estevam u32 reg_3p0_tog; /* 0x12c */ 887a7683867SFabio Estevam u32 reg_2p5; /* 0x130 */ 888a7683867SFabio Estevam u32 reg_2p5_set; /* 0x134 */ 889a7683867SFabio Estevam u32 reg_2p5_clr; /* 0x138 */ 890a7683867SFabio Estevam u32 reg_2p5_tog; /* 0x13c */ 891a7683867SFabio Estevam u32 reg_core; /* 0x140 */ 892a7683867SFabio Estevam u32 reg_core_set; /* 0x144 */ 893a7683867SFabio Estevam u32 reg_core_clr; /* 0x148 */ 894a7683867SFabio Estevam u32 reg_core_tog; /* 0x14c */ 895a7683867SFabio Estevam u32 ana_misc0; /* 0x150 */ 896a7683867SFabio Estevam u32 ana_misc0_set; /* 0x154 */ 897a7683867SFabio Estevam u32 ana_misc0_clr; /* 0x158 */ 898a7683867SFabio Estevam u32 ana_misc0_tog; /* 0x15c */ 899a7683867SFabio Estevam u32 ana_misc1; /* 0x160 */ 900a7683867SFabio Estevam u32 ana_misc1_set; /* 0x164 */ 901a7683867SFabio Estevam u32 ana_misc1_clr; /* 0x168 */ 902a7683867SFabio Estevam u32 ana_misc1_tog; /* 0x16c */ 903a7683867SFabio Estevam u32 ana_misc2; /* 0x170 */ 904a7683867SFabio Estevam u32 ana_misc2_set; /* 0x174 */ 905a7683867SFabio Estevam u32 ana_misc2_clr; /* 0x178 */ 906a7683867SFabio Estevam u32 ana_misc2_tog; /* 0x17c */ 907a7683867SFabio Estevam u32 tempsense0; /* 0x180 */ 908a7683867SFabio Estevam u32 tempsense0_set; /* 0x184 */ 909a7683867SFabio Estevam u32 tempsense0_clr; /* 0x188 */ 910a7683867SFabio Estevam u32 tempsense0_tog; /* 0x18c */ 911a7683867SFabio Estevam u32 tempsense1; /* 0x190 */ 912a7683867SFabio Estevam u32 tempsense1_set; /* 0x194 */ 913a7683867SFabio Estevam u32 tempsense1_clr; /* 0x198 */ 914a7683867SFabio Estevam u32 tempsense1_tog; /* 0x19c */ 915a7683867SFabio Estevam u32 usb1_vbus_detect; /* 0x1a0 */ 916a7683867SFabio Estevam u32 usb1_vbus_detect_set; /* 0x1a4 */ 917a7683867SFabio Estevam u32 usb1_vbus_detect_clr; /* 0x1a8 */ 918a7683867SFabio Estevam u32 usb1_vbus_detect_tog; /* 0x1ac */ 919a7683867SFabio Estevam u32 usb1_chrg_detect; /* 0x1b0 */ 920a7683867SFabio Estevam u32 usb1_chrg_detect_set; /* 0x1b4 */ 921a7683867SFabio Estevam u32 usb1_chrg_detect_clr; /* 0x1b8 */ 922a7683867SFabio Estevam u32 usb1_chrg_detect_tog; /* 0x1bc */ 923a7683867SFabio Estevam u32 usb1_vbus_det_stat; /* 0x1c0 */ 924a7683867SFabio Estevam u32 usb1_vbus_det_stat_set; /* 0x1c4 */ 925a7683867SFabio Estevam u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ 926a7683867SFabio Estevam u32 usb1_vbus_det_stat_tog; /* 0x1cc */ 927a7683867SFabio Estevam u32 usb1_chrg_det_stat; /* 0x1d0 */ 928a7683867SFabio Estevam u32 usb1_chrg_det_stat_set; /* 0x1d4 */ 929a7683867SFabio Estevam u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ 930a7683867SFabio Estevam u32 usb1_chrg_det_stat_tog; /* 0x1dc */ 931a7683867SFabio Estevam u32 usb1_loopback; /* 0x1e0 */ 932a7683867SFabio Estevam u32 usb1_loopback_set; /* 0x1e4 */ 933a7683867SFabio Estevam u32 usb1_loopback_clr; /* 0x1e8 */ 934a7683867SFabio Estevam u32 usb1_loopback_tog; /* 0x1ec */ 935a7683867SFabio Estevam u32 usb1_misc; /* 0x1f0 */ 936a7683867SFabio Estevam u32 usb1_misc_set; /* 0x1f4 */ 937a7683867SFabio Estevam u32 usb1_misc_clr; /* 0x1f8 */ 938a7683867SFabio Estevam u32 usb1_misc_tog; /* 0x1fc */ 939a7683867SFabio Estevam u32 usb2_vbus_detect; /* 0x200 */ 940a7683867SFabio Estevam u32 usb2_vbus_detect_set; /* 0x204 */ 941a7683867SFabio Estevam u32 usb2_vbus_detect_clr; /* 0x208 */ 942a7683867SFabio Estevam u32 usb2_vbus_detect_tog; /* 0x20c */ 943a7683867SFabio Estevam u32 usb2_chrg_detect; /* 0x210 */ 944a7683867SFabio Estevam u32 usb2_chrg_detect_set; /* 0x214 */ 945a7683867SFabio Estevam u32 usb2_chrg_detect_clr; /* 0x218 */ 946a7683867SFabio Estevam u32 usb2_chrg_detect_tog; /* 0x21c */ 947a7683867SFabio Estevam u32 usb2_vbus_det_stat; /* 0x220 */ 948a7683867SFabio Estevam u32 usb2_vbus_det_stat_set; /* 0x224 */ 949a7683867SFabio Estevam u32 usb2_vbus_det_stat_clr; /* 0x228 */ 950a7683867SFabio Estevam u32 usb2_vbus_det_stat_tog; /* 0x22c */ 951a7683867SFabio Estevam u32 usb2_chrg_det_stat; /* 0x230 */ 952a7683867SFabio Estevam u32 usb2_chrg_det_stat_set; /* 0x234 */ 953a7683867SFabio Estevam u32 usb2_chrg_det_stat_clr; /* 0x238 */ 954a7683867SFabio Estevam u32 usb2_chrg_det_stat_tog; /* 0x23c */ 955a7683867SFabio Estevam u32 usb2_loopback; /* 0x240 */ 956a7683867SFabio Estevam u32 usb2_loopback_set; /* 0x244 */ 957a7683867SFabio Estevam u32 usb2_loopback_clr; /* 0x248 */ 958a7683867SFabio Estevam u32 usb2_loopback_tog; /* 0x24c */ 959a7683867SFabio Estevam u32 usb2_misc; /* 0x250 */ 960a7683867SFabio Estevam u32 usb2_misc_set; /* 0x254 */ 961a7683867SFabio Estevam u32 usb2_misc_clr; /* 0x258 */ 962a7683867SFabio Estevam u32 usb2_misc_tog; /* 0x25c */ 963a7683867SFabio Estevam u32 digprog; /* 0x260 */ 96420332a06STroy Kisky u32 reserved1[7]; 96520332a06STroy Kisky u32 digprog_sololite; /* 0x280 */ 966a7683867SFabio Estevam }; 967a7683867SFabio Estevam 9683fc4176dSEric Nelson #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) 9693fc4176dSEric Nelson #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) 9703fc4176dSEric Nelson #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) 9713fc4176dSEric Nelson #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) 9723fc4176dSEric Nelson #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) 9733fc4176dSEric Nelson #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) 974e66ad6e7SEric Nelson 97576c91e66SFabio Estevam struct wdog_regs { 97676c91e66SFabio Estevam u16 wcr; /* Control */ 97776c91e66SFabio Estevam u16 wsr; /* Service */ 97876c91e66SFabio Estevam u16 wrsr; /* Reset Status */ 97976c91e66SFabio Estevam u16 wicr; /* Interrupt Control */ 98076c91e66SFabio Estevam u16 wmcr; /* Miscellaneous Control */ 98176c91e66SFabio Estevam }; 98276c91e66SFabio Estevam 983aafe4020SHeiko Schocher #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) 984aafe4020SHeiko Schocher #define PWMCR_DOZEEN (1 << 24) 985aafe4020SHeiko Schocher #define PWMCR_WAITEN (1 << 23) 986aafe4020SHeiko Schocher #define PWMCR_DBGEN (1 << 22) 987aafe4020SHeiko Schocher #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) 988aafe4020SHeiko Schocher #define PWMCR_CLKSRC_IPG (1 << 16) 989aafe4020SHeiko Schocher #define PWMCR_EN (1 << 0) 990aafe4020SHeiko Schocher 991aafe4020SHeiko Schocher struct pwm_regs { 992aafe4020SHeiko Schocher u32 cr; 993aafe4020SHeiko Schocher u32 sr; 994aafe4020SHeiko Schocher u32 ir; 995aafe4020SHeiko Schocher u32 sar; 996aafe4020SHeiko Schocher u32 pr; 997aafe4020SHeiko Schocher u32 cnr; 998aafe4020SHeiko Schocher }; 999*23eaf418SStefan Agner 1000*23eaf418SStefan Agner /* 1001*23eaf418SStefan Agner * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB 1002*23eaf418SStefan Agner * If boot from the other mode, USB0_PWD will keep reset value 1003*23eaf418SStefan Agner */ 1004*23eaf418SStefan Agner #define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) 1005*23eaf418SStefan Agner 100623608e23SJason Liu #endif /* __ASSEMBLER__*/ 100723608e23SJason Liu #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ 1008