Lines Matching +full:0 +full:x02200000
17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
160 reg = <0x00900000 0x40000>;
168 #size-cells = <0>;
170 reg = <0x02018000 0x4000>;
171 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
188 reg = <0x02200000 0x4000>;
189 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
199 reg = <0x02204000 0x4000>;
200 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
209 #size-cells = <0>;
211 reg = <0x02800000 0x400000>;
212 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
213 <0 7 IRQ_TYPE_LEVEL_HIGH>;
220 ipu2_csi0: port@0 {
221 reg = <0>;
239 ipu2_di0_disp0: endpoint@0 {
240 reg = <0>;
302 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
311 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
316 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
324 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
329 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
335 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
341 mux-controls = <&mux 0>;
343 #size-cells = <0>;
345 port@0 {
346 reg = <0>;
373 #size-cells = <0>;
375 port@0 {
376 reg = <0>;
435 lvds-channel@0 {
527 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
528 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
529 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
530 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
531 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
532 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
533 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */