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/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8516-apmixedsys.c51 { .div = 0, .freq = MT8516_PLL_FMAX },
60 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
61 21, 0x0104, 24, 0, 0x0104, 0),
62 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
63 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
64 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
65 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
66 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
67 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
68 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
[all …]
H A Dclk-mt8167-apmixedsys.c50 { .div = 0, .freq = MT8167_PLL_FMAX },
59 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
60 21, 0x0104, 24, 0, 0x0104, 0),
61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
62 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
63 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
64 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
65 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
66 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
67 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
[all …]
H A Dclk-mt8135.c355 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
356 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
357 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
358 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
360 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
362 0x0144, 8, 2, 15),
363 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
364 MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
366 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
367 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_arm_c9.h6 #define BCMA_DMU_CRU_USB2_CONTROL 0x0164
7 #define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK 0x00000FFC
9 #define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK 0x00007000
11 #define BCMA_DMU_CRU_CLKSET_KEY 0x0180
12 #define BCMA_DMU_CRU_STRAPS_CTRL 0x02A0
13 #define BCMA_DMU_CRU_STRAPS_CTRL_USB3 0x00000010
14 #define BCMA_DMU_CRU_STRAPS_CTRL_4BYTE 0x00008000
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/openbmc/linux/drivers/media/platform/mediatek/jpeg/
H A Dmtk_jpeg_dec_reg.h14 #define BIT_INQST_MASK_ERROR_BS 0x20
15 #define BIT_INQST_MASK_PAUSE 0x10
16 #define BIT_INQST_MASK_OVERFLOW 0x04
17 #define BIT_INQST_MASK_UNDERFLOW 0x02
18 #define BIT_INQST_MASK_EOF 0x01
19 #define BIT_INQST_MASK_ALLIRQ 0x37
21 #define JPGDEC_REG_RESET 0x0090
22 #define JPGDEC_REG_BRZ_FACTOR 0x00f8
23 #define JPGDEC_REG_DU_NUM 0x00fc
24 #define JPGDEC_REG_DEST_ADDR0_Y 0x0140
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Diomux-vf610.h46 VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
47 VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
48 VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
49 VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
50 VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
51 VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
52 VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
53 VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
54 VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
55 VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6ul-pinfunc.h17 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
18 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
24 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
25 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
26 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
27 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/openbmc/u-boot/include/
H A Dcp1250.h4 * Constant CP1250 contains the Unicode code points for characters 0x80 - 0xff
8 0x20ac, 0x0000, 0x201a, 0x0000, \
9 0x201e, 0x2026, 0x2020, 0x2021, \
10 0x0000, 0x2030, 0x0160, 0x2039, \
11 0x015a, 0x0164, 0x017d, 0x0179, \
12 0x0000, 0x2018, 0x2019, 0x201c, \
13 0x201d, 0x2022, 0x2013, 0x2014, \
14 0x0000, 0x2122, 0x0161, 0x203a, \
15 0x015b, 0x0165, 0x017e, 0x017a, \
16 0x00a0, 0x02c7, 0x02d8, 0x0141, \
[all …]
/openbmc/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_xgmac.h12 #define X2_BLOCK_ETH_MAC_CSR_OFFSET 0x3000
13 #define BLOCK_AXG_MAC_OFFSET 0x0800
14 #define BLOCK_AXG_STATS_OFFSET 0x0800
15 #define BLOCK_AXG_MAC_CSR_OFFSET 0x2000
16 #define BLOCK_PCS_OFFSET 0x3800
18 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define XGENET_SRST_ADDR 0x00
20 #define XGENET_CLKEN_ADDR 0x08
22 #define CSR_CLK BIT(0)
29 #define CSR_RST BIT(0)
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/openbmc/linux/drivers/usb/serial/
H A Diuu_phoenix.h13 #define IUU_USB_VENDOR_ID 0x104f
14 #define IUU_USB_PRODUCT_ID 0x0004
15 #define IUU_USB_OP_TIMEOUT 0x0200
19 #define IUU_NO_OPERATION 0x00
20 #define IUU_GET_FIRMWARE_VERSION 0x01
21 #define IUU_GET_PRODUCT_NAME 0x02
22 #define IUU_GET_STATE_REGISTER 0x03
23 #define IUU_SET_LED 0x04
24 #define IUU_WAIT_MUS 0x05
25 #define IUU_WAIT_MS 0x06
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s.h3 /* 0x0000: ctx_dma */
4 /* 0x0000: ctx_dma_query */
5 0x00000000,
6 /* 0x0004: ctx_dma_src */
7 0x00000000,
8 /* 0x0008: ctx_dma_dst */
9 0x00000000,
10 /* 0x000c: ctx_query_address_high */
11 0x00000000,
12 /* 0x0010: ctx_query_address_low */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap4/
H A Dcpu.h19 u32 tidr; /* 0x00 r */
20 u8 res[0xc];
21 u32 tiocp_cfg; /* 0x10 rw */
22 u32 tistat; /* 0x14 r */
23 u32 tisr; /* 0x18 rw */
24 u32 tier; /* 0x1c rw */
25 u32 twer; /* 0x20 rw */
26 u32 tclr; /* 0x24 rw */
27 u32 tcrr; /* 0x28 rw */
28 u32 tldr; /* 0x2c rw */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx7d-pinctrl.yaml94 reg = <0x30330000 0x10000>;
98 <0x0160 0x03D0 0x0714 0x1 0x0 0x7e>,
99 <0x0164 0x03D4 0x0000 0x1 0x0 0x76>;
105 reg = <0x302c0000 0x10000>;
110 <0x0008 0x0038 0x0000 0x0 0x0 0x59>,
111 <0x000C 0x003C 0x0000 0x0 0x0 0x59>;
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dmfp.h23 #define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
24 #define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
25 #define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
26 #define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
27 #define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
28 #define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
29 #define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
30 #define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
31 #define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
32 #define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dcpu.h23 u32 tidr; /* 0x00 r */
24 u8 res1[0xc];
25 u32 tiocp_cfg; /* 0x10 rw */
26 u8 res2[0x10];
27 u32 tisr_raw; /* 0x24 r */
28 u32 tisr; /* 0x28 rw */
29 u32 tier; /* 0x2c rw */
30 u32 ticr; /* 0x30 rw */
31 u32 twer; /* 0x34 rw */
32 u32 tclr; /* 0x38 rw */
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dsdio.h12 #define MCR_WCIR 0x0000
13 #define MCR_WHLPCR 0x0004
18 #define WHLPCR_INT_EN_SET BIT(0)
20 #define MCR_WSDIOCSR 0x0008
21 #define MCR_WHCR 0x000C
32 #define MCR_WHISR 0x0010
33 #define MCR_WHIER 0x0014
40 #define WHIER_TX_DONE_INT_EN BIT(0)
47 #define MCR_WASR 0x0020
48 #define MCR_WSICR 0x0024
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am6548-iot2050-advanced-m2.dts26 ti,cluster-mode = <0>;
32 AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
38 AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
44 AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
45 AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
51 AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
52 AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
53 AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */
61 AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
62 AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]

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