1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2ce089c04SPrafulla Wadaskar /* 3ce089c04SPrafulla Wadaskar * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h 4ce089c04SPrafulla Wadaskar * (C) Copyright 2007 5ce089c04SPrafulla Wadaskar * Marvell Semiconductor <www.marvell.com> 6ce089c04SPrafulla Wadaskar * 2007-08-21: eric miao <eric.miao@marvell.com> 7ce089c04SPrafulla Wadaskar * 8ce089c04SPrafulla Wadaskar * (C) Copyright 2010 9ce089c04SPrafulla Wadaskar * Marvell Semiconductor <www.marvell.com> 10ce089c04SPrafulla Wadaskar * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 11ce089c04SPrafulla Wadaskar * Contributor: Mahavir Jain <mjain@marvell.com> 12ce089c04SPrafulla Wadaskar */ 13ce089c04SPrafulla Wadaskar 14ce089c04SPrafulla Wadaskar #ifndef __ARMADA100_MFP_H 15ce089c04SPrafulla Wadaskar #define __ARMADA100_MFP_H 16ce089c04SPrafulla Wadaskar 17ce089c04SPrafulla Wadaskar /* 18ce089c04SPrafulla Wadaskar * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs 19ce089c04SPrafulla Wadaskar * 20ce089c04SPrafulla Wadaskar * offset, pull,pF, drv,dF, edge,eF ,afn,aF 21ce089c04SPrafulla Wadaskar */ 22ce089c04SPrafulla Wadaskar /* UART1 */ 2381a9ab21SLei Wen #define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) 2481a9ab21SLei Wen #define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST) 2581a9ab21SLei Wen #define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST) 2681a9ab21SLei Wen #define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST) 2781a9ab21SLei Wen #define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM) 2881a9ab21SLei Wen #define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) 2981a9ab21SLei Wen #define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM) 3081a9ab21SLei Wen #define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM) 3181a9ab21SLei Wen #define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM) 3281a9ab21SLei Wen #define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM) 3381a9ab21SLei Wen #define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM) 3481a9ab21SLei Wen #define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM) 35ce089c04SPrafulla Wadaskar 36ce089c04SPrafulla Wadaskar /* UART2 */ 3781a9ab21SLei Wen #define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM) 3881a9ab21SLei Wen #define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM) 3981a9ab21SLei Wen #define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM) 4081a9ab21SLei Wen #define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM) 41ce089c04SPrafulla Wadaskar 42ce089c04SPrafulla Wadaskar /* UART3 */ 4382b13f73SAjay Bhargav #define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM) 4482b13f73SAjay Bhargav #define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM) 4581a9ab21SLei Wen 4681a9ab21SLei Wen /* I2c */ 4781a9ab21SLei Wen #define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) 4881a9ab21SLei Wen #define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) 49ce089c04SPrafulla Wadaskar 50aa0ecfebSAjay Bhargav /* Fast Ethernet */ 51aa0ecfebSAjay Bhargav #define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) 52aa0ecfebSAjay Bhargav #define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 53aa0ecfebSAjay Bhargav #define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) 54aa0ecfebSAjay Bhargav #define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) 55aa0ecfebSAjay Bhargav #define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) 56aa0ecfebSAjay Bhargav #define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 57aa0ecfebSAjay Bhargav #define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) 58aa0ecfebSAjay Bhargav #define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) 59aa0ecfebSAjay Bhargav #define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) 60aa0ecfebSAjay Bhargav #define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 61aa0ecfebSAjay Bhargav #define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) 62aa0ecfebSAjay Bhargav #define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) 63aa0ecfebSAjay Bhargav #define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) 64aa0ecfebSAjay Bhargav #define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 65aa0ecfebSAjay Bhargav #define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) 66aa0ecfebSAjay Bhargav #define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) 67aa0ecfebSAjay Bhargav #define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 68aa0ecfebSAjay Bhargav 69daa4b2f7SAjay Bhargav /* SPI */ 70daa4b2f7SAjay Bhargav #define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) 71daa4b2f7SAjay Bhargav #define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) 72daa4b2f7SAjay Bhargav #define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) 73daa4b2f7SAjay Bhargav #define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) 74daa4b2f7SAjay Bhargav 75ce089c04SPrafulla Wadaskar /* More macros can be defined here... */ 76ce089c04SPrafulla Wadaskar 77ce089c04SPrafulla Wadaskar #define MFP_PIN_MAX 117 78ce089c04SPrafulla Wadaskar 79ce089c04SPrafulla Wadaskar #endif /* __ARMADA100_MFP_H */ 80