1f0a58aa3SFeifei Xu /* 2f0a58aa3SFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 3f0a58aa3SFeifei Xu * 4f0a58aa3SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5f0a58aa3SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6f0a58aa3SFeifei Xu * to deal in the Software without restriction, including without limitation 7f0a58aa3SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8f0a58aa3SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9f0a58aa3SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10f0a58aa3SFeifei Xu * 11f0a58aa3SFeifei Xu * The above copyright notice and this permission notice shall be included 12f0a58aa3SFeifei Xu * in all copies or substantial portions of the Software. 13f0a58aa3SFeifei Xu * 14f0a58aa3SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15f0a58aa3SFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16f0a58aa3SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17f0a58aa3SFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18f0a58aa3SFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19f0a58aa3SFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20f0a58aa3SFeifei Xu */ 21f0a58aa3SFeifei Xu #ifndef _nbio_6_1_OFFSET_HEADER 22f0a58aa3SFeifei Xu #define _nbio_6_1_OFFSET_HEADER 23f0a58aa3SFeifei Xu 24f0a58aa3SFeifei Xu 25f0a58aa3SFeifei Xu 26f0a58aa3SFeifei Xu // addressBlock: nbio_pcie_pswuscfg0_cfgdecp 27f0a58aa3SFeifei Xu // base address: 0x0 28f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_VENDOR_ID 0x0000 29f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_DEVICE_ID 0x0002 30f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_COMMAND 0x0004 31f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_STATUS 0x0006 32f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_REVISION_ID 0x0008 33f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PROG_INTERFACE 0x0009 34f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_SUB_CLASS 0x000a 35f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_BASE_CLASS 0x000b 36f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_CACHE_LINE 0x000c 37f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_LATENCY 0x000d 38f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_HEADER 0x000e 39f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_BIST 0x000f 40f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x0018 41f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_IO_BASE_LIMIT 0x001c 42f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_SECONDARY_STATUS 0x001e 43f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020 44f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PREF_BASE_LIMIT 0x0024 45f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PREF_BASE_UPPER 0x0028 46f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PREF_LIMIT_UPPER 0x002c 47f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_IO_BASE_LIMIT_HI 0x0030 48f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_CAP_PTR 0x0034 49f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_INTERRUPT_LINE 0x003c 50f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_INTERRUPT_PIN 0x003d 51f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL 0x003e 52f0a58aa3SFeifei Xu #define cfgEXT_BRIDGE_CNTL 0x0040 53f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_VENDOR_CAP_LIST 0x0048 54f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_ADAPTER_ID_W 0x004c 55f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PMI_CAP_LIST 0x0050 56f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PMI_CAP 0x0052 57f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PMI_STATUS_CNTL 0x0054 58f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_CAP_LIST 0x0058 59f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_CAP 0x005a 60f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_DEVICE_CAP 0x005c 61f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_DEVICE_CNTL 0x0060 62f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_DEVICE_STATUS 0x0062 63f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_LINK_CAP 0x0064 64f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_LINK_CNTL 0x0068 65f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_LINK_STATUS 0x006a 66f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_DEVICE_CAP2 0x007c 67f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_DEVICE_CNTL2 0x0080 68f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_DEVICE_STATUS2 0x0082 69f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_LINK_CAP2 0x0084 70f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_LINK_CNTL2 0x0088 71f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_LINK_STATUS2 0x008a 72f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_MSI_CAP_LIST 0x00a0 73f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_CNTL 0x00a2 74f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_ADDR_LO 0x00a4 75f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_ADDR_HI 0x00a8 76f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_DATA 0x00a8 77f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_MSI_MSG_DATA_64 0x00ac 78f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_SSID_CAP_LIST 0x00c0 79f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_SSID_CAP 0x00c4 80f0a58aa3SFeifei Xu #define cfgMSI_MAP_CAP_LIST 0x00c8 81f0a58aa3SFeifei Xu #define cfgMSI_MAP_CAP 0x00ca 82f0a58aa3SFeifei Xu #define cfgMSI_MAP_ADDR_LO 0x00cc 83f0a58aa3SFeifei Xu #define cfgMSI_MAP_ADDR_HI 0x00d0 84f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 85f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 86f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1 0x0108 87f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2 0x010c 88f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST 0x0110 89f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1 0x0114 90f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2 0x0118 91f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL 0x011c 92f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS 0x011e 93f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP 0x0120 94f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL 0x0124 95f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS 0x012a 96f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP 0x012c 97f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL 0x0130 98f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS 0x0136 99f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 100f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 101f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 102f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 103f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS 0x0154 104f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK 0x0158 105f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY 0x015c 106f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS 0x0160 107f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK 0x0164 108f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL 0x0168 109f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_HDR_LOG0 0x016c 110f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_HDR_LOG1 0x0170 111f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_HDR_LOG2 0x0174 112f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_HDR_LOG3 0x0178 113f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0 0x0188 114f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1 0x018c 115f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2 0x0190 116f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3 0x0194 117f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 118f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LINK_CNTL3 0x0274 119f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS 0x0278 120f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 121f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 122f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 123f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 124f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 125f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 126f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 127f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 128f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 129f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 130f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 131f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 132f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 133f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 134f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 135f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 136f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST 0x02a0 137f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_ACS_CAP 0x02a4 138f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_ACS_CNTL 0x02a6 139f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST 0x02f0 140f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_CAP 0x02f4 141f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_CNTL 0x02f6 142f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_ADDR0 0x02f8 143f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_ADDR1 0x02fc 144f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_RCV0 0x0300 145f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_RCV1 0x0304 146f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0 0x0308 147f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1 0x030c 148f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 149f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 150f0a58aa3SFeifei Xu #define cfgPCIE_MC_OVERLAY_BAR0 0x0318 151f0a58aa3SFeifei Xu #define cfgPCIE_MC_OVERLAY_BAR1 0x031c 152f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST 0x0320 153f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_LTR_CAP 0x0324 154f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST 0x0328 155f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_ARI_CAP 0x032c 156f0a58aa3SFeifei Xu #define cfgPSWUSCFG0_PCIE_ARI_CNTL 0x032e 157f0a58aa3SFeifei Xu #define cfgPCIE_L1_PM_SUB_CAP_LIST 0x0370 158f0a58aa3SFeifei Xu #define cfgPCIE_L1_PM_SUB_CAP 0x0374 159f0a58aa3SFeifei Xu #define cfgPCIE_L1_PM_SUB_CNTL 0x0378 160f0a58aa3SFeifei Xu #define cfgPCIE_L1_PM_SUB_CNTL2 0x037c 161f0a58aa3SFeifei Xu #define cfgPCIE_ESM_CAP_LIST 0x03c4 162f0a58aa3SFeifei Xu #define cfgPCIE_ESM_HEADER_1 0x03c8 163f0a58aa3SFeifei Xu #define cfgPCIE_ESM_HEADER_2 0x03cc 164f0a58aa3SFeifei Xu #define cfgPCIE_ESM_STATUS 0x03ce 165f0a58aa3SFeifei Xu #define cfgPCIE_ESM_CTRL 0x03d0 166f0a58aa3SFeifei Xu #define cfgPCIE_ESM_CAP_1 0x03d4 167f0a58aa3SFeifei Xu #define cfgPCIE_ESM_CAP_2 0x03d8 168f0a58aa3SFeifei Xu #define cfgPCIE_ESM_CAP_3 0x03dc 169f0a58aa3SFeifei Xu #define cfgPCIE_ESM_CAP_4 0x03e0 170f0a58aa3SFeifei Xu #define cfgPCIE_ESM_CAP_5 0x03e4 171f0a58aa3SFeifei Xu #define cfgPCIE_ESM_CAP_6 0x03e8 172f0a58aa3SFeifei Xu #define cfgPCIE_ESM_CAP_7 0x03ec 173f0a58aa3SFeifei Xu 174f0a58aa3SFeifei Xu 175f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp 176f0a58aa3SFeifei Xu // base address: 0x0 177f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000 178f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002 179f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004 180f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006 181f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008 182f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009 183f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a 184f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b 185f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c 186f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d 187f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e 188f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f 189f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010 190f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014 191f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018 192f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c 193f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020 194f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024 195f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c 196f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030 197f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034 198f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c 199f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d 200f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e 201f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f 202f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048 203f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c 204f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050 205f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052 206f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054 207f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064 208f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066 209f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068 210f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c 211f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e 212f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070 213f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074 214f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076 215f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088 216f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c 217f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e 218f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090 219f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094 220f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096 221f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2 0x0098 222f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2 0x009c 223f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2 0x009e 224f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0 225f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2 226f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 227f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 228f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8 229f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac 230f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac 231f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0 232f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0 233f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4 234f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0 235f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2 236f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4 237f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8 238f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 239f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 240f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 241f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 242f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 243f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 244f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 245f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c 246f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e 247f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 248f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 249f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a 250f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c 251f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 252f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 253f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 254f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 255f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 256f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 257f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 258f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 259f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 260f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 261f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 262f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 263f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c 264f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170 265f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174 266f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178 267f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 268f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 269f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 270f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 271f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 272f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204 273f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208 274f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c 275f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210 276f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214 277f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218 278f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c 279f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220 280f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224 281f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228 282f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c 283f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230 284f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 285f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 286f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 287f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c 288f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 289f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254 290f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 291f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c 292f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e 293f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 294f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 295f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 296f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 297f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 298f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 299f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 300f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 301f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 302f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274 303f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 304f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 305f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 306f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 307f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 308f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 309f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 310f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 311f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 312f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 313f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 314f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 315f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 316f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 317f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 318f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 319f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 320f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 321f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4 322f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6 323f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 324f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4 325f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6 326f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 327f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4 328f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6 329f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 330f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 331f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 332f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4 333f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6 334f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 335f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x02e4 336f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x02e8 337f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 338f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4 339f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6 340f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8 341f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc 342f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300 343f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304 344f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308 345f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c 346f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 347f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 348f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 349f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324 350f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 351f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c 352f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e 353f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 354f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334 355f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338 356f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a 357f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c 358f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e 359f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340 360f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 361f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 362f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346 363f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 364f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 365f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 366f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 367f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 368f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 369f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 370f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 371f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 372f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 373f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 374f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 375f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 376f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c 377f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 378f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 379f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 380f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c 381f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 382f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 383f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 384f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c 385f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 386f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 387f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 388f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c 389f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 390f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 391f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 392f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c 393f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 394f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 395f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 396f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c 397f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 398f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 399f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 400f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c 401f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 402f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 403f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 404f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c 405f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 406f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 407f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 408f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c 409f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 410f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 411f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 412f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 413f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac 414f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 415f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 416f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 417f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc 418f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 419f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 420f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 421f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 422f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc 423f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 424f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 425f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 426f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec 427f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 428f0a58aa3SFeifei Xu 429f0a58aa3SFeifei Xu 430f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp 431f0a58aa3SFeifei Xu // base address: 0x0 432f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 433f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 434f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 435f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 436f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 437f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 438f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a 439f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b 440f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c 441f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d 442f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e 443f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f 444f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 445f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 446f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 447f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c 448f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 449f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 450f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c 451f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 452f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 453f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c 454f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d 455f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e 456f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f 457f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 458f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c 459f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 460f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 461f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 462f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 463f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 464f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 465f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c 466f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e 467f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 468f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 469f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 470f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 471f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c 472f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e 473f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 474f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 475f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 476f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098 477f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c 478f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e 479f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 480f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 481f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 482f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 483f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 484f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac 485f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac 486f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 487f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 488f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 489f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 490f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 491f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 492f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 493f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 494f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 495f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 496f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 497f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 498f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 499f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 500f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c 501f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e 502f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 503f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 504f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a 505f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c 506f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 507f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 508f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 509f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 510f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 511f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 512f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 513f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 514f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 515f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 516f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 517f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 518f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c 519f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 520f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 521f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 522f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 523f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 524f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 525f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 526f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 527f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 528f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 529f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c 530f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 531f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 532f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 533f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c 534f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 535f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 536f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 537f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c 538f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 539f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 540f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 541f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 542f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c 543f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 544f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 545f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 546f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c 547f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e 548f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 549f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 550f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 551f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 552f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 553f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 554f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 555f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 556f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 557f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 558f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 559f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 560f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 561f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 562f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 563f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 564f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 565f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 566f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 567f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 568f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 569f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 570f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 571f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 572f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 573f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 574f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 575f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 576f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 577f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 578f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 579f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 580f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 581f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 582f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 583f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 584f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 585f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 586f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 587f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 588f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 589f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 590f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x02e4 591f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x02e8 592f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 593f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 594f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 595f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 596f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc 597f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 598f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 599f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 600f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c 601f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 602f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 603f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 604f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 605f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 606f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c 607f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e 608f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 609f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 610f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 611f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a 612f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c 613f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e 614f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 615f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 616f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 617f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 618f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 619f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 620f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 621f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 622f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 623f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 624f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 625f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 626f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 627f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 628f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 629f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 630f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 631f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c 632f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 633f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 634f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 635f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c 636f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 637f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 638f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 639f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c 640f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 641f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 642f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 643f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c 644f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 645f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 646f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 647f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c 648f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 649f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 650f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 651f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c 652f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 653f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 654f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 655f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c 656f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 657f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 658f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 659f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c 660f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 661f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 662f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 663f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c 664f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 665f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 666f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 667f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 668f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac 669f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 670f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 671f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 672f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc 673f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 674f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 675f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 676f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 677f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc 678f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 679f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 680f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 681f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec 682f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 683f0a58aa3SFeifei Xu 684f0a58aa3SFeifei Xu 685f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp 686f0a58aa3SFeifei Xu // base address: 0x0 687f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000 688f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002 689f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004 690f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006 691f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008 692f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009 693f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a 694f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b 695f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c 696f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d 697f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e 698f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f 699f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010 700f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018 701f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c 702f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e 703f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020 704f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024 705f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028 706f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c 707f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030 708f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034 709f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c 710f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d 711f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e 712f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050 713f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052 714f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054 715f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058 716f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a 717f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c 718f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060 719f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062 720f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064 721f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068 722f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a 723f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c 724f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070 725f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072 726f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c 727f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080 728f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082 729f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084 730f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088 731f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a 732f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c 733f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090 734f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092 735f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0 736f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2 737f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4 738f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8 739f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8 740f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac 741f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0 742f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4 743f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 744f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 745f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108 746f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c 747f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110 748f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114 749f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118 750f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c 751f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e 752f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120 753f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124 754f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a 755f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c 756f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130 757f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136 758f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 759f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 760f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 761f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 762f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154 763f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158 764f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c 765f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160 766f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164 767f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168 768f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c 769f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170 770f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174 771f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178 772f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188 773f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c 774f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190 775f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194 776f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 777f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274 778f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278 779f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 780f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 781f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 782f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 783f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 784f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 785f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 786f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 787f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 788f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 789f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 790f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 791f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 792f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 793f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 794f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 795f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0 796f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4 797f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6 798f0a58aa3SFeifei Xu 799f0a58aa3SFeifei Xu 800f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp 801f0a58aa3SFeifei Xu // base address: 0x0 802f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000 803f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002 804f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004 805f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006 806f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008 807f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009 808f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a 809f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b 810f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c 811f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d 812f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e 813f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f 814f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010 815f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014 816f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018 817f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c 818f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020 819f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024 820f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c 821f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030 822f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034 823f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c 824f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d 825f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064 826f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066 827f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068 828f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c 829f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e 830f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070 831f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074 832f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076 833f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088 834f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c 835f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e 836f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090 837f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094 838f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096 839f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2 0x0098 840f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2 0x009c 841f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2 0x009e 842f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0 843f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2 844f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4 845f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8 846f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8 847f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac 848f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac 849f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0 850f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0 851f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4 852f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0 853f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2 854f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4 855f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8 856f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 857f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 858f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 859f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 860f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 861f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 862f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158 863f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 864f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160 865f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164 866f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 867f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c 868f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170 869f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174 870f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178 871f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 872f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 873f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 874f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 875f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 876f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4 877f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6 878f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 879f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c 880f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e 881f0a58aa3SFeifei Xu 882f0a58aa3SFeifei Xu 883f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp 884f0a58aa3SFeifei Xu // base address: 0x0 885f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000 886f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002 887f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004 888f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006 889f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008 890f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009 891f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a 892f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b 893f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c 894f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d 895f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e 896f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f 897f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010 898f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014 899f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018 900f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c 901f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020 902f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024 903f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c 904f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030 905f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034 906f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c 907f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d 908f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064 909f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066 910f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068 911f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c 912f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e 913f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070 914f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074 915f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076 916f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088 917f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c 918f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e 919f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090 920f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094 921f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096 922f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2 0x0098 923f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2 0x009c 924f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2 0x009e 925f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0 926f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2 927f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4 928f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8 929f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8 930f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac 931f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac 932f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0 933f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0 934f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4 935f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0 936f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2 937f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4 938f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8 939f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 940f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 941f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 942f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 943f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 944f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 945f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158 946f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 947f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160 948f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164 949f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 950f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c 951f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170 952f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174 953f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178 954f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 955f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 956f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 957f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 958f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 959f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4 960f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6 961f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 962f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c 963f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e 964f0a58aa3SFeifei Xu 965f0a58aa3SFeifei Xu 966f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp 967f0a58aa3SFeifei Xu // base address: 0x0 968f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000 969f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002 970f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004 971f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006 972f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008 973f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009 974f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a 975f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b 976f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c 977f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d 978f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e 979f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f 980f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010 981f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014 982f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018 983f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c 984f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020 985f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024 986f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c 987f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030 988f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034 989f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c 990f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d 991f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064 992f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066 993f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068 994f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c 995f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e 996f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070 997f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074 998f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076 999f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088 1000f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c 1001f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e 1002f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090 1003f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094 1004f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096 1005f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2 0x0098 1006f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2 0x009c 1007f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2 0x009e 1008f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0 1009f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2 1010f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4 1011f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8 1012f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8 1013f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac 1014f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac 1015f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0 1016f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0 1017f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4 1018f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0 1019f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2 1020f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4 1021f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8 1022f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1023f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1024f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 1025f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c 1026f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1027f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 1028f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158 1029f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1030f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160 1031f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164 1032f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1033f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c 1034f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170 1035f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174 1036f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178 1037f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 1038f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c 1039f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 1040f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 1041f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1042f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4 1043f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6 1044f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1045f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c 1046f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e 1047f0a58aa3SFeifei Xu 1048f0a58aa3SFeifei Xu 1049f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp 1050f0a58aa3SFeifei Xu // base address: 0x0 1051f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000 1052f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002 1053f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004 1054f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006 1055f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008 1056f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009 1057f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a 1058f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b 1059f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c 1060f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d 1061f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e 1062f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f 1063f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010 1064f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014 1065f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018 1066f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c 1067f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020 1068f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024 1069f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c 1070f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030 1071f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034 1072f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c 1073f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d 1074f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064 1075f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066 1076f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068 1077f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c 1078f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e 1079f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070 1080f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074 1081f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076 1082f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088 1083f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c 1084f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e 1085f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090 1086f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094 1087f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096 1088f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2 0x0098 1089f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2 0x009c 1090f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2 0x009e 1091f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0 1092f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2 1093f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4 1094f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8 1095f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8 1096f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac 1097f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac 1098f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0 1099f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0 1100f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4 1101f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0 1102f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2 1103f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4 1104f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8 1105f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1106f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1107f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 1108f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c 1109f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1110f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 1111f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158 1112f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1113f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160 1114f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164 1115f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1116f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c 1117f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170 1118f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174 1119f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178 1120f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 1121f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c 1122f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 1123f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 1124f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1125f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4 1126f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6 1127f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1128f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c 1129f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e 1130f0a58aa3SFeifei Xu 1131f0a58aa3SFeifei Xu 1132f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp 1133f0a58aa3SFeifei Xu // base address: 0x0 1134f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000 1135f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002 1136f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004 1137f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006 1138f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008 1139f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009 1140f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a 1141f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b 1142f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c 1143f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d 1144f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e 1145f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f 1146f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010 1147f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014 1148f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018 1149f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c 1150f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020 1151f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024 1152f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c 1153f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030 1154f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034 1155f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c 1156f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d 1157f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064 1158f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066 1159f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068 1160f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c 1161f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e 1162f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070 1163f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074 1164f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076 1165f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088 1166f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c 1167f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e 1168f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090 1169f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094 1170f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096 1171f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2 0x0098 1172f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2 0x009c 1173f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2 0x009e 1174f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0 1175f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2 1176f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4 1177f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8 1178f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8 1179f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac 1180f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac 1181f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0 1182f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0 1183f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4 1184f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0 1185f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2 1186f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4 1187f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8 1188f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1189f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1190f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 1191f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c 1192f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1193f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 1194f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158 1195f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1196f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160 1197f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164 1198f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1199f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c 1200f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170 1201f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174 1202f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178 1203f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 1204f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c 1205f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 1206f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 1207f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1208f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4 1209f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6 1210f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1211f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c 1212f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e 1213f0a58aa3SFeifei Xu 1214f0a58aa3SFeifei Xu 1215f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp 1216f0a58aa3SFeifei Xu // base address: 0x0 1217f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000 1218f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002 1219f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004 1220f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006 1221f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008 1222f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009 1223f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a 1224f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b 1225f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c 1226f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d 1227f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e 1228f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f 1229f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010 1230f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014 1231f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018 1232f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c 1233f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020 1234f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024 1235f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c 1236f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030 1237f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034 1238f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c 1239f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d 1240f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064 1241f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066 1242f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068 1243f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c 1244f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e 1245f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070 1246f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074 1247f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076 1248f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088 1249f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c 1250f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e 1251f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090 1252f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094 1253f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096 1254f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2 0x0098 1255f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2 0x009c 1256f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2 0x009e 1257f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0 1258f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2 1259f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4 1260f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8 1261f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8 1262f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac 1263f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac 1264f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0 1265f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0 1266f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4 1267f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0 1268f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2 1269f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4 1270f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8 1271f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1272f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1273f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 1274f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c 1275f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1276f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 1277f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158 1278f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1279f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160 1280f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164 1281f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1282f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c 1283f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170 1284f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174 1285f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178 1286f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 1287f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c 1288f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 1289f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 1290f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1291f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4 1292f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6 1293f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1294f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c 1295f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e 1296f0a58aa3SFeifei Xu 1297f0a58aa3SFeifei Xu 1298f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp 1299f0a58aa3SFeifei Xu // base address: 0x0 1300f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000 1301f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002 1302f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004 1303f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006 1304f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008 1305f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009 1306f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a 1307f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b 1308f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c 1309f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d 1310f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e 1311f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f 1312f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010 1313f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014 1314f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018 1315f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c 1316f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020 1317f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024 1318f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c 1319f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030 1320f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034 1321f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c 1322f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d 1323f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064 1324f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066 1325f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068 1326f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c 1327f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e 1328f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070 1329f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074 1330f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076 1331f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088 1332f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c 1333f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e 1334f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090 1335f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094 1336f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096 1337f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2 0x0098 1338f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2 0x009c 1339f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2 0x009e 1340f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0 1341f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2 1342f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4 1343f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8 1344f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8 1345f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac 1346f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac 1347f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0 1348f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0 1349f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4 1350f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0 1351f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2 1352f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4 1353f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8 1354f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1355f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1356f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 1357f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c 1358f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1359f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 1360f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158 1361f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1362f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160 1363f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164 1364f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1365f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c 1366f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170 1367f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174 1368f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178 1369f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 1370f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c 1371f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 1372f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 1373f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1374f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4 1375f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6 1376f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1377f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c 1378f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e 1379f0a58aa3SFeifei Xu 1380f0a58aa3SFeifei Xu 1381f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp 1382f0a58aa3SFeifei Xu // base address: 0x0 1383f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000 1384f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002 1385f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004 1386f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006 1387f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008 1388f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009 1389f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a 1390f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b 1391f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c 1392f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d 1393f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e 1394f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f 1395f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010 1396f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014 1397f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018 1398f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c 1399f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020 1400f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024 1401f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c 1402f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030 1403f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034 1404f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c 1405f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d 1406f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064 1407f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066 1408f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068 1409f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c 1410f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e 1411f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070 1412f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074 1413f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076 1414f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088 1415f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c 1416f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e 1417f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090 1418f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094 1419f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096 1420f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2 0x0098 1421f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2 0x009c 1422f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2 0x009e 1423f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0 1424f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2 1425f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4 1426f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8 1427f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8 1428f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac 1429f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac 1430f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0 1431f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0 1432f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4 1433f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0 1434f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2 1435f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4 1436f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8 1437f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1438f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1439f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 1440f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c 1441f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1442f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 1443f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158 1444f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1445f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160 1446f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164 1447f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1448f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c 1449f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170 1450f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174 1451f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178 1452f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 1453f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c 1454f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 1455f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 1456f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1457f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4 1458f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6 1459f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1460f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c 1461f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e 1462f0a58aa3SFeifei Xu 1463f0a58aa3SFeifei Xu 1464f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp 1465f0a58aa3SFeifei Xu // base address: 0x0 1466f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000 1467f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002 1468f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004 1469f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006 1470f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008 1471f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009 1472f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a 1473f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b 1474f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c 1475f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d 1476f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e 1477f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f 1478f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010 1479f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014 1480f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018 1481f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c 1482f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020 1483f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024 1484f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c 1485f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030 1486f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034 1487f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c 1488f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d 1489f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064 1490f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066 1491f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068 1492f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c 1493f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e 1494f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070 1495f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074 1496f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076 1497f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088 1498f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c 1499f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e 1500f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090 1501f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094 1502f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096 1503f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2 0x0098 1504f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2 0x009c 1505f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2 0x009e 1506f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0 1507f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2 1508f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4 1509f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8 1510f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8 1511f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac 1512f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac 1513f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0 1514f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0 1515f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4 1516f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0 1517f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2 1518f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4 1519f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8 1520f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1521f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1522f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108 1523f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c 1524f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1525f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154 1526f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158 1527f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1528f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160 1529f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164 1530f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1531f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c 1532f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170 1533f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174 1534f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178 1535f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188 1536f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c 1537f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190 1538f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194 1539f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1540f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4 1541f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6 1542f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1543f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c 1544f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e 1545f0a58aa3SFeifei Xu 1546f0a58aa3SFeifei Xu 1547f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp 1548f0a58aa3SFeifei Xu // base address: 0x0 1549f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000 1550f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002 1551f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004 1552f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006 1553f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008 1554f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009 1555f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a 1556f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b 1557f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c 1558f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d 1559f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e 1560f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f 1561f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010 1562f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014 1563f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018 1564f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c 1565f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020 1566f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024 1567f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c 1568f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030 1569f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034 1570f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c 1571f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d 1572f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064 1573f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066 1574f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068 1575f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c 1576f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e 1577f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070 1578f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074 1579f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076 1580f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088 1581f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c 1582f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e 1583f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090 1584f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094 1585f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096 1586f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2 0x0098 1587f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2 0x009c 1588f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2 0x009e 1589f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0 1590f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2 1591f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4 1592f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8 1593f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8 1594f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac 1595f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac 1596f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0 1597f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0 1598f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4 1599f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0 1600f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2 1601f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4 1602f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8 1603f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1604f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1605f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108 1606f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c 1607f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1608f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154 1609f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158 1610f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1611f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160 1612f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164 1613f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1614f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c 1615f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170 1616f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174 1617f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178 1618f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188 1619f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c 1620f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190 1621f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194 1622f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1623f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4 1624f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6 1625f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1626f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c 1627f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e 1628f0a58aa3SFeifei Xu 1629f0a58aa3SFeifei Xu 1630f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp 1631f0a58aa3SFeifei Xu // base address: 0x0 1632f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000 1633f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002 1634f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004 1635f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006 1636f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008 1637f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009 1638f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a 1639f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b 1640f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c 1641f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d 1642f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e 1643f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f 1644f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010 1645f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014 1646f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018 1647f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c 1648f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020 1649f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024 1650f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c 1651f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030 1652f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034 1653f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c 1654f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d 1655f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064 1656f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066 1657f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068 1658f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c 1659f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e 1660f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070 1661f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074 1662f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076 1663f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088 1664f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c 1665f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e 1666f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090 1667f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094 1668f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096 1669f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2 0x0098 1670f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2 0x009c 1671f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2 0x009e 1672f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0 1673f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2 1674f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4 1675f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8 1676f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8 1677f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac 1678f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac 1679f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0 1680f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0 1681f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4 1682f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0 1683f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2 1684f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4 1685f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8 1686f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1687f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1688f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108 1689f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c 1690f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1691f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154 1692f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158 1693f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1694f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160 1695f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164 1696f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1697f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c 1698f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170 1699f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174 1700f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178 1701f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188 1702f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c 1703f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190 1704f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194 1705f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1706f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4 1707f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6 1708f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1709f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c 1710f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e 1711f0a58aa3SFeifei Xu 1712f0a58aa3SFeifei Xu 1713f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp 1714f0a58aa3SFeifei Xu // base address: 0x0 1715f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000 1716f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002 1717f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004 1718f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006 1719f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008 1720f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009 1721f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a 1722f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b 1723f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c 1724f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d 1725f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e 1726f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f 1727f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010 1728f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014 1729f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018 1730f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c 1731f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020 1732f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024 1733f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c 1734f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030 1735f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034 1736f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c 1737f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d 1738f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064 1739f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066 1740f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068 1741f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c 1742f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e 1743f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070 1744f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074 1745f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076 1746f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088 1747f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c 1748f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e 1749f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090 1750f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094 1751f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096 1752f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2 0x0098 1753f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2 0x009c 1754f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2 0x009e 1755f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0 1756f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2 1757f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4 1758f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8 1759f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8 1760f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac 1761f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac 1762f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0 1763f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0 1764f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4 1765f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0 1766f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2 1767f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4 1768f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8 1769f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1770f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1771f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108 1772f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c 1773f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1774f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154 1775f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158 1776f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1777f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160 1778f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164 1779f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1780f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c 1781f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170 1782f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174 1783f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178 1784f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188 1785f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c 1786f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190 1787f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194 1788f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1789f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4 1790f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6 1791f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1792f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c 1793f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e 1794f0a58aa3SFeifei Xu 1795f0a58aa3SFeifei Xu 1796f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp 1797f0a58aa3SFeifei Xu // base address: 0x0 1798f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000 1799f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002 1800f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004 1801f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006 1802f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008 1803f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009 1804f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a 1805f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b 1806f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c 1807f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d 1808f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e 1809f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f 1810f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010 1811f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014 1812f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018 1813f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c 1814f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020 1815f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024 1816f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c 1817f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030 1818f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034 1819f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c 1820f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d 1821f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064 1822f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066 1823f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068 1824f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c 1825f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e 1826f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070 1827f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074 1828f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076 1829f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088 1830f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c 1831f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e 1832f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090 1833f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094 1834f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096 1835f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2 0x0098 1836f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2 0x009c 1837f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2 0x009e 1838f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0 1839f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2 1840f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4 1841f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8 1842f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8 1843f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac 1844f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac 1845f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0 1846f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0 1847f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4 1848f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0 1849f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2 1850f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4 1851f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8 1852f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1853f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1854f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108 1855f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c 1856f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1857f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154 1858f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158 1859f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1860f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160 1861f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164 1862f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1863f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c 1864f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170 1865f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174 1866f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178 1867f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188 1868f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c 1869f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190 1870f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194 1871f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1872f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4 1873f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6 1874f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1875f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c 1876f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e 1877f0a58aa3SFeifei Xu 1878f0a58aa3SFeifei Xu 1879f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp 1880f0a58aa3SFeifei Xu // base address: 0x0 1881f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000 1882f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002 1883f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004 1884f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006 1885f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008 1886f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009 1887f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a 1888f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b 1889f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c 1890f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d 1891f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e 1892f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f 1893f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010 1894f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014 1895f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018 1896f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c 1897f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020 1898f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024 1899f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c 1900f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030 1901f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034 1902f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c 1903f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d 1904f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064 1905f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066 1906f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068 1907f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c 1908f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e 1909f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070 1910f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074 1911f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076 1912f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088 1913f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c 1914f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e 1915f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090 1916f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094 1917f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096 1918f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2 0x0098 1919f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2 0x009c 1920f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2 0x009e 1921f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0 1922f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2 1923f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4 1924f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8 1925f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8 1926f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac 1927f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac 1928f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0 1929f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0 1930f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4 1931f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0 1932f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2 1933f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4 1934f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8 1935f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1936f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1937f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108 1938f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c 1939f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1940f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154 1941f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158 1942f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 1943f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160 1944f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164 1945f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 1946f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c 1947f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170 1948f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174 1949f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178 1950f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188 1951f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c 1952f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190 1953f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194 1954f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 1955f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4 1956f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6 1957f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328 1958f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c 1959f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e 1960f0a58aa3SFeifei Xu 1961f0a58aa3SFeifei Xu 1962f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp 1963f0a58aa3SFeifei Xu // base address: 0x0 1964f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000 1965f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002 1966f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004 1967f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006 1968f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008 1969f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009 1970f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a 1971f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b 1972f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c 1973f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d 1974f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e 1975f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f 1976f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010 1977f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014 1978f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018 1979f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c 1980f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020 1981f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024 1982f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c 1983f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030 1984f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034 1985f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c 1986f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d 1987f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064 1988f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066 1989f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068 1990f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c 1991f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e 1992f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070 1993f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074 1994f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076 1995f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088 1996f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c 1997f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e 1998f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090 1999f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094 2000f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096 2001f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2 0x0098 2002f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2 0x009c 2003f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2 0x009e 2004f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0 2005f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2 2006f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4 2007f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8 2008f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8 2009f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac 2010f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac 2011f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0 2012f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0 2013f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4 2014f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0 2015f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2 2016f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4 2017f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8 2018f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2019f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2020f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108 2021f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c 2022f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2023f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154 2024f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158 2025f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2026f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160 2027f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164 2028f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2029f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c 2030f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170 2031f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174 2032f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178 2033f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188 2034f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c 2035f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190 2036f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194 2037f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2038f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4 2039f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6 2040f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2041f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c 2042f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e 2043f0a58aa3SFeifei Xu 2044f0a58aa3SFeifei Xu 2045f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp 2046f0a58aa3SFeifei Xu // base address: 0x0 2047f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000 2048f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002 2049f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004 2050f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006 2051f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008 2052f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009 2053f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a 2054f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b 2055f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c 2056f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d 2057f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e 2058f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f 2059f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010 2060f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014 2061f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018 2062f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c 2063f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020 2064f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024 2065f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c 2066f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030 2067f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034 2068f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c 2069f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d 2070f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064 2071f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066 2072f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068 2073f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c 2074f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e 2075f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070 2076f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074 2077f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076 2078f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088 2079f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c 2080f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e 2081f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090 2082f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094 2083f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096 2084f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2 0x0098 2085f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2 0x009c 2086f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2 0x009e 2087f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0 2088f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2 2089f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4 2090f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8 2091f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8 2092f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac 2093f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac 2094f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0 2095f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0 2096f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4 2097f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0 2098f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2 2099f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4 2100f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8 2101f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 2102f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 2103f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108 2104f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c 2105f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 2106f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154 2107f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158 2108f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 2109f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160 2110f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164 2111f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 2112f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c 2113f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170 2114f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174 2115f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178 2116f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188 2117f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c 2118f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190 2119f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194 2120f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 2121f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4 2122f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6 2123f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328 2124f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c 2125f0a58aa3SFeifei Xu #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e 2126f0a58aa3SFeifei Xu 2127f0a58aa3SFeifei Xu 2128f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..767] 2129f0a58aa3SFeifei Xu // base address: 0x0 2130f0a58aa3SFeifei Xu #define mmMM_INDEX 0x0000 2131f0a58aa3SFeifei Xu #define mmMM_INDEX_BASE_IDX 0 2132f0a58aa3SFeifei Xu #define mmMM_DATA 0x0001 2133f0a58aa3SFeifei Xu #define mmMM_DATA_BASE_IDX 0 2134f0a58aa3SFeifei Xu #define mmMM_INDEX_HI 0x0006 2135f0a58aa3SFeifei Xu #define mmMM_INDEX_HI_BASE_IDX 0 2136f0a58aa3SFeifei Xu 2137f0a58aa3SFeifei Xu 2138f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_pf_SYSDEC[0..767] 2139f0a58aa3SFeifei Xu // base address: 0x0 2140f0a58aa3SFeifei Xu #define mmSYSHUB_INDEX_OVLP 0x0008 2141f0a58aa3SFeifei Xu #define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 2142f0a58aa3SFeifei Xu #define mmSYSHUB_DATA_OVLP 0x0009 2143f0a58aa3SFeifei Xu #define mmSYSHUB_DATA_OVLP_BASE_IDX 0 2144f0a58aa3SFeifei Xu #define mmPCIE_INDEX 0x000c 2145f0a58aa3SFeifei Xu #define mmPCIE_INDEX_BASE_IDX 0 2146f0a58aa3SFeifei Xu #define mmPCIE_DATA 0x000d 2147f0a58aa3SFeifei Xu #define mmPCIE_DATA_BASE_IDX 0 2148f0a58aa3SFeifei Xu #define mmPCIE_INDEX2 0x000e 2149f0a58aa3SFeifei Xu #define mmPCIE_INDEX2_BASE_IDX 0 2150f0a58aa3SFeifei Xu #define mmPCIE_DATA2 0x000f 2151f0a58aa3SFeifei Xu #define mmPCIE_DATA2_BASE_IDX 0 2152f0a58aa3SFeifei Xu #define mmSBIOS_SCRATCH_0 0x0034 2153f0a58aa3SFeifei Xu #define mmSBIOS_SCRATCH_0_BASE_IDX 1 2154f0a58aa3SFeifei Xu #define mmSBIOS_SCRATCH_1 0x0035 2155f0a58aa3SFeifei Xu #define mmSBIOS_SCRATCH_1_BASE_IDX 1 2156f0a58aa3SFeifei Xu #define mmSBIOS_SCRATCH_2 0x0036 2157f0a58aa3SFeifei Xu #define mmSBIOS_SCRATCH_2_BASE_IDX 1 2158f0a58aa3SFeifei Xu #define mmSBIOS_SCRATCH_3 0x0037 2159f0a58aa3SFeifei Xu #define mmSBIOS_SCRATCH_3_BASE_IDX 1 2160f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_0 0x0038 2161f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_0_BASE_IDX 1 2162f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_1 0x0039 2163f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_1_BASE_IDX 1 2164f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_2 0x003a 2165f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_2_BASE_IDX 1 2166f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_3 0x003b 2167f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_3_BASE_IDX 1 2168f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_4 0x003c 2169f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_4_BASE_IDX 1 2170f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_5 0x003d 2171f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_5_BASE_IDX 1 2172f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_6 0x003e 2173f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_6_BASE_IDX 1 2174f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_7 0x003f 2175f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_7_BASE_IDX 1 2176f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_8 0x0040 2177f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_8_BASE_IDX 1 2178f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_9 0x0041 2179f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_9_BASE_IDX 1 2180f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_10 0x0042 2181f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_10_BASE_IDX 1 2182f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_11 0x0043 2183f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_11_BASE_IDX 1 2184f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_12 0x0044 2185f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_12_BASE_IDX 1 2186f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_13 0x0045 2187f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_13_BASE_IDX 1 2188f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_14 0x0046 2189f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_14_BASE_IDX 1 2190f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_15 0x0047 2191f0a58aa3SFeifei Xu #define mmBIOS_SCRATCH_15_BASE_IDX 1 2192f0a58aa3SFeifei Xu #define mmBIF_RLC_INTR_CNTL 0x004c 2193f0a58aa3SFeifei Xu #define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 2194f0a58aa3SFeifei Xu #define mmBIF_VCE_INTR_CNTL 0x004d 2195f0a58aa3SFeifei Xu #define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 2196f0a58aa3SFeifei Xu #define mmBIF_UVD_INTR_CNTL 0x004e 2197f0a58aa3SFeifei Xu #define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 2198f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR0 0x006c 2199f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 2200f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d 2201f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 2202f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR1 0x006e 2203f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 2204f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f 2205f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 2206f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR2 0x0070 2207f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 2208f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 2209f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 2210f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR3 0x0072 2211f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 2212f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 2213f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 2214f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR4 0x0074 2215f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 2216f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 2217f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 2218f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR5 0x0076 2219f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 2220f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 2221f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 2222f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR6 0x0078 2223f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 2224f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 2225f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 2226f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR7 0x007a 2227f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 2228f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b 2229f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 2230f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_CNTL 0x007c 2231f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 2232f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d 2233f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 2234f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e 2235f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 2236f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f 2237f0a58aa3SFeifei Xu #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 2238f0a58aa3SFeifei Xu 2239f0a58aa3SFeifei Xu 2240f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_syshub_mmreg_ind_syshubdec[32..39] 2241f0a58aa3SFeifei Xu // base address: 0x20 2242f0a58aa3SFeifei Xu #define mmSYSHUB_INDEX 0x0008 2243f0a58aa3SFeifei Xu #define mmSYSHUB_INDEX_BASE_IDX 0 2244f0a58aa3SFeifei Xu #define mmSYSHUB_DATA 0x0009 2245f0a58aa3SFeifei Xu #define mmSYSHUB_DATA_BASE_IDX 0 2246f0a58aa3SFeifei Xu 2247f0a58aa3SFeifei Xu 2248f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975] 2249f0a58aa3SFeifei Xu // base address: 0x3480 225058a50420SJim Qu #define mmRCC_BIF_STRAP0 0x0000 225158a50420SJim Qu #define mmRCC_BIF_STRAP0_BASE_IDX 2 2252f0a58aa3SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP0 0x000f 2253f0a58aa3SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 2254f0a58aa3SFeifei Xu 2255f0a58aa3SFeifei Xu 2256f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_rcc_ep_dev0_BIFDEC1[13440..14975] 2257f0a58aa3SFeifei Xu // base address: 0x3480 2258f0a58aa3SFeifei Xu #define mmEP_PCIE_SCRATCH 0x0023 2259f0a58aa3SFeifei Xu #define mmEP_PCIE_SCRATCH_BASE_IDX 2 2260f0a58aa3SFeifei Xu #define mmEP_PCIE_CNTL 0x0025 2261f0a58aa3SFeifei Xu #define mmEP_PCIE_CNTL_BASE_IDX 2 2262f0a58aa3SFeifei Xu #define mmEP_PCIE_INT_CNTL 0x0026 2263f0a58aa3SFeifei Xu #define mmEP_PCIE_INT_CNTL_BASE_IDX 2 2264f0a58aa3SFeifei Xu #define mmEP_PCIE_INT_STATUS 0x0027 2265f0a58aa3SFeifei Xu #define mmEP_PCIE_INT_STATUS_BASE_IDX 2 2266f0a58aa3SFeifei Xu #define mmEP_PCIE_RX_CNTL2 0x0028 2267f0a58aa3SFeifei Xu #define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 2268f0a58aa3SFeifei Xu #define mmEP_PCIE_BUS_CNTL 0x0029 2269f0a58aa3SFeifei Xu #define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 2270f0a58aa3SFeifei Xu #define mmEP_PCIE_CFG_CNTL 0x002a 2271f0a58aa3SFeifei Xu #define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 2272f0a58aa3SFeifei Xu #define mmEP_PCIE_TX_LTR_CNTL 0x002c 2273f0a58aa3SFeifei Xu #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 2274f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002d 2275f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 2276f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002d 2277f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 2278f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002d 2279f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 2280f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002d 2281f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 2282f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x002e 2283f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 2284f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x002e 2285f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 2286f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x002e 2287f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 2288f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x002e 2289f0a58aa3SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 2290f0a58aa3SFeifei Xu #define mmEP_PCIE_F0_DPA_CAP 0x0032 2291f0a58aa3SFeifei Xu #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 2292f0a58aa3SFeifei Xu #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0033 2293f0a58aa3SFeifei Xu #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 2294f0a58aa3SFeifei Xu #define mmEP_PCIE_F0_DPA_CNTL 0x0033 2295f0a58aa3SFeifei Xu #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 2296f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0033 2297f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 2298f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0034 2299f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 2300f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0034 2301f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 2302f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0034 2303f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 2304f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0034 2305f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 2306f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0035 2307f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 2308f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0035 2309f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 2310f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0035 2311f0a58aa3SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 2312f0a58aa3SFeifei Xu #define mmEP_PCIE_PME_CONTROL 0x0035 2313f0a58aa3SFeifei Xu #define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 2314f0a58aa3SFeifei Xu #define mmEP_PCIEP_RESERVED 0x0036 2315f0a58aa3SFeifei Xu #define mmEP_PCIEP_RESERVED_BASE_IDX 2 2316f0a58aa3SFeifei Xu #define mmEP_PCIE_TX_CNTL 0x0038 2317f0a58aa3SFeifei Xu #define mmEP_PCIE_TX_CNTL_BASE_IDX 2 2318f0a58aa3SFeifei Xu #define mmEP_PCIE_TX_REQUESTER_ID 0x0039 2319f0a58aa3SFeifei Xu #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 2320f0a58aa3SFeifei Xu #define mmEP_PCIE_ERR_CNTL 0x003a 2321f0a58aa3SFeifei Xu #define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 2322f0a58aa3SFeifei Xu #define mmEP_PCIE_RX_CNTL 0x003b 2323f0a58aa3SFeifei Xu #define mmEP_PCIE_RX_CNTL_BASE_IDX 2 2324f0a58aa3SFeifei Xu #define mmEP_PCIE_LC_SPEED_CNTL 0x003c 2325f0a58aa3SFeifei Xu #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 2326f0a58aa3SFeifei Xu 2327f0a58aa3SFeifei Xu 2328f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_rcc_dwn_dev0_BIFDEC1[13440..14975] 2329f0a58aa3SFeifei Xu // base address: 0x3480 2330f0a58aa3SFeifei Xu #define mmDN_PCIE_RESERVED 0x0040 2331f0a58aa3SFeifei Xu #define mmDN_PCIE_RESERVED_BASE_IDX 2 2332f0a58aa3SFeifei Xu #define mmDN_PCIE_SCRATCH 0x0041 2333f0a58aa3SFeifei Xu #define mmDN_PCIE_SCRATCH_BASE_IDX 2 2334f0a58aa3SFeifei Xu #define mmDN_PCIE_CNTL 0x0043 2335f0a58aa3SFeifei Xu #define mmDN_PCIE_CNTL_BASE_IDX 2 2336f0a58aa3SFeifei Xu #define mmDN_PCIE_CONFIG_CNTL 0x0044 2337f0a58aa3SFeifei Xu #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 2338f0a58aa3SFeifei Xu #define mmDN_PCIE_RX_CNTL2 0x0045 2339f0a58aa3SFeifei Xu #define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 2340f0a58aa3SFeifei Xu #define mmDN_PCIE_BUS_CNTL 0x0046 2341f0a58aa3SFeifei Xu #define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 2342f0a58aa3SFeifei Xu #define mmDN_PCIE_CFG_CNTL 0x0047 2343f0a58aa3SFeifei Xu #define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 2344f0a58aa3SFeifei Xu 2345f0a58aa3SFeifei Xu 2346f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_rcc_dwnp_dev0_BIFDEC1[13440..14975] 2347f0a58aa3SFeifei Xu // base address: 0x3480 2348f0a58aa3SFeifei Xu #define mmPCIE_ERR_CNTL 0x004f 2349f0a58aa3SFeifei Xu #define mmPCIE_ERR_CNTL_BASE_IDX 2 2350f0a58aa3SFeifei Xu #define mmPCIE_RX_CNTL 0x0050 2351f0a58aa3SFeifei Xu #define mmPCIE_RX_CNTL_BASE_IDX 2 2352f0a58aa3SFeifei Xu #define mmPCIE_LC_SPEED_CNTL 0x0051 2353f0a58aa3SFeifei Xu #define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 2354f0a58aa3SFeifei Xu #define mmPCIE_LC_CNTL2 0x0052 2355f0a58aa3SFeifei Xu #define mmPCIE_LC_CNTL2_BASE_IDX 2 2356f0a58aa3SFeifei Xu #define mmPCIEP_STRAP_MISC 0x0053 2357f0a58aa3SFeifei Xu #define mmPCIEP_STRAP_MISC_BASE_IDX 2 2358f0a58aa3SFeifei Xu #define mmLTR_MSG_INFO_FROM_EP 0x0054 2359f0a58aa3SFeifei Xu #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 2360f0a58aa3SFeifei Xu 2361f0a58aa3SFeifei Xu 2362f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1[13440..14975] 2363f0a58aa3SFeifei Xu // base address: 0x3480 2364f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_ERR_LOG 0x0085 2365f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_ERR_LOG_BASE_IDX 2 2366f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN 0x00c0 2367f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN_BASE_IDX 2 2368f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE 0x00c3 2369f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 2370f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_CONFIG_RESERVED 0x00c4 2371f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_CONFIG_RESERVED_BASE_IDX 2 2372f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 2373f0a58aa3SFeifei Xu #define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 2374f0a58aa3SFeifei Xu 2375f0a58aa3SFeifei Xu 2376f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_rcc_pf_0_BIFDEC1[13440..14975] 2377f0a58aa3SFeifei Xu // base address: 0x3480 2378f0a58aa3SFeifei Xu #define mmRCC_ERR_INT_CNTL 0x0086 2379f0a58aa3SFeifei Xu #define mmRCC_ERR_INT_CNTL_BASE_IDX 2 2380f0a58aa3SFeifei Xu #define mmRCC_BACO_CNTL_MISC 0x0087 2381f0a58aa3SFeifei Xu #define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 2382f0a58aa3SFeifei Xu #define mmRCC_RESET_EN 0x0088 2383f0a58aa3SFeifei Xu #define mmRCC_RESET_EN_BASE_IDX 2 2384f0a58aa3SFeifei Xu #define mmRCC_VDM_SUPPORT 0x0089 2385f0a58aa3SFeifei Xu #define mmRCC_VDM_SUPPORT_BASE_IDX 2 2386f0a58aa3SFeifei Xu #define mmRCC_PEER_REG_RANGE0 0x00be 2387f0a58aa3SFeifei Xu #define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 2388f0a58aa3SFeifei Xu #define mmRCC_PEER_REG_RANGE1 0x00bf 2389f0a58aa3SFeifei Xu #define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 2390f0a58aa3SFeifei Xu #define mmRCC_BUS_CNTL 0x00c1 2391f0a58aa3SFeifei Xu #define mmRCC_BUS_CNTL_BASE_IDX 2 2392f0a58aa3SFeifei Xu #define mmRCC_CONFIG_CNTL 0x00c2 2393f0a58aa3SFeifei Xu #define mmRCC_CONFIG_CNTL_BASE_IDX 2 2394f0a58aa3SFeifei Xu #define mmRCC_CONFIG_F0_BASE 0x00c6 2395f0a58aa3SFeifei Xu #define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 2396f0a58aa3SFeifei Xu #define mmRCC_CONFIG_APER_SIZE 0x00c7 2397f0a58aa3SFeifei Xu #define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 2398f0a58aa3SFeifei Xu #define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 2399f0a58aa3SFeifei Xu #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 2400f0a58aa3SFeifei Xu #define mmRCC_XDMA_LO 0x00c9 2401f0a58aa3SFeifei Xu #define mmRCC_XDMA_LO_BASE_IDX 2 2402f0a58aa3SFeifei Xu #define mmRCC_XDMA_HI 0x00ca 2403f0a58aa3SFeifei Xu #define mmRCC_XDMA_HI_BASE_IDX 2 2404f0a58aa3SFeifei Xu #define mmRCC_FEATURES_CONTROL_MISC 0x00cb 2405f0a58aa3SFeifei Xu #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 2406f0a58aa3SFeifei Xu #define mmRCC_BUSNUM_CNTL1 0x00cc 2407f0a58aa3SFeifei Xu #define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 2408f0a58aa3SFeifei Xu #define mmRCC_BUSNUM_LIST0 0x00cd 2409f0a58aa3SFeifei Xu #define mmRCC_BUSNUM_LIST0_BASE_IDX 2 2410f0a58aa3SFeifei Xu #define mmRCC_BUSNUM_LIST1 0x00ce 2411f0a58aa3SFeifei Xu #define mmRCC_BUSNUM_LIST1_BASE_IDX 2 2412f0a58aa3SFeifei Xu #define mmRCC_BUSNUM_CNTL2 0x00cf 2413f0a58aa3SFeifei Xu #define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 2414f0a58aa3SFeifei Xu #define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 2415f0a58aa3SFeifei Xu #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 2416f0a58aa3SFeifei Xu #define mmRCC_HOST_BUSNUM 0x00d1 2417f0a58aa3SFeifei Xu #define mmRCC_HOST_BUSNUM_BASE_IDX 2 2418f0a58aa3SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 2419f0a58aa3SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 2420f0a58aa3SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 2421f0a58aa3SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 2422f0a58aa3SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 2423f0a58aa3SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 2424f0a58aa3SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 2425f0a58aa3SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 2426f0a58aa3SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 2427f0a58aa3SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 2428f0a58aa3SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 2429f0a58aa3SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 2430f0a58aa3SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 2431f0a58aa3SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 2432f0a58aa3SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 2433f0a58aa3SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 2434f0a58aa3SFeifei Xu #define mmRCC_CMN_LINK_CNTL 0x00de 2435f0a58aa3SFeifei Xu #define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 2436f0a58aa3SFeifei Xu #define mmRCC_EP_REQUESTERID_RESTORE 0x00df 2437f0a58aa3SFeifei Xu #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 2438f0a58aa3SFeifei Xu #define mmRCC_LTR_LSWITCH_CNTL 0x00e0 2439f0a58aa3SFeifei Xu #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 2440f0a58aa3SFeifei Xu #define mmRCC_MH_ARB_CNTL 0x00e1 2441f0a58aa3SFeifei Xu #define mmRCC_MH_ARB_CNTL_BASE_IDX 2 2442f0a58aa3SFeifei Xu 2443f0a58aa3SFeifei Xu 2444f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1[13440..14975] 2445f0a58aa3SFeifei Xu // base address: 0x3480 2446f0a58aa3SFeifei Xu #define mmBIF_MM_INDACCESS_CNTL 0x00e6 2447f0a58aa3SFeifei Xu #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 2448f0a58aa3SFeifei Xu #define mmBUS_CNTL 0x00e7 2449f0a58aa3SFeifei Xu #define mmBUS_CNTL_BASE_IDX 2 2450f0a58aa3SFeifei Xu #define mmBIF_SCRATCH0 0x00e8 2451f0a58aa3SFeifei Xu #define mmBIF_SCRATCH0_BASE_IDX 2 2452f0a58aa3SFeifei Xu #define mmBIF_SCRATCH1 0x00e9 2453f0a58aa3SFeifei Xu #define mmBIF_SCRATCH1_BASE_IDX 2 2454f0a58aa3SFeifei Xu #define mmBX_RESET_EN 0x00ed 2455f0a58aa3SFeifei Xu #define mmBX_RESET_EN_BASE_IDX 2 2456f0a58aa3SFeifei Xu #define mmMM_CFGREGS_CNTL 0x00ee 2457f0a58aa3SFeifei Xu #define mmMM_CFGREGS_CNTL_BASE_IDX 2 2458f0a58aa3SFeifei Xu #define mmBX_RESET_CNTL 0x00f0 2459f0a58aa3SFeifei Xu #define mmBX_RESET_CNTL_BASE_IDX 2 2460f0a58aa3SFeifei Xu #define mmINTERRUPT_CNTL 0x00f1 2461f0a58aa3SFeifei Xu #define mmINTERRUPT_CNTL_BASE_IDX 2 2462f0a58aa3SFeifei Xu #define mmINTERRUPT_CNTL2 0x00f2 2463f0a58aa3SFeifei Xu #define mmINTERRUPT_CNTL2_BASE_IDX 2 2464f0a58aa3SFeifei Xu #define mmCLKREQB_PAD_CNTL 0x00f8 2465f0a58aa3SFeifei Xu #define mmCLKREQB_PAD_CNTL_BASE_IDX 2 2466f0a58aa3SFeifei Xu #define mmBIF_FEATURES_CONTROL_MISC 0x00fb 2467f0a58aa3SFeifei Xu #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 2468f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_CNTL 0x00fc 2469f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_CNTL_BASE_IDX 2 2470f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_INT_CNTL 0x00fd 2471f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 2472f0a58aa3SFeifei Xu #define mmBIF_FB_EN 0x00ff 2473f0a58aa3SFeifei Xu #define mmBIF_FB_EN_BASE_IDX 2 2474f0a58aa3SFeifei Xu #define mmBIF_BUSY_DELAY_CNTR 0x0100 2475f0a58aa3SFeifei Xu #define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2 2476f0a58aa3SFeifei Xu #define mmBIF_MST_TRANS_PENDING_VF 0x0109 2477f0a58aa3SFeifei Xu #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 2478f0a58aa3SFeifei Xu #define mmBIF_SLV_TRANS_PENDING_VF 0x010a 2479f0a58aa3SFeifei Xu #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 2480f0a58aa3SFeifei Xu #define mmBACO_CNTL 0x010b 2481f0a58aa3SFeifei Xu #define mmBACO_CNTL_BASE_IDX 2 2482f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIME0 0x010c 2483f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 2484f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIMER1 0x010d 2485f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 2486f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIMER2 0x010e 2487f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 2488f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIMER3 0x010f 2489f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 2490f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIMER4 0x0110 2491f0a58aa3SFeifei Xu #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 2492f0a58aa3SFeifei Xu #define mmMEM_TYPE_CNTL 0x0111 2493f0a58aa3SFeifei Xu #define mmMEM_TYPE_CNTL_BASE_IDX 2 2494f0a58aa3SFeifei Xu #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0113 2495f0a58aa3SFeifei Xu #define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 2 2496f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX0_LOWER 0x0114 2497f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 2 2498f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX0_UPPER 0x0115 2499f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 2 2500f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX1_LOWER 0x0116 2501f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 2 2502f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX1_UPPER 0x0117 2503f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 2 2504f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX2_LOWER 0x0118 2505f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 2 2506f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX2_UPPER 0x0119 2507f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 2 2508f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX3_LOWER 0x011a 2509f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 2 2510f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX3_UPPER 0x011b 2511f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 2 2512f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX4_LOWER 0x011c 2513f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 2 2514f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX4_UPPER 0x011d 2515f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 2 2516f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX5_LOWER 0x011e 2517f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 2 2518f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX5_UPPER 0x011f 2519f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 2 2520f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV1_LOWER 0x0120 2521f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 2 2522f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV1_UPPER 0x0121 2523f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 2 2524f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV2_LOWER 0x0122 2525f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 2 2526f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV2_UPPER 0x0123 2527f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 2 2528f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV3_LOWER 0x0124 2529f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 2 2530f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV3_UPPER 0x0125 2531f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 2 2532f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV4_LOWER 0x0126 2533f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 2 2534f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV4_UPPER 0x0127 2535f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 2 2536f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_FB_CMP 0x0128 2537f0a58aa3SFeifei Xu #define mmBIF_VDDGFX_FB_CMP_BASE_IDX 2 2538f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0129 2539f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 2 2540f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x012a 2541f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 2 2542f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x012b 2543f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 2 2544f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x012c 2545f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 2 2546f0a58aa3SFeifei Xu #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d 2547f0a58aa3SFeifei Xu #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 2548f0a58aa3SFeifei Xu #define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e 2549f0a58aa3SFeifei Xu #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 2550f0a58aa3SFeifei Xu #define mmBIF_RB_CNTL 0x012f 2551f0a58aa3SFeifei Xu #define mmBIF_RB_CNTL_BASE_IDX 2 2552f0a58aa3SFeifei Xu #define mmBIF_RB_BASE 0x0130 2553f0a58aa3SFeifei Xu #define mmBIF_RB_BASE_BASE_IDX 2 2554f0a58aa3SFeifei Xu #define mmBIF_RB_RPTR 0x0131 2555f0a58aa3SFeifei Xu #define mmBIF_RB_RPTR_BASE_IDX 2 2556f0a58aa3SFeifei Xu #define mmBIF_RB_WPTR 0x0132 2557f0a58aa3SFeifei Xu #define mmBIF_RB_WPTR_BASE_IDX 2 2558f0a58aa3SFeifei Xu #define mmBIF_RB_WPTR_ADDR_HI 0x0133 2559f0a58aa3SFeifei Xu #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 2560f0a58aa3SFeifei Xu #define mmBIF_RB_WPTR_ADDR_LO 0x0134 2561f0a58aa3SFeifei Xu #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 2562f0a58aa3SFeifei Xu #define mmMAILBOX_INDEX 0x0135 2563f0a58aa3SFeifei Xu #define mmMAILBOX_INDEX_BASE_IDX 2 2564f0a58aa3SFeifei Xu #define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 2565f0a58aa3SFeifei Xu #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 2566f0a58aa3SFeifei Xu #define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 2567f0a58aa3SFeifei Xu #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 2568f0a58aa3SFeifei Xu #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 2569f0a58aa3SFeifei Xu #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 2570f0a58aa3SFeifei Xu #define mmBIF_PERSTB_PAD_CNTL 0x0148 2571f0a58aa3SFeifei Xu #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 2572f0a58aa3SFeifei Xu #define mmBIF_PX_EN_PAD_CNTL 0x0149 2573f0a58aa3SFeifei Xu #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 2574f0a58aa3SFeifei Xu #define mmBIF_REFPADKIN_PAD_CNTL 0x014a 2575f0a58aa3SFeifei Xu #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 2576f0a58aa3SFeifei Xu #define mmBIF_CLKREQB_PAD_CNTL 0x014b 2577f0a58aa3SFeifei Xu #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 2578f0a58aa3SFeifei Xu 2579f0a58aa3SFeifei Xu 2580f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1 2581f0a58aa3SFeifei Xu // base address: 0x0 2582f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_BIF_BME_STATUS 0x00eb 2583f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 2584f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec 2585f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2586f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2587f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2588f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2589f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2590f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2591f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2592f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2593f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2594f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2595f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2596f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 2597f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2598f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 2599f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2600f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 2601f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 2602f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 2603f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2604f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 2605f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2606f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 2607f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2608f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 2609f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2610f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 2611f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2612f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 2613f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2614f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 2615f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2616f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 2617f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2618f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_CONTROL 0x013e 2619f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 2620f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f 2621f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 2622f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 2623f0a58aa3SFeifei Xu #define mmBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 2624f0a58aa3SFeifei Xu 2625f0a58aa3SFeifei Xu 2626f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_gdc_GDCDEC[14976..15487] 2627f0a58aa3SFeifei Xu // base address: 0x3a80 2628f0a58aa3SFeifei Xu #define mmNGDC_SDP_PORT_CTRL 0x01c2 2629f0a58aa3SFeifei Xu #define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 2630f0a58aa3SFeifei Xu #define mmSHUB_REGS_IF_CTL 0x01c3 2631f0a58aa3SFeifei Xu #define mmSHUB_REGS_IF_CTL_BASE_IDX 2 2632f0a58aa3SFeifei Xu #define mmNGDC_RESERVED_0 0x01cb 2633f0a58aa3SFeifei Xu #define mmNGDC_RESERVED_0_BASE_IDX 2 2634f0a58aa3SFeifei Xu #define mmNGDC_RESERVED_1 0x01cc 2635f0a58aa3SFeifei Xu #define mmNGDC_RESERVED_1_BASE_IDX 2 2636f0a58aa3SFeifei Xu #define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd 2637f0a58aa3SFeifei Xu #define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 2638f0a58aa3SFeifei Xu #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 2639f0a58aa3SFeifei Xu #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 2640f0a58aa3SFeifei Xu #define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 2641f0a58aa3SFeifei Xu #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 2642f0a58aa3SFeifei Xu #define mmBIF_IH_DOORBELL_RANGE 0x01d2 2643f0a58aa3SFeifei Xu #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 2644f0a58aa3SFeifei Xu #define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 2645f0a58aa3SFeifei Xu #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 2646f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_FENCE_CNTL 0x01de 2647f0a58aa3SFeifei Xu #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 2648f0a58aa3SFeifei Xu #define mmS2A_MISC_CNTL 0x01df 2649f0a58aa3SFeifei Xu #define mmS2A_MISC_CNTL_BASE_IDX 2 2650f0a58aa3SFeifei Xu 2651f0a58aa3SFeifei Xu 2652f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_rcc_pf_0_BIFDEC2 2653f0a58aa3SFeifei Xu // base address: 0x0 2654f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO 0x0400 2655f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 2656f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI 0x0401 2657f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 2658f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA 0x0402 2659f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 2660f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL 0x0403 2661f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 2662f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO 0x0404 2663f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 2664f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI 0x0405 2665f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 2666f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA 0x0406 2667f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 2668f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL 0x0407 2669f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 2670f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO 0x0408 2671f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 2672f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI 0x0409 2673f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 2674f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA 0x040a 2675f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 2676f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL 0x040b 2677f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 2678f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_PBA 0x0800 2679f0a58aa3SFeifei Xu #define mmRCC_PF_0_GFXMSIX_PBA_BASE_IDX 3 2680f0a58aa3SFeifei Xu 2681f0a58aa3SFeifei Xu 2682f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..255] 2683f0a58aa3SFeifei Xu // base address: 0x0 2684f0a58aa3SFeifei Xu //#define mmBIF_BX_PF_MM_INDEX 0x0000 2685f0a58aa3SFeifei Xu //#define mmBIF_BX_PF_MM_DATA 0x0001 2686f0a58aa3SFeifei Xu //#define mmBIF_BX_PF_MM_INDEX_HI 0x0006 2687f0a58aa3SFeifei Xu 2688f0a58aa3SFeifei Xu 2689f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 2690f0a58aa3SFeifei Xu // base address: 0x0 2691f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 2692f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 2693f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 2694f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 2695f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 2696f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 2697f0a58aa3SFeifei Xu 2698f0a58aa3SFeifei Xu 2699f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_rcc_dev0_epf0_vf0_BIFPFVFDEC1 2700f0a58aa3SFeifei Xu // base address: 0x0 2701f0a58aa3SFeifei Xu 2702f0a58aa3SFeifei Xu 2703f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 2704f0a58aa3SFeifei Xu // base address: 0x0 2705f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb 2706f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 2707f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec 2708f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2709f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2710f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2711f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2712f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2713f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2714f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2715f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2716f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2717f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2718f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2719f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 2720f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2721f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 2722f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2723f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 2724f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 2725f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 2726f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2727f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 2728f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2729f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 2730f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2731f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 2732f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2733f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 2734f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2735f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 2736f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2737f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 2738f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2739f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 2740f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2741f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e 2742f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 2743f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f 2744f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 2745f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 2746f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 2747f0a58aa3SFeifei Xu 2748f0a58aa3SFeifei Xu 2749f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 2750f0a58aa3SFeifei Xu // base address: 0x0 2751f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 2752f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 2753f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 2754f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 2755f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 2756f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 2757f0a58aa3SFeifei Xu 2758f0a58aa3SFeifei Xu 2759f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 2760f0a58aa3SFeifei Xu // base address: 0x0 2761f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb 2762f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 2763f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec 2764f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2765f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2766f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2767f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2768f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2769f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2770f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2771f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2772f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2773f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2774f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2775f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 2776f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2777f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 2778f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2779f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 2780f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 2781f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 2782f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2783f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 2784f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2785f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 2786f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2787f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 2788f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2789f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a 2790f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2791f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b 2792f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2793f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c 2794f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2795f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d 2796f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2797f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e 2798f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 2799f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f 2800f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 2801f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 2802f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 2803f0a58aa3SFeifei Xu 2804f0a58aa3SFeifei Xu 2805f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 2806f0a58aa3SFeifei Xu // base address: 0x0 2807f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 2808f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 2809f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 2810f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 2811f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 2812f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 2813f0a58aa3SFeifei Xu 2814f0a58aa3SFeifei Xu 2815f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 2816f0a58aa3SFeifei Xu // base address: 0x0 2817f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb 2818f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 2819f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec 2820f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2821f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2822f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2823f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2824f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2825f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2826f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2827f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2828f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2829f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2830f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2831f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 2832f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2833f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 2834f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2835f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 2836f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 2837f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 2838f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2839f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 2840f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2841f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 2842f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2843f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 2844f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2845f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a 2846f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2847f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b 2848f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2849f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c 2850f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2851f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d 2852f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2853f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e 2854f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 2855f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f 2856f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 2857f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 2858f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 2859f0a58aa3SFeifei Xu 2860f0a58aa3SFeifei Xu 2861f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 2862f0a58aa3SFeifei Xu // base address: 0x0 2863f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 2864f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 2865f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 2866f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 2867f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 2868f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 2869f0a58aa3SFeifei Xu 2870f0a58aa3SFeifei Xu 2871f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 2872f0a58aa3SFeifei Xu // base address: 0x0 2873f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb 2874f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 2875f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec 2876f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2877f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2878f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2879f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2880f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2881f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2882f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2883f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2884f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2885f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2886f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2887f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 2888f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2889f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 2890f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2891f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 2892f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 2893f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 2894f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2895f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 2896f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2897f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 2898f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2899f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 2900f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2901f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a 2902f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2903f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b 2904f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2905f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c 2906f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2907f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d 2908f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2909f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e 2910f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 2911f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f 2912f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 2913f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 2914f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 2915f0a58aa3SFeifei Xu 2916f0a58aa3SFeifei Xu 2917f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 2918f0a58aa3SFeifei Xu // base address: 0x0 2919f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 2920f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 2921f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 2922f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 2923f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 2924f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 2925f0a58aa3SFeifei Xu 2926f0a58aa3SFeifei Xu 2927f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 2928f0a58aa3SFeifei Xu // base address: 0x0 2929f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb 2930f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 2931f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec 2932f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2933f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2934f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2935f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2936f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2937f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2938f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2939f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2940f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2941f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2942f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2943f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 2944f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 2945f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 2946f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 2947f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 2948f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 2949f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 2950f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 2951f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 2952f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 2953f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 2954f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 2955f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 2956f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 2957f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a 2958f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 2959f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b 2960f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 2961f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c 2962f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 2963f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d 2964f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 2965f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e 2966f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 2967f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f 2968f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 2969f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 2970f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 2971f0a58aa3SFeifei Xu 2972f0a58aa3SFeifei Xu 2973f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 2974f0a58aa3SFeifei Xu // base address: 0x0 2975f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 2976f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 2977f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 2978f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 2979f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 2980f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 2981f0a58aa3SFeifei Xu 2982f0a58aa3SFeifei Xu 2983f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 2984f0a58aa3SFeifei Xu // base address: 0x0 2985f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb 2986f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 2987f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec 2988f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 2989f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 2990f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 2991f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 2992f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 2993f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 2994f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 2995f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 2996f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2997f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 2998f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 2999f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 3000f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3001f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 3002f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3003f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 3004f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 3005f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 3006f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3007f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 3008f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3009f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 3010f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3011f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 3012f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3013f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a 3014f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3015f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b 3016f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3017f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c 3018f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3019f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d 3020f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3021f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e 3022f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 3023f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f 3024f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 3025f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 3026f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 3027f0a58aa3SFeifei Xu 3028f0a58aa3SFeifei Xu 3029f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 3030f0a58aa3SFeifei Xu // base address: 0x0 3031f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 3032f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 3033f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 3034f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 3035f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 3036f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 3037f0a58aa3SFeifei Xu 3038f0a58aa3SFeifei Xu 3039f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 3040f0a58aa3SFeifei Xu // base address: 0x0 3041f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb 3042f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 3043f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec 3044f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3045f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3046f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3047f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3048f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3049f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3050f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3051f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3052f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3053f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3054f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3055f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 3056f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3057f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 3058f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3059f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 3060f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 3061f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 3062f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3063f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 3064f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3065f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 3066f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3067f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 3068f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3069f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a 3070f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3071f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b 3072f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3073f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c 3074f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3075f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d 3076f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3077f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e 3078f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 3079f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f 3080f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 3081f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 3082f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 3083f0a58aa3SFeifei Xu 3084f0a58aa3SFeifei Xu 3085f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 3086f0a58aa3SFeifei Xu // base address: 0x0 3087f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 3088f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 3089f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 3090f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 3091f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 3092f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 3093f0a58aa3SFeifei Xu 3094f0a58aa3SFeifei Xu 3095f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 3096f0a58aa3SFeifei Xu // base address: 0x0 3097f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb 3098f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 3099f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec 3100f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3101f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3102f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3103f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3104f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3105f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3106f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3107f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3108f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3109f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3110f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3111f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 3112f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3113f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 3114f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3115f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 3116f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 3117f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 3118f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3119f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 3120f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3121f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 3122f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3123f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 3124f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3125f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a 3126f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3127f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b 3128f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3129f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c 3130f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3131f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d 3132f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3133f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e 3134f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 3135f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f 3136f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 3137f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 3138f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 3139f0a58aa3SFeifei Xu 3140f0a58aa3SFeifei Xu 3141f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 3142f0a58aa3SFeifei Xu // base address: 0x0 3143f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 3144f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 3145f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 3146f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 3147f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 3148f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 3149f0a58aa3SFeifei Xu 3150f0a58aa3SFeifei Xu 3151f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 3152f0a58aa3SFeifei Xu // base address: 0x0 3153f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb 3154f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 3155f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec 3156f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3157f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3158f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3159f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3160f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3161f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3162f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3163f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3164f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3165f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3166f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3167f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 3168f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3169f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 3170f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3171f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 3172f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 3173f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 3174f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3175f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 3176f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3177f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 3178f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3179f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 3180f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3181f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a 3182f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3183f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b 3184f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3185f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c 3186f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3187f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d 3188f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3189f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e 3190f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 3191f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f 3192f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 3193f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 3194f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 3195f0a58aa3SFeifei Xu 3196f0a58aa3SFeifei Xu 3197f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 3198f0a58aa3SFeifei Xu // base address: 0x0 3199f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 3200f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 3201f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 3202f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 3203f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 3204f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 3205f0a58aa3SFeifei Xu 3206f0a58aa3SFeifei Xu 3207f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 3208f0a58aa3SFeifei Xu // base address: 0x0 3209f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb 3210f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 3211f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec 3212f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3213f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3214f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3215f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3216f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3217f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3218f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3219f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3220f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3221f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3222f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3223f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 3224f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3225f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 3226f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3227f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 3228f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 3229f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 3230f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3231f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 3232f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3233f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 3234f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3235f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 3236f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3237f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a 3238f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3239f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b 3240f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3241f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c 3242f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3243f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d 3244f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3245f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e 3246f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 3247f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f 3248f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 3249f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 3250f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 3251f0a58aa3SFeifei Xu 3252f0a58aa3SFeifei Xu 3253f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 3254f0a58aa3SFeifei Xu // base address: 0x0 3255f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 3256f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 3257f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 3258f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 3259f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 3260f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 3261f0a58aa3SFeifei Xu 3262f0a58aa3SFeifei Xu 3263f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 3264f0a58aa3SFeifei Xu // base address: 0x0 3265f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb 3266f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 3267f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec 3268f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3269f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3270f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3271f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3272f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3273f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3274f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3275f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3276f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3277f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3278f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3279f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 3280f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3281f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 3282f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3283f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 3284f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 3285f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 3286f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3287f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 3288f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3289f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 3290f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3291f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 3292f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3293f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a 3294f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3295f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b 3296f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3297f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c 3298f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3299f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d 3300f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3301f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e 3302f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 3303f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f 3304f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 3305f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 3306f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 3307f0a58aa3SFeifei Xu 3308f0a58aa3SFeifei Xu 3309f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 3310f0a58aa3SFeifei Xu // base address: 0x0 3311f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 3312f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 3313f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 3314f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 3315f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 3316f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 3317f0a58aa3SFeifei Xu 3318f0a58aa3SFeifei Xu 3319f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 3320f0a58aa3SFeifei Xu // base address: 0x0 3321f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb 3322f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 3323f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec 3324f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3325f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3326f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3327f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3328f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3329f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3330f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3331f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3332f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3333f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3334f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3335f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 3336f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3337f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 3338f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3339f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 3340f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 3341f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 3342f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3343f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 3344f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3345f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 3346f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3347f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 3348f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3349f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a 3350f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3351f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b 3352f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3353f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c 3354f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3355f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d 3356f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3357f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e 3358f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 3359f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f 3360f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 3361f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 3362f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 3363f0a58aa3SFeifei Xu 3364f0a58aa3SFeifei Xu 3365f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 3366f0a58aa3SFeifei Xu // base address: 0x0 3367f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 3368f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 3369f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 3370f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 3371f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 3372f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 3373f0a58aa3SFeifei Xu 3374f0a58aa3SFeifei Xu 3375f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 3376f0a58aa3SFeifei Xu // base address: 0x0 3377f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb 3378f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 3379f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec 3380f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3381f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3382f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3383f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3384f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3385f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3386f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3387f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3388f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3389f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3390f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3391f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 3392f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3393f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 3394f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3395f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 3396f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 3397f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 3398f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3399f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 3400f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3401f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 3402f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3403f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 3404f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3405f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a 3406f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3407f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b 3408f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3409f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c 3410f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3411f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d 3412f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3413f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e 3414f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 3415f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f 3416f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 3417f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 3418f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 3419f0a58aa3SFeifei Xu 3420f0a58aa3SFeifei Xu 3421f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 3422f0a58aa3SFeifei Xu // base address: 0x0 3423f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 3424f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 3425f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 3426f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 3427f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 3428f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 3429f0a58aa3SFeifei Xu 3430f0a58aa3SFeifei Xu 3431f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 3432f0a58aa3SFeifei Xu // base address: 0x0 3433f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb 3434f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 3435f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec 3436f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3437f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3438f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3439f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3440f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3441f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3442f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3443f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3444f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3445f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3446f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3447f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 3448f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3449f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 3450f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3451f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 3452f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 3453f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 3454f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3455f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 3456f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3457f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 3458f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3459f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 3460f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3461f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a 3462f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3463f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b 3464f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3465f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c 3466f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3467f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d 3468f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3469f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e 3470f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 3471f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f 3472f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 3473f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 3474f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 3475f0a58aa3SFeifei Xu 3476f0a58aa3SFeifei Xu 3477f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 3478f0a58aa3SFeifei Xu // base address: 0x0 3479f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 3480f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 3481f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 3482f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 3483f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 3484f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 3485f0a58aa3SFeifei Xu 3486f0a58aa3SFeifei Xu 3487f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 3488f0a58aa3SFeifei Xu // base address: 0x0 3489f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb 3490f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 3491f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec 3492f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3493f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3494f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3495f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3496f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3497f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3498f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3499f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3500f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3501f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3502f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3503f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 3504f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3505f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 3506f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3507f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 3508f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 3509f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 3510f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3511f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 3512f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3513f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 3514f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3515f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 3516f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3517f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a 3518f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3519f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b 3520f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3521f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c 3522f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3523f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d 3524f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3525f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e 3526f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 3527f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f 3528f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 3529f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 3530f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 3531f0a58aa3SFeifei Xu 3532f0a58aa3SFeifei Xu 3533f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 3534f0a58aa3SFeifei Xu // base address: 0x0 3535f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 3536f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 3537f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 3538f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 3539f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 3540f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 3541f0a58aa3SFeifei Xu 3542f0a58aa3SFeifei Xu 3543f0a58aa3SFeifei Xu // addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 3544f0a58aa3SFeifei Xu // base address: 0x0 3545f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb 3546f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 3547f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec 3548f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 3549f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 3550f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 3551f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 3552f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 3553f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 3554f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 3555f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 3556f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3557f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 3558f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 3559f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 3560f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 3561f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 3562f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 3563f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 3564f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 3565f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 3566f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 3567f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 3568f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 3569f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 3570f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 3571f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 3572f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 3573f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a 3574f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 3575f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b 3576f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 3577f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c 3578f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 3579f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d 3580f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 3581f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e 3582f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 3583f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f 3584f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 3585f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 3586f0a58aa3SFeifei Xu #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 3587f0a58aa3SFeifei Xu 3588f0a58aa3SFeifei Xu 3589f0a58aa3SFeifei Xu // addressBlock: syshub_mmreg_ind_syshubind 3590f0a58aa3SFeifei Xu // base address: 0x0 3591f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK 0x10000 3592f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 3593f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 3594f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c 3595f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 3596f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 3597f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL 0x10018 3598f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL 0x1001c 3599f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL 0x10020 3600f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL 0x10024 3601f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL 0x10028 3602f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL 0x1002c 3603f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL 0x10030 3604f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL 0x10034 3605f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL 0x10100 3606f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL 0x10104 3607f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL 0x10108 3608f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL 0x1010c 3609f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL 0x10110 3610f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL 0x10114 3611f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL 0x10118 3612f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL 0x1011c 3613f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL 0x10300 3614f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE 0x10308 3615f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER 0x1030c 3616f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK 0x10310 3617f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH 0x10f00 3618f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK 0x10f04 3619f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 3620f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 3621f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 3622f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c 3623f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 3624f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 3625f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL 0x11018 3626f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL 0x1101c 3627f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL 0x11020 3628f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL 0x11024 3629f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL 0x11028 3630f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL 0x1102c 3631f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL 0x11030 3632f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL 0x11034 3633f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL 0x11038 3634f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL 0x1103c 3635f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK 0x11040 3636f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD 0x20108 3637f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS 0x30008 3638f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS 0x31008 3639f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS 0x32008 3640f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD 0x40108 3641f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD 0x50008 3642f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD 0x51008 3643f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD 0x52008 3644f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD 0x53008 3645f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD 0x54008 3646f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD 0x60108 3647f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD 0x61108 3648f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD 0x62108 3649f0a58aa3SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS 0x70008 3650f0a58aa3SFeifei Xu 3651f0a58aa3SFeifei Xu #endif 3652