151199920SFeifei Xu /* 251199920SFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 351199920SFeifei Xu * 451199920SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 551199920SFeifei Xu * copy of this software and associated documentation files (the "Software"), 651199920SFeifei Xu * to deal in the Software without restriction, including without limitation 751199920SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 851199920SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 951199920SFeifei Xu * Software is furnished to do so, subject to the following conditions: 1051199920SFeifei Xu * 1151199920SFeifei Xu * The above copyright notice and this permission notice shall be included 1251199920SFeifei Xu * in all copies or substantial portions of the Software. 1351199920SFeifei Xu * 1451199920SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1551199920SFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1651199920SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1751199920SFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 1851199920SFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1951199920SFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2051199920SFeifei Xu */ 2151199920SFeifei Xu #ifndef _nbio_7_0_OFFSET_HEADER 2251199920SFeifei Xu #define _nbio_7_0_OFFSET_HEADER 2351199920SFeifei Xu 2451199920SFeifei Xu 2551199920SFeifei Xu 2651199920SFeifei Xu // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec 2751199920SFeifei Xu // base address: 0x0 2851199920SFeifei Xu #define cfgNB_NBCFG0_NB_VENDOR_ID 0x0000 2951199920SFeifei Xu #define cfgNB_NBCFG0_NB_DEVICE_ID 0x0002 3051199920SFeifei Xu #define cfgNB_NBCFG0_NB_COMMAND 0x0004 3151199920SFeifei Xu #define cfgNB_NBCFG0_NB_STATUS 0x0006 3251199920SFeifei Xu #define cfgNB_NBCFG0_NB_REVISION_ID 0x0008 3351199920SFeifei Xu #define cfgNB_NBCFG0_NB_REGPROG_INF 0x0009 3451199920SFeifei Xu #define cfgNB_NBCFG0_NB_SUB_CLASS 0x000a 3551199920SFeifei Xu #define cfgNB_NBCFG0_NB_BASE_CODE 0x000b 3651199920SFeifei Xu #define cfgNB_NBCFG0_NB_CACHE_LINE 0x000c 3751199920SFeifei Xu #define cfgNB_NBCFG0_NB_LATENCY 0x000d 3851199920SFeifei Xu #define cfgNB_NBCFG0_NB_HEADER 0x000e 3951199920SFeifei Xu #define cfgNB_NBCFG0_NB_ADAPTER_ID 0x002c 4051199920SFeifei Xu #define cfgNB_NBCFG0_NB_CAPABILITIES_PTR 0x0034 4151199920SFeifei Xu #define cfgNB_NBCFG0_NB_HEADER_W 0x0048 4251199920SFeifei Xu #define cfgNB_NBCFG0_NB_PCI_CTRL 0x004c 4351199920SFeifei Xu #define cfgNB_NBCFG0_NB_ADAPTER_ID_W 0x0050 4451199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_0 0x005c 4551199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_0 0x0060 4651199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_DATA_0 0x0064 4751199920SFeifei Xu #define cfgNB_NBCFG0_NBCFG_SCRATCH_0 0x0068 4851199920SFeifei Xu #define cfgNB_NBCFG0_NBCFG_SCRATCH_1 0x006c 4951199920SFeifei Xu #define cfgNB_NBCFG0_NBCFG_SCRATCH_2 0x0070 5051199920SFeifei Xu #define cfgNB_NBCFG0_NBCFG_SCRATCH_3 0x0074 5151199920SFeifei Xu #define cfgNB_NBCFG0_NBCFG_SCRATCH_4 0x0078 5251199920SFeifei Xu #define cfgNB_NBCFG0_NB_PCI_ARB 0x0084 5351199920SFeifei Xu #define cfgNB_NBCFG0_NB_DRAM_SLOT1_BASE 0x0088 5451199920SFeifei Xu #define cfgNB_NBCFG0_NB_TOP_OF_DRAM_SLOT1 0x0090 5551199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_1 0x009c 5651199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_1 0x00a0 5751199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_DATA_1 0x00a4 5851199920SFeifei Xu #define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX0 0x00a8 5951199920SFeifei Xu #define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX1 0x00ac 6051199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_2 0x00b4 6151199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_2 0x00b8 6251199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_DATA_2 0x00bc 6351199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_3 0x00c0 6451199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_3 0x00c4 6551199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_DATA_3 0x00c8 6651199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_4 0x00cc 6751199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_4 0x00d0 6851199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_DATA_4 0x00d4 6951199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_5 0x00dc 7051199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_5 0x00e0 7151199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_DATA_5 0x00e4 7251199920SFeifei Xu #define cfgNB_NBCFG0_NB_PERF_CNT_CTRL 0x00f4 7351199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_INDEX_6 0x00f8 7451199920SFeifei Xu #define cfgNB_NBCFG0_NB_SMN_DATA_6 0x00fc 7551199920SFeifei Xu 7651199920SFeifei Xu 7751199920SFeifei Xu // addressBlock: nbio_iohub_iommu_l2_iommul2cfg 7851199920SFeifei Xu // base address: 0x0 7951199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_VENDOR_ID 0x0000 8051199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_DEVICE_ID 0x0002 8151199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_COMMAND 0x0004 8251199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_STATUS 0x0006 8351199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_REVISION_ID 0x0008 8451199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_REGPROG_INF 0x0009 8551199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_SUB_CLASS 0x000a 8651199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_BASE_CODE 0x000b 8751199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_CACHE_LINE 0x000c 8851199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_LATENCY 0x000d 8951199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_HEADER 0x000e 9051199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_BIST 0x000f 9151199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID 0x002c 9251199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_CAPABILITIES_PTR 0x0034 9351199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_INTERRUPT_LINE 0x003c 9451199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_INTERRUPT_PIN 0x003d 9551199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_CAP_HEADER 0x0040 9651199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_CAP_BASE_LO 0x0044 9751199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_CAP_BASE_HI 0x0048 9851199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_CAP_RANGE 0x004c 9951199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_CAP_MISC 0x0050 10051199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_CAP_MISC_1 0x0054 10151199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_MSI_CAP 0x0064 10251199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_LO 0x0068 10351199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_HI 0x006c 10451199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_MSI_DATA 0x0070 10551199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_MSI_MAPPING_CAP 0x0074 10651199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_W 0x0078 10751199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_CONTROL_W 0x007c 10851199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL0_W 0x0080 10951199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL1_W 0x0084 11051199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_RANGE_W 0x0088 11151199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_DSFX_CONTROL 0x008c 11251199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_DSSX_DUMMY_0 0x0090 11351199920SFeifei Xu #define cfgIOMMU_L2_0_IOMMU_DSCX_DUMMY_0 0x0094 11451199920SFeifei Xu #define cfgIOMMU_L2_0_L2B_POISON_DVM_CNTRL 0x0098 11551199920SFeifei Xu #define cfgIOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control 0x009c 11651199920SFeifei Xu #define cfgIOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control 0x00a0 11751199920SFeifei Xu #define cfgIOMMU_L2_0_SMMU_MMIO_IDR0_W 0x00a4 11851199920SFeifei Xu #define cfgIOMMU_L2_0_SMMU_MMIO_IDR1_W 0x00a8 11951199920SFeifei Xu #define cfgIOMMU_L2_0_SMMU_MMIO_IDR2_W 0x00ac 12051199920SFeifei Xu #define cfgIOMMU_L2_0_SMMU_MMIO_IDR3_W 0x00b0 12151199920SFeifei Xu #define cfgIOMMU_L2_0_SMMU_MMIO_IDR5_W 0x00b8 12251199920SFeifei Xu #define cfgIOMMU_L2_0_SMMU_MMIO_IIDR_W 0x00bc 12351199920SFeifei Xu #define cfgIOMMU_L2_0_SMMU_AIDR_W 0x00c0 12451199920SFeifei Xu 12551199920SFeifei Xu 12651199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp 12751199920SFeifei Xu // base address: 0x0 12851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 12951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_DEVICE_ID 0x0002 13051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_COMMAND 0x0004 13151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_STATUS 0x0006 13251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_REVISION_ID 0x0008 13351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0009 13451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SUB_CLASS 0x000a 13551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_BASE_CLASS 0x000b 13651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_CACHE_LINE 0x000c 13751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_LATENCY 0x000d 13851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_HEADER 0x000e 13951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_BIST 0x000f 14051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0010 14151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0018 14251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x001c 14351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x001e 14451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0020 14551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0024 14651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x0028 14751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x002c 14851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x0030 14951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_CAP_PTR 0x0034 15051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x003c 15151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x003d 15251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x003e 15351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0040 15451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0050 15551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PMI_CAP 0x0052 15651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0054 15751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0058 15851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP 0x005a 15951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP 0x005c 16051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0060 16151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0062 16251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_LINK_CAP 0x0064 16351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL 0x0068 16451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS 0x006a 16551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP 0x006c 16651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL 0x0070 16751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS 0x0072 16851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_ROOT_CNTL 0x0074 16951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_ROOT_CAP 0x0076 17051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_ROOT_STATUS 0x0078 17151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x007c 17251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0080 17351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0082 17451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_LINK_CAP2 0x0084 17551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0088 17651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS2 0x008a 17751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP2 0x008c 17851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0090 17951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0092 18051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x00a0 18151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x00a2 18251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x00a4 18351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x00a8 18451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x00a8 18551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x00ac 18651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x00c0 18751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_SSID_CAP 0x00c4 18851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST 0x00c8 18951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP 0x00ca 19051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO 0x00cc 19151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI 0x00d0 19251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 19351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 19451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0108 19551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x010c 19651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0110 19751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0114 19851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0118 19951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x011c 20051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x011e 20151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0120 20251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0124 20351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x012a 20451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x012c 20551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x0130 20651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x0136 20751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 20851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 20951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 21051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 21151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0154 21251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0158 21351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x015c 21451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0160 21551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0164 21651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x0168 21751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x016c 21851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x0170 21951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x0174 22051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x0178 22151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x017c 22251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x0180 22351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x0184 22451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x0188 22551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x018c 22651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0190 22751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0194 22851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 22951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x0274 23051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x0278 23151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 23251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 23351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 23451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 23551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 23651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 23751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 23851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 23951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 24051199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 24151199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 24251199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 24351199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 24451199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 24551199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 24651199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 24751199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x02a0 24851199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x02a4 24951199920SFeifei Xu #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x02a6 25051199920SFeifei Xu 25151199920SFeifei Xu 25251199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp 25351199920SFeifei Xu // base address: 0x0 25451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_VENDOR_ID 0x0000 25551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_DEVICE_ID 0x0002 25651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_COMMAND 0x0004 25751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_STATUS 0x0006 25851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_REVISION_ID 0x0008 25951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PROG_INTERFACE 0x0009 26051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SUB_CLASS 0x000a 26151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_BASE_CLASS 0x000b 26251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_CACHE_LINE 0x000c 26351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_LATENCY 0x000d 26451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_HEADER 0x000e 26551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_BIST 0x000f 26651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_BASE_ADDR_1 0x0010 26751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY 0x0018 26851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT 0x001c 26951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SECONDARY_STATUS 0x001e 27051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT 0x0020 27151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT 0x0024 27251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PREF_BASE_UPPER 0x0028 27351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER 0x002c 27451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI 0x0030 27551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_CAP_PTR 0x0034 27651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_INTERRUPT_LINE 0x003c 27751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_INTERRUPT_PIN 0x003d 27851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL 0x003e 27951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL 0x0040 28051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PMI_CAP_LIST 0x0050 28151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PMI_CAP 0x0052 28251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL 0x0054 28351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_CAP_LIST 0x0058 28451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_CAP 0x005a 28551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP 0x005c 28651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL 0x0060 28751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS 0x0062 28851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_LINK_CAP 0x0064 28951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_LINK_CNTL 0x0068 29051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_LINK_STATUS 0x006a 29151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SLOT_CAP 0x006c 29251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL 0x0070 29351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS 0x0072 29451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_ROOT_CNTL 0x0074 29551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_ROOT_CAP 0x0076 29651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_ROOT_STATUS 0x0078 29751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP2 0x007c 29851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL2 0x0080 29951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS2 0x0082 30051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_LINK_CAP2 0x0084 30151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_LINK_CNTL2 0x0088 30251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_LINK_STATUS2 0x008a 30351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SLOT_CAP2 0x008c 30451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL2 0x0090 30551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS2 0x0092 30651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_CAP_LIST 0x00a0 30751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_CNTL 0x00a2 30851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO 0x00a4 30951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI 0x00a8 31051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA 0x00a8 31151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64 0x00ac 31251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SSID_CAP_LIST 0x00c0 31351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_SSID_CAP 0x00c4 31451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST 0x00c8 31551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP 0x00ca 31651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO 0x00cc 31751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI 0x00d0 31851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 31951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 32051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1 0x0108 32151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2 0x010c 32251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST 0x0110 32351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1 0x0114 32451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2 0x0118 32551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL 0x011c 32651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS 0x011e 32751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP 0x0120 32851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL 0x0124 32951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS 0x012a 33051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP 0x012c 33151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL 0x0130 33251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS 0x0136 33351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 33451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 33551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 33651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 33751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS 0x0154 33851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK 0x0158 33951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY 0x015c 34051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS 0x0160 34151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK 0x0164 34251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL 0x0168 34351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0 0x016c 34451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1 0x0170 34551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2 0x0174 34651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3 0x0178 34751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD 0x017c 34851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS 0x0180 34951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID 0x0184 35051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0 0x0188 35151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1 0x018c 35251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2 0x0190 35351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3 0x0194 35451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 35551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3 0x0274 35651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS 0x0278 35751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 35851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 35951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 36051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 36151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 36251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 36351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 36451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 36551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 36651199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 36751199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 36851199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 36951199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 37051199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 37151199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 37251199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 37351199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST 0x02a0 37451199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CAP 0x02a4 37551199920SFeifei Xu #define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL 0x02a6 37651199920SFeifei Xu 37751199920SFeifei Xu 37851199920SFeifei Xu // addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec 37951199920SFeifei Xu // base address: 0x0 38051199920SFeifei Xu #define cfgNB_PCIEDUMMY0_0_DEVICE_VENDOR_ID 0x0000 38151199920SFeifei Xu #define cfgNB_PCIEDUMMY0_0_STATUS_COMMAND 0x0004 38251199920SFeifei Xu #define cfgNB_PCIEDUMMY0_0_CLASS_CODE_REVID 0x0008 38351199920SFeifei Xu #define cfgNB_PCIEDUMMY0_0_HEADER_TYPE 0x000c 38451199920SFeifei Xu #define cfgNB_PCIEDUMMY0_0_HEADER_TYPE_W 0x0040 38551199920SFeifei Xu 38651199920SFeifei Xu 38751199920SFeifei Xu // addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec 38851199920SFeifei Xu // base address: 0x0 38951199920SFeifei Xu #define cfgNB_PCIEDUMMY1_0_DEVICE_VENDOR_ID 0x0000 39051199920SFeifei Xu #define cfgNB_PCIEDUMMY1_0_STATUS_COMMAND 0x0004 39151199920SFeifei Xu #define cfgNB_PCIEDUMMY1_0_CLASS_CODE_REVID 0x0008 39251199920SFeifei Xu #define cfgNB_PCIEDUMMY1_0_HEADER_TYPE 0x000c 39351199920SFeifei Xu #define cfgNB_PCIEDUMMY1_0_HEADER_TYPE_W 0x0040 39451199920SFeifei Xu 39551199920SFeifei Xu 39651199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 39751199920SFeifei Xu // base address: 0x0 39851199920SFeifei Xu #define cfgVENDOR_ID 0x0000 39951199920SFeifei Xu #define cfgDEVICE_ID 0x0002 40051199920SFeifei Xu #define cfgCOMMAND 0x0004 40151199920SFeifei Xu #define cfgSTATUS 0x0006 40251199920SFeifei Xu #define cfgREVISION_ID 0x0008 40351199920SFeifei Xu #define cfgPROG_INTERFACE 0x0009 40451199920SFeifei Xu #define cfgSUB_CLASS 0x000a 40551199920SFeifei Xu #define cfgBASE_CLASS 0x000b 40651199920SFeifei Xu #define cfgCACHE_LINE 0x000c 40751199920SFeifei Xu #define cfgLATENCY 0x000d 40851199920SFeifei Xu #define cfgHEADER 0x000e 40951199920SFeifei Xu #define cfgBIST 0x000f 41051199920SFeifei Xu #define cfgBASE_ADDR_1 0x0010 41151199920SFeifei Xu #define cfgBASE_ADDR_2 0x0014 41251199920SFeifei Xu #define cfgBASE_ADDR_3 0x0018 41351199920SFeifei Xu #define cfgBASE_ADDR_4 0x001c 41451199920SFeifei Xu #define cfgBASE_ADDR_5 0x0020 41551199920SFeifei Xu #define cfgBASE_ADDR_6 0x0024 41651199920SFeifei Xu #define cfgADAPTER_ID 0x002c 41751199920SFeifei Xu #define cfgROM_BASE_ADDR 0x0030 41851199920SFeifei Xu #define cfgCAP_PTR 0x0034 41951199920SFeifei Xu #define cfgINTERRUPT_LINE 0x003c 42051199920SFeifei Xu #define cfgINTERRUPT_PIN 0x003d 42151199920SFeifei Xu #define cfgMIN_GRANT 0x003e 42251199920SFeifei Xu #define cfgMAX_LATENCY 0x003f 42351199920SFeifei Xu #define cfgVENDOR_CAP_LIST 0x0048 42451199920SFeifei Xu #define cfgADAPTER_ID_W 0x004c 42551199920SFeifei Xu #define cfgPMI_CAP_LIST 0x0050 42651199920SFeifei Xu #define cfgPMI_CAP 0x0052 42751199920SFeifei Xu #define cfgPMI_STATUS_CNTL 0x0054 42851199920SFeifei Xu #define cfgPCIE_CAP_LIST 0x0064 42951199920SFeifei Xu #define cfgPCIE_CAP 0x0066 43051199920SFeifei Xu #define cfgDEVICE_CAP 0x0068 43151199920SFeifei Xu #define cfgDEVICE_CNTL 0x006c 43251199920SFeifei Xu #define cfgDEVICE_STATUS 0x006e 43351199920SFeifei Xu #define cfgLINK_CAP 0x0070 43451199920SFeifei Xu #define cfgLINK_CNTL 0x0074 43551199920SFeifei Xu #define cfgLINK_STATUS 0x0076 43651199920SFeifei Xu #define cfgDEVICE_CAP2 0x0088 43751199920SFeifei Xu #define cfgDEVICE_CNTL2 0x008c 43851199920SFeifei Xu #define cfgDEVICE_STATUS2 0x008e 43951199920SFeifei Xu #define cfgLINK_CAP2 0x0090 44051199920SFeifei Xu #define cfgLINK_CNTL2 0x0094 44151199920SFeifei Xu #define cfgLINK_STATUS2 0x0096 44251199920SFeifei Xu #define cfgSLOT_CAP2 0x0098 44351199920SFeifei Xu #define cfgSLOT_CNTL2 0x009c 44451199920SFeifei Xu #define cfgSLOT_STATUS2 0x009e 44551199920SFeifei Xu #define cfgMSI_CAP_LIST 0x00a0 44651199920SFeifei Xu #define cfgMSI_MSG_CNTL 0x00a2 44751199920SFeifei Xu #define cfgMSI_MSG_ADDR_LO 0x00a4 44851199920SFeifei Xu #define cfgMSI_MSG_ADDR_HI 0x00a8 44951199920SFeifei Xu #define cfgMSI_MSG_DATA 0x00a8 45051199920SFeifei Xu #define cfgMSI_MASK 0x00ac 45151199920SFeifei Xu #define cfgMSI_MSG_DATA_64 0x00ac 45251199920SFeifei Xu #define cfgMSI_MASK_64 0x00b0 45351199920SFeifei Xu #define cfgMSI_PENDING 0x00b0 45451199920SFeifei Xu #define cfgMSI_PENDING_64 0x00b4 45551199920SFeifei Xu #define cfgMSIX_CAP_LIST 0x00c0 45651199920SFeifei Xu #define cfgMSIX_MSG_CNTL 0x00c2 45751199920SFeifei Xu #define cfgMSIX_TABLE 0x00c4 45851199920SFeifei Xu #define cfgMSIX_PBA 0x00c8 45951199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 46051199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 46151199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC1 0x0108 46251199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC2 0x010c 46351199920SFeifei Xu #define cfgPCIE_VC_ENH_CAP_LIST 0x0110 46451199920SFeifei Xu #define cfgPCIE_PORT_VC_CAP_REG1 0x0114 46551199920SFeifei Xu #define cfgPCIE_PORT_VC_CAP_REG2 0x0118 46651199920SFeifei Xu #define cfgPCIE_PORT_VC_CNTL 0x011c 46751199920SFeifei Xu #define cfgPCIE_PORT_VC_STATUS 0x011e 46851199920SFeifei Xu #define cfgPCIE_VC0_RESOURCE_CAP 0x0120 46951199920SFeifei Xu #define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 47051199920SFeifei Xu #define cfgPCIE_VC0_RESOURCE_STATUS 0x012a 47151199920SFeifei Xu #define cfgPCIE_VC1_RESOURCE_CAP 0x012c 47251199920SFeifei Xu #define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 47351199920SFeifei Xu #define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 47451199920SFeifei Xu #define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 47551199920SFeifei Xu #define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 47651199920SFeifei Xu #define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 47751199920SFeifei Xu #define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 47851199920SFeifei Xu #define cfgPCIE_UNCORR_ERR_STATUS 0x0154 47951199920SFeifei Xu #define cfgPCIE_UNCORR_ERR_MASK 0x0158 48051199920SFeifei Xu #define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c 48151199920SFeifei Xu #define cfgPCIE_CORR_ERR_STATUS 0x0160 48251199920SFeifei Xu #define cfgPCIE_CORR_ERR_MASK 0x0164 48351199920SFeifei Xu #define cfgPCIE_ADV_ERR_CAP_CNTL 0x0168 48451199920SFeifei Xu #define cfgPCIE_HDR_LOG0 0x016c 48551199920SFeifei Xu #define cfgPCIE_HDR_LOG1 0x0170 48651199920SFeifei Xu #define cfgPCIE_HDR_LOG2 0x0174 48751199920SFeifei Xu #define cfgPCIE_HDR_LOG3 0x0178 48851199920SFeifei Xu #define cfgPCIE_TLP_PREFIX_LOG0 0x0188 48951199920SFeifei Xu #define cfgPCIE_TLP_PREFIX_LOG1 0x018c 49051199920SFeifei Xu #define cfgPCIE_TLP_PREFIX_LOG2 0x0190 49151199920SFeifei Xu #define cfgPCIE_TLP_PREFIX_LOG3 0x0194 49251199920SFeifei Xu #define cfgPCIE_BAR_ENH_CAP_LIST 0x0200 49351199920SFeifei Xu #define cfgPCIE_BAR1_CAP 0x0204 49451199920SFeifei Xu #define cfgPCIE_BAR1_CNTL 0x0208 49551199920SFeifei Xu #define cfgPCIE_BAR2_CAP 0x020c 49651199920SFeifei Xu #define cfgPCIE_BAR2_CNTL 0x0210 49751199920SFeifei Xu #define cfgPCIE_BAR3_CAP 0x0214 49851199920SFeifei Xu #define cfgPCIE_BAR3_CNTL 0x0218 49951199920SFeifei Xu #define cfgPCIE_BAR4_CAP 0x021c 50051199920SFeifei Xu #define cfgPCIE_BAR4_CNTL 0x0220 50151199920SFeifei Xu #define cfgPCIE_BAR5_CAP 0x0224 50251199920SFeifei Xu #define cfgPCIE_BAR5_CNTL 0x0228 50351199920SFeifei Xu #define cfgPCIE_BAR6_CAP 0x022c 50451199920SFeifei Xu #define cfgPCIE_BAR6_CNTL 0x0230 50551199920SFeifei Xu #define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 50651199920SFeifei Xu #define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x0244 50751199920SFeifei Xu #define cfgPCIE_PWR_BUDGET_DATA 0x0248 50851199920SFeifei Xu #define cfgPCIE_PWR_BUDGET_CAP 0x024c 50951199920SFeifei Xu #define cfgPCIE_DPA_ENH_CAP_LIST 0x0250 51051199920SFeifei Xu #define cfgPCIE_DPA_CAP 0x0254 51151199920SFeifei Xu #define cfgPCIE_DPA_LATENCY_INDICATOR 0x0258 51251199920SFeifei Xu #define cfgPCIE_DPA_STATUS 0x025c 51351199920SFeifei Xu #define cfgPCIE_DPA_CNTL 0x025e 51451199920SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 51551199920SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 51651199920SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 51751199920SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 51851199920SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 51951199920SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 52051199920SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 52151199920SFeifei Xu #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 52251199920SFeifei Xu #define cfgPCIE_SECONDARY_ENH_CAP_LIST 0x0270 52351199920SFeifei Xu #define cfgPCIE_LINK_CNTL3 0x0274 52451199920SFeifei Xu #define cfgPCIE_LANE_ERROR_STATUS 0x0278 52551199920SFeifei Xu #define cfgPCIE_LANE_0_EQUALIZATION_CNTL 0x027c 52651199920SFeifei Xu #define cfgPCIE_LANE_1_EQUALIZATION_CNTL 0x027e 52751199920SFeifei Xu #define cfgPCIE_LANE_2_EQUALIZATION_CNTL 0x0280 52851199920SFeifei Xu #define cfgPCIE_LANE_3_EQUALIZATION_CNTL 0x0282 52951199920SFeifei Xu #define cfgPCIE_LANE_4_EQUALIZATION_CNTL 0x0284 53051199920SFeifei Xu #define cfgPCIE_LANE_5_EQUALIZATION_CNTL 0x0286 53151199920SFeifei Xu #define cfgPCIE_LANE_6_EQUALIZATION_CNTL 0x0288 53251199920SFeifei Xu #define cfgPCIE_LANE_7_EQUALIZATION_CNTL 0x028a 53351199920SFeifei Xu #define cfgPCIE_LANE_8_EQUALIZATION_CNTL 0x028c 53451199920SFeifei Xu #define cfgPCIE_LANE_9_EQUALIZATION_CNTL 0x028e 53551199920SFeifei Xu #define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 53651199920SFeifei Xu #define cfgPCIE_LANE_11_EQUALIZATION_CNTL 0x0292 53751199920SFeifei Xu #define cfgPCIE_LANE_12_EQUALIZATION_CNTL 0x0294 53851199920SFeifei Xu #define cfgPCIE_LANE_13_EQUALIZATION_CNTL 0x0296 53951199920SFeifei Xu #define cfgPCIE_LANE_14_EQUALIZATION_CNTL 0x0298 54051199920SFeifei Xu #define cfgPCIE_LANE_15_EQUALIZATION_CNTL 0x029a 54151199920SFeifei Xu #define cfgPCIE_ACS_ENH_CAP_LIST 0x02a0 54251199920SFeifei Xu #define cfgPCIE_ACS_CAP 0x02a4 54351199920SFeifei Xu #define cfgPCIE_ACS_CNTL 0x02a6 54451199920SFeifei Xu #define cfgPCIE_ATS_ENH_CAP_LIST 0x02b0 54551199920SFeifei Xu #define cfgPCIE_ATS_CAP 0x02b4 54651199920SFeifei Xu #define cfgPCIE_ATS_CNTL 0x02b6 54751199920SFeifei Xu #define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 54851199920SFeifei Xu #define cfgPCIE_PAGE_REQ_CNTL 0x02c4 54951199920SFeifei Xu #define cfgPCIE_PAGE_REQ_STATUS 0x02c6 55051199920SFeifei Xu #define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 55151199920SFeifei Xu #define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 55251199920SFeifei Xu #define cfgPCIE_PASID_ENH_CAP_LIST 0x02d0 55351199920SFeifei Xu #define cfgPCIE_PASID_CAP 0x02d4 55451199920SFeifei Xu #define cfgPCIE_PASID_CNTL 0x02d6 55551199920SFeifei Xu #define cfgPCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 55651199920SFeifei Xu #define cfgPCIE_TPH_REQR_CAP 0x02e4 55751199920SFeifei Xu #define cfgPCIE_TPH_REQR_CNTL 0x02e8 55851199920SFeifei Xu #define cfgPCIE_MC_ENH_CAP_LIST 0x02f0 55951199920SFeifei Xu #define cfgPCIE_MC_CAP 0x02f4 56051199920SFeifei Xu #define cfgPCIE_MC_CNTL 0x02f6 56151199920SFeifei Xu #define cfgPCIE_MC_ADDR0 0x02f8 56251199920SFeifei Xu #define cfgPCIE_MC_ADDR1 0x02fc 56351199920SFeifei Xu #define cfgPCIE_MC_RCV0 0x0300 56451199920SFeifei Xu #define cfgPCIE_MC_RCV1 0x0304 56551199920SFeifei Xu #define cfgPCIE_MC_BLOCK_ALL0 0x0308 56651199920SFeifei Xu #define cfgPCIE_MC_BLOCK_ALL1 0x030c 56751199920SFeifei Xu #define cfgPCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 56851199920SFeifei Xu #define cfgPCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 56951199920SFeifei Xu #define cfgPCIE_LTR_ENH_CAP_LIST 0x0320 57051199920SFeifei Xu #define cfgPCIE_LTR_CAP 0x0324 57151199920SFeifei Xu #define cfgPCIE_ARI_ENH_CAP_LIST 0x0328 57251199920SFeifei Xu #define cfgPCIE_ARI_CAP 0x032c 57351199920SFeifei Xu #define cfgPCIE_ARI_CNTL 0x032e 57451199920SFeifei Xu #define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 57551199920SFeifei Xu #define cfgPCIE_SRIOV_CAP 0x0334 57651199920SFeifei Xu #define cfgPCIE_SRIOV_CONTROL 0x0338 57751199920SFeifei Xu #define cfgPCIE_SRIOV_STATUS 0x033a 57851199920SFeifei Xu #define cfgPCIE_SRIOV_INITIAL_VFS 0x033c 57951199920SFeifei Xu #define cfgPCIE_SRIOV_TOTAL_VFS 0x033e 58051199920SFeifei Xu #define cfgPCIE_SRIOV_NUM_VFS 0x0340 58151199920SFeifei Xu #define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 58251199920SFeifei Xu #define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 58351199920SFeifei Xu #define cfgPCIE_SRIOV_VF_STRIDE 0x0346 58451199920SFeifei Xu #define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a 58551199920SFeifei Xu #define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 58651199920SFeifei Xu #define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 58751199920SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 58851199920SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 58951199920SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c 59051199920SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 59151199920SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 59251199920SFeifei Xu #define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 59351199920SFeifei Xu #define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 59451199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 59551199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 59651199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 59751199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c 59851199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 59951199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 60051199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 60151199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c 60251199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 60351199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 60451199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 60551199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c 60651199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 60751199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 60851199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 60951199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c 61051199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 61151199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 61251199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 61351199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c 61451199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 61551199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 61651199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 61751199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c 61851199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 61951199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 62051199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 62151199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c 62251199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 62351199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 62451199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 62551199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c 62651199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 62751199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 62851199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 62951199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c 63051199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 63151199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 63251199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 63351199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 63451199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac 63551199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 63651199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 63751199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 63851199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc 63951199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 64051199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 64151199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 64251199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 64351199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc 64451199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 64551199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 64651199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 64751199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec 64851199920SFeifei Xu #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 64951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 65051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 65151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 65251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 65351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 65451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 65551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a 65651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b 65751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c 65851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d 65951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e 66051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f 66151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 66251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 66351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 66451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c 66551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 66651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 66751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c 66851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 66951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 67051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c 67151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d 67251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e 67351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f 67451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048 67551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c 67651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 67751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 67851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 67951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 68051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 68151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 68251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c 68351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e 68451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 68551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 68651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 68751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 68851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c 68951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e 69051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 69151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 69251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 69351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_SLOT_CAP2 0x0098 69451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_SLOT_CNTL2 0x009c 69551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_SLOT_STATUS2 0x009e 69651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 69751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 69851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 69951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 70051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 70151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac 70251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac 70351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 70451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 70551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 70651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 70751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 70851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 70951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 71051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 71151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 71251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 71351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c 71451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110 71551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114 71651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118 71751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c 71851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e 71951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120 72051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124 72151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a 72251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c 72351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130 72451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136 72551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 72651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 72751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 72851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 72951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154 73051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158 73151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c 73251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160 73351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164 73451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 73551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c 73651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170 73751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174 73851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178 73951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188 74051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c 74151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190 74251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194 74351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200 74451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204 74551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208 74651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c 74751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210 74851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214 74951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218 75051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c 75151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220 75251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224 75351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228 75451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c 75551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230 75651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 75751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 75851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248 75951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c 76051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250 76151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254 76251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258 76351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c 76451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e 76551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 76651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 76751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 76851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 76951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 77051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 77151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 77251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 77351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 77451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274 77551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278 77651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 77751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 77851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 77951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 78051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 78151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 78251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 78351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 78451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 78551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 78651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 78751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 78851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 78951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 79051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 79151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 79251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0 79351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4 79451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6 79551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 79651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x02b4 79751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x02b6 79851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 79951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL 0x02c4 80051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS 0x02c6 80151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 80251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 80351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0 80451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4 80551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6 80651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 80751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP 0x02e4 80851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL 0x02e8 80951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x02f0 81051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x02f4 81151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x02f6 81251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x02f8 81351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x02fc 81451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x0300 81551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x0304 81651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x0308 81751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x030c 81851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 81951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 82051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320 82151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324 82251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328 82351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c 82451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e 82551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 82651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x0334 82751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x0338 82851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x033a 82951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x033c 83051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x033e 83151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x0340 83251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 83351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 83451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x0346 83551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 83651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 83751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 83851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 83951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 84051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 84151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 84251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 84351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 84451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 84551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 84651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 84751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 84851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c 84951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 85051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 85151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 85251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c 85351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 85451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 85551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 85651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c 85751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 85851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 85951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 86051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c 86151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 86251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 86351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 86451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c 86551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 86651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 86751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 86851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c 86951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 87051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 87151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 87251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c 87351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 87451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 87551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 87651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c 87751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 87851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 87951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 88051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c 88151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 88251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 88351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 88451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 88551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac 88651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 88751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 88851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 88951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc 89051199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 89151199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 89251199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 89351199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 89451199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc 89551199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 89651199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 89751199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 89851199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec 89951199920SFeifei Xu //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 90051199920SFeifei Xu 90151199920SFeifei Xu 90251199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 90351199920SFeifei Xu // base address: 0x0 90451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 90551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 90651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 90751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 90851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 90951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 91051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a 91151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b 91251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c 91351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d 91451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e 91551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f 91651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 91751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 91851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 91951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c 92051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 92151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 92251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c 92351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 92451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 92551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c 92651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d 92751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e 92851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f 92951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 93051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c 93151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 93251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 93351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 93451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 93551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 93651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 93751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c 93851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e 93951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 94051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 94151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 94251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 94351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c 94451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e 94551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 94651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 94751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 94851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098 94951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c 95051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e 95151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 95251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 95351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 95451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 95551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 95651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac 95751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac 95851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 95951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 96051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 96151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 96251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 96351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 96451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 96551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 96651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 96751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 96851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 96951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 97051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 97151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 97251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c 97351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e 97451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 97551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 97651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a 97751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c 97851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 97951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 98051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 98151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 98251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 98351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 98451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 98551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 98651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 98751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 98851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 98951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 99051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c 99151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 99251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 99351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 99451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 99551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 99651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 99751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 99851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 99951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 100051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 100151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c 100251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 100351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 100451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 100551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c 100651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 100751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 100851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 100951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c 101051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 101151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 101251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 101351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 101451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c 101551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 101651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 101751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 101851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c 101951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e 102051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 102151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 102251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 102351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 102451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 102551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 102651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 102751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 102851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 102951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 103051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 103151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 103251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 103351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 103451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 103551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 103651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 103751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 103851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 103951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 104051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 104151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 104251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 104351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 104451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 104551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 104651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 104751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 104851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 104951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 105051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 105151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 105251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 105351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 105451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 105551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 105651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 105751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 105851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 105951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 106051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 106151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 106251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x02e4 106351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x02e8 106451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 106551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 106651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 106751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 106851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc 106951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 107051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 107151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 107251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c 107351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 107451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 107551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 107651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 107751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 107851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c 107951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e 108051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 108151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 108251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 108351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a 108451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c 108551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e 108651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 108751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 108851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 108951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 109051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a 109151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 109251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 109351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 109451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 109551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c 109651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 109751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 109851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 109951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 110051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 110151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 110251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 110351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c 110451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 110551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 110651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 110751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c 110851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 110951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 111051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 111151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c 111251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 111351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 111451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 111551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c 111651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 111751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 111851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 111951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c 112051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 112151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 112251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 112351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c 112451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 112551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 112651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 112751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c 112851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 112951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 113051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 113151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c 113251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 113351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 113451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 113551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c 113651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 113751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 113851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 113951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 114051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac 114151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 114251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 114351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 114451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc 114551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 114651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 114751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 114851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 114951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc 115051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 115151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 115251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 115351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec 115451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 115551199920SFeifei Xu 115651199920SFeifei Xu 115751199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp 115851199920SFeifei Xu // base address: 0x0 115951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0x0000 116051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0x0002 116151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_COMMAND 0x0004 116251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_STATUS 0x0006 116351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID 0x0008 116451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0x0009 116551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0x000a 116651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0x000b 116751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0x000c 116851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_LATENCY 0x000d 116951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_HEADER 0x000e 117051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_BIST 0x000f 117151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0x0010 117251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0x0014 117351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0x0018 117451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0x001c 117551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0x0020 117651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0x0024 117751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0x002c 117851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0x0030 117951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR 0x0034 118051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0x003c 118151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0x003d 118251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0x003e 118351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0x003f 118451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0x0048 118551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0x004c 118651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0x0050 118751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP 0x0052 118851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0x0054 118951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_SBRN 0x0060 119051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_FLADJ 0x0061 119151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0x0062 119251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0x0064 119351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0x0066 119451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0x0068 119551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0x006c 119651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0x006e 119751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP 0x0070 119851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0x0074 119951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0x0076 120051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0x0088 120151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0x008c 120251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0x008e 120351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0x0090 120451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0x0094 120551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0x0096 120651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CAP2 0x0098 120751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CNTL2 0x009c 120851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_SLOT_STATUS2 0x009e 120951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0x00a0 121051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0x00a2 121151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0x00a4 121251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0x00a8 121351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0x00a8 121451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK 0x00ac 121551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0x00ac 121651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0x00b0 121751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0x00b0 121851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0x00b4 121951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0x00c0 122051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0x00c2 122151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0x00c4 122251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0x00c8 122351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0 0x00d0 122451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1 0x00d4 122551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX 0x00d8 122651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA 0x00dc 122751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 122851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 122951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 123051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x010c 123151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 123251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 123351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0x0158 123451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 123551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0x0160 123651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0x0164 123751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 123851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0x016c 123951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0x0170 124051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0x0174 124151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0x0178 124251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 124351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x018c 124451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 124551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 124651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x0200 124751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0x0204 124851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0x0208 124951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0x020c 125051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0x0210 125151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0x0214 125251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0x0218 125351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0x021c 125451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0x0220 125551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0x0224 125651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0x0228 125751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0x022c 125851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0x0230 125951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 126051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 126151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0x0248 126251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c 126351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x0250 126451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0x0254 126551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 126651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0x025c 126751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0x025e 126851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 126951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 127051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 127151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 127251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 127351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 127451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 127551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 127651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 127751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0x02a4 127851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0x02a6 127951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 128051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0x032c 128151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0x032e 128251199920SFeifei Xu 128351199920SFeifei Xu 128451199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp 128551199920SFeifei Xu // base address: 0x0 128651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0x0000 128751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0x0002 128851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_COMMAND 0x0004 128951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_STATUS 0x0006 129051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID 0x0008 129151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0x0009 129251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0x000a 129351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0x000b 129451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0x000c 129551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_LATENCY 0x000d 129651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_HEADER 0x000e 129751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_BIST 0x000f 129851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0x0010 129951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0x0014 130051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0x0018 130151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0x001c 130251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0x0020 130351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0x0024 130451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0x002c 130551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0x0030 130651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR 0x0034 130751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0x003c 130851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0x003d 130951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0x003e 131051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0x003f 131151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0x0048 131251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0x004c 131351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0x0050 131451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP 0x0052 131551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0x0054 131651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_SBRN 0x0060 131751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_FLADJ 0x0061 131851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0x0062 131951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0x0064 132051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0x0066 132151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0x0068 132251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0x006c 132351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0x006e 132451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP 0x0070 132551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0x0074 132651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0x0076 132751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0x0088 132851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0x008c 132951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0x008e 133051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0x0090 133151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0x0094 133251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0x0096 133351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CAP2 0x0098 133451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CNTL2 0x009c 133551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_SLOT_STATUS2 0x009e 133651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0x00a0 133751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0x00a2 133851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0x00a4 133951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0x00a8 134051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0x00a8 134151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK 0x00ac 134251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0x00ac 134351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0x00b0 134451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0x00b0 134551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0x00b4 134651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0x00c0 134751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0x00c2 134851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0x00c4 134951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0x00c8 135051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0 0x00d0 135151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1 0x00d4 135251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX 0x00d8 135351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA 0x00dc 135451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 135551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 135651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 135751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0x010c 135851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 135951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 136051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0x0158 136151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 136251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0x0160 136351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0x0164 136451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 136551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0x016c 136651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0x0170 136751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0x0174 136851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0x0178 136951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 137051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0x018c 137151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 137251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 137351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0x0200 137451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0x0204 137551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0x0208 137651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0x020c 137751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0x0210 137851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0x0214 137951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0x0218 138051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0x021c 138151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0x0220 138251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0x0224 138351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0x0228 138451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0x022c 138551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0x0230 138651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 138751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 138851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0x0248 138951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0x024c 139051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0x0250 139151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0x0254 139251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 139351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0x025c 139451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0x025e 139551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 139651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 139751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 139851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 139951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 140051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 140151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 140251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 140351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 140451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0x02a4 140551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0x02a6 140651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 140751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0x032c 140851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0x032e 140951199920SFeifei Xu 141051199920SFeifei Xu 141151199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp 141251199920SFeifei Xu // base address: 0x0 141351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_ID 0x0000 141451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_ID 0x0002 141551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_COMMAND 0x0004 141651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_STATUS 0x0006 141751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_REVISION_ID 0x0008 141851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE 0x0009 141951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_SUB_CLASS 0x000a 142051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_BASE_CLASS 0x000b 142151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_CACHE_LINE 0x000c 142251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_LATENCY 0x000d 142351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_HEADER 0x000e 142451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_BIST 0x000f 142551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1 0x0010 142651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2 0x0014 142751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3 0x0018 142851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4 0x001c 142951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5 0x0020 143051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6 0x0024 143151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID 0x002c 143251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR 0x0030 143351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_CAP_PTR 0x0034 143451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE 0x003c 143551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN 0x003d 143651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MIN_GRANT 0x003e 143751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MAX_LATENCY 0x003f 143851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST 0x0048 143951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W 0x004c 144051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST 0x0050 144151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP 0x0052 144251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL 0x0054 144351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_SBRN 0x0060 144451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_FLADJ 0x0061 144551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD 0x0062 144651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST 0x0064 144751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP 0x0066 144851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP 0x0068 144951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL 0x006c 145051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS 0x006e 145151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP 0x0070 145251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL 0x0074 145351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS 0x0076 145451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2 0x0088 145551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2 0x008c 145651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2 0x008e 145751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP2 0x0090 145851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL2 0x0094 145951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS2 0x0096 146051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CAP2 0x0098 146151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CNTL2 0x009c 146251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_SLOT_STATUS2 0x009e 146351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST 0x00a0 146451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL 0x00a2 146551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO 0x00a4 146651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI 0x00a8 146751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA 0x00a8 146851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK 0x00ac 146951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64 0x00ac 147051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK_64 0x00b0 147151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING 0x00b0 147251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64 0x00b4 147351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST 0x00c0 147451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL 0x00c2 147551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_TABLE 0x00c4 147651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_PBA 0x00c8 147751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_0 0x00d0 147851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_1 0x00d4 147951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX 0x00d8 148051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA 0x00dc 148151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 148251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 148351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 148451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2 0x010c 148551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 148651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 148751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK 0x0158 148851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 148951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS 0x0160 149051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK 0x0164 149151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 149251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0 0x016c 149351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1 0x0170 149451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2 0x0174 149551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3 0x0178 149651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 149751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1 0x018c 149851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 149951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 150051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST 0x0200 150151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP 0x0204 150251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL 0x0208 150351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP 0x020c 150451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL 0x0210 150551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP 0x0214 150651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL 0x0218 150751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP 0x021c 150851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL 0x0220 150951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP 0x0224 151051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL 0x0228 151151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP 0x022c 151251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL 0x0230 151351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 151451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 151551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA 0x0248 151651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP 0x024c 151751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST 0x0250 151851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP 0x0254 151951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 152051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS 0x025c 152151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL 0x025e 152251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 152351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 152451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 152551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 152651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 152751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 152851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 152951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 153051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 153151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP 0x02a4 153251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL 0x02a6 153351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 153451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP 0x032c 153551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL 0x032e 153651199920SFeifei Xu 153751199920SFeifei Xu 153851199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp 153951199920SFeifei Xu // base address: 0x0 154051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_ID 0x0000 154151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_ID 0x0002 154251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_COMMAND 0x0004 154351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_STATUS 0x0006 154451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_REVISION_ID 0x0008 154551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE 0x0009 154651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_SUB_CLASS 0x000a 154751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_BASE_CLASS 0x000b 154851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_CACHE_LINE 0x000c 154951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_LATENCY 0x000d 155051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_HEADER 0x000e 155151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_BIST 0x000f 155251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1 0x0010 155351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2 0x0014 155451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3 0x0018 155551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4 0x001c 155651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5 0x0020 155751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6 0x0024 155851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID 0x002c 155951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR 0x0030 156051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_CAP_PTR 0x0034 156151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE 0x003c 156251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN 0x003d 156351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MIN_GRANT 0x003e 156451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MAX_LATENCY 0x003f 156551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST 0x0048 156651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W 0x004c 156751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST 0x0050 156851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP 0x0052 156951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL 0x0054 157051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_SBRN 0x0060 157151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_FLADJ 0x0061 157251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD 0x0062 157351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST 0x0064 157451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP 0x0066 157551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP 0x0068 157651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL 0x006c 157751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS 0x006e 157851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP 0x0070 157951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL 0x0074 158051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS 0x0076 158151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2 0x0088 158251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2 0x008c 158351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2 0x008e 158451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP2 0x0090 158551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL2 0x0094 158651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS2 0x0096 158751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CAP2 0x0098 158851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CNTL2 0x009c 158951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_SLOT_STATUS2 0x009e 159051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST 0x00a0 159151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL 0x00a2 159251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO 0x00a4 159351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI 0x00a8 159451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA 0x00a8 159551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK 0x00ac 159651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64 0x00ac 159751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK_64 0x00b0 159851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING 0x00b0 159951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64 0x00b4 160051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST 0x00c0 160151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL 0x00c2 160251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_TABLE 0x00c4 160351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_PBA 0x00c8 160451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_0 0x00d0 160551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_1 0x00d4 160651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX 0x00d8 160751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA 0x00dc 160851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 160951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 161051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 161151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2 0x010c 161251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 161351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 161451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK 0x0158 161551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 161651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS 0x0160 161751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK 0x0164 161851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 161951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0 0x016c 162051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1 0x0170 162151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2 0x0174 162251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3 0x0178 162351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 162451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1 0x018c 162551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 162651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 162751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST 0x0200 162851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP 0x0204 162951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL 0x0208 163051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP 0x020c 163151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL 0x0210 163251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP 0x0214 163351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL 0x0218 163451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP 0x021c 163551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL 0x0220 163651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP 0x0224 163751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL 0x0228 163851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP 0x022c 163951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL 0x0230 164051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 164151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 164251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA 0x0248 164351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP 0x024c 164451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST 0x0250 164551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP 0x0254 164651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 164751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS 0x025c 164851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL 0x025e 164951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 165051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 165151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 165251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 165351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 165451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 165551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 165651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 165751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 165851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP 0x02a4 165951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL 0x02a6 166051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 166151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP 0x032c 166251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL 0x032e 166351199920SFeifei Xu 166451199920SFeifei Xu 166551199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp 166651199920SFeifei Xu // base address: 0x0 166751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_ID 0x0000 166851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_ID 0x0002 166951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_COMMAND 0x0004 167051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_STATUS 0x0006 167151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_REVISION_ID 0x0008 167251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE 0x0009 167351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_SUB_CLASS 0x000a 167451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_BASE_CLASS 0x000b 167551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_CACHE_LINE 0x000c 167651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_LATENCY 0x000d 167751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_HEADER 0x000e 167851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_BIST 0x000f 167951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1 0x0010 168051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2 0x0014 168151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3 0x0018 168251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4 0x001c 168351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5 0x0020 168451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6 0x0024 168551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID 0x002c 168651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR 0x0030 168751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_CAP_PTR 0x0034 168851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE 0x003c 168951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN 0x003d 169051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MIN_GRANT 0x003e 169151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MAX_LATENCY 0x003f 169251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST 0x0048 169351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W 0x004c 169451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST 0x0050 169551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP 0x0052 169651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL 0x0054 169751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_SBRN 0x0060 169851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_FLADJ 0x0061 169951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD 0x0062 170051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST 0x0064 170151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP 0x0066 170251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP 0x0068 170351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL 0x006c 170451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS 0x006e 170551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP 0x0070 170651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL 0x0074 170751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS 0x0076 170851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2 0x0088 170951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2 0x008c 171051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2 0x008e 171151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP2 0x0090 171251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL2 0x0094 171351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS2 0x0096 171451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CAP2 0x0098 171551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CNTL2 0x009c 171651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_SLOT_STATUS2 0x009e 171751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST 0x00a0 171851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL 0x00a2 171951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO 0x00a4 172051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI 0x00a8 172151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA 0x00a8 172251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK 0x00ac 172351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64 0x00ac 172451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK_64 0x00b0 172551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING 0x00b0 172651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64 0x00b4 172751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST 0x00c0 172851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL 0x00c2 172951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_TABLE 0x00c4 173051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_PBA 0x00c8 173151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_0 0x00d0 173251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_1 0x00d4 173351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX 0x00d8 173451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA 0x00dc 173551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 173651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 173751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 173851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2 0x010c 173951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 174051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 174151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK 0x0158 174251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 174351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS 0x0160 174451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK 0x0164 174551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 174651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0 0x016c 174751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1 0x0170 174851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2 0x0174 174951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3 0x0178 175051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 175151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1 0x018c 175251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 175351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 175451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST 0x0200 175551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP 0x0204 175651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL 0x0208 175751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP 0x020c 175851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL 0x0210 175951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP 0x0214 176051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL 0x0218 176151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP 0x021c 176251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL 0x0220 176351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP 0x0224 176451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL 0x0228 176551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP 0x022c 176651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL 0x0230 176751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 176851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 176951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA 0x0248 177051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP 0x024c 177151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST 0x0250 177251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP 0x0254 177351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 177451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS 0x025c 177551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL 0x025e 177651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 177751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 177851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 177951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 178051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 178151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 178251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 178351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 178451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 178551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP 0x02a4 178651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL 0x02a6 178751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 178851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP 0x032c 178951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL 0x032e 179051199920SFeifei Xu 179151199920SFeifei Xu 179251199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp 179351199920SFeifei Xu // base address: 0x0 179451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_ID 0x0000 179551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_ID 0x0002 179651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_COMMAND 0x0004 179751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_STATUS 0x0006 179851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_REVISION_ID 0x0008 179951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE 0x0009 180051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_SUB_CLASS 0x000a 180151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_BASE_CLASS 0x000b 180251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_CACHE_LINE 0x000c 180351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_LATENCY 0x000d 180451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_HEADER 0x000e 180551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_BIST 0x000f 180651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1 0x0010 180751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2 0x0014 180851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3 0x0018 180951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4 0x001c 181051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5 0x0020 181151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6 0x0024 181251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID 0x002c 181351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR 0x0030 181451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_CAP_PTR 0x0034 181551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE 0x003c 181651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN 0x003d 181751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MIN_GRANT 0x003e 181851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MAX_LATENCY 0x003f 181951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST 0x0048 182051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W 0x004c 182151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST 0x0050 182251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP 0x0052 182351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL 0x0054 182451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_SBRN 0x0060 182551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_FLADJ 0x0061 182651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD 0x0062 182751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST 0x0064 182851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP 0x0066 182951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP 0x0068 183051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL 0x006c 183151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS 0x006e 183251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP 0x0070 183351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL 0x0074 183451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS 0x0076 183551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2 0x0088 183651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2 0x008c 183751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2 0x008e 183851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP2 0x0090 183951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL2 0x0094 184051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS2 0x0096 184151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CAP2 0x0098 184251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CNTL2 0x009c 184351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_SLOT_STATUS2 0x009e 184451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST 0x00a0 184551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL 0x00a2 184651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO 0x00a4 184751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI 0x00a8 184851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA 0x00a8 184951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK 0x00ac 185051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64 0x00ac 185151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK_64 0x00b0 185251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING 0x00b0 185351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64 0x00b4 185451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST 0x00c0 185551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL 0x00c2 185651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_TABLE 0x00c4 185751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_PBA 0x00c8 185851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_0 0x00d0 185951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_1 0x00d4 186051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX 0x00d8 186151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA 0x00dc 186251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 186351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 186451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 186551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2 0x010c 186651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 186751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 186851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK 0x0158 186951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 187051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS 0x0160 187151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK 0x0164 187251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 187351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0 0x016c 187451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1 0x0170 187551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2 0x0174 187651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3 0x0178 187751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 187851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1 0x018c 187951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 188051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 188151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST 0x0200 188251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP 0x0204 188351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL 0x0208 188451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP 0x020c 188551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL 0x0210 188651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP 0x0214 188751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL 0x0218 188851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP 0x021c 188951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL 0x0220 189051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP 0x0224 189151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL 0x0228 189251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP 0x022c 189351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL 0x0230 189451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 189551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 189651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA 0x0248 189751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP 0x024c 189851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST 0x0250 189951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP 0x0254 190051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 190151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS 0x025c 190251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL 0x025e 190351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 190451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 190551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 190651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 190751199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 190851199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 190951199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 191051199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 191151199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 191251199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP 0x02a4 191351199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL 0x02a6 191451199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 191551199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP 0x032c 191651199920SFeifei Xu #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL 0x032e 191751199920SFeifei Xu 191851199920SFeifei Xu 191951199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp 192051199920SFeifei Xu // base address: 0x0 192151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_ID 0x0000 192251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_ID 0x0002 192351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_COMMAND 0x0004 192451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_STATUS 0x0006 192551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_REVISION_ID 0x0008 192651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE 0x0009 192751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_SUB_CLASS 0x000a 192851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_BASE_CLASS 0x000b 192951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_CACHE_LINE 0x000c 193051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_LATENCY 0x000d 193151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_HEADER 0x000e 193251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_BIST 0x000f 193351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1 0x0010 193451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2 0x0014 193551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3 0x0018 193651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4 0x001c 193751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5 0x0020 193851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6 0x0024 193951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID 0x002c 194051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR 0x0030 194151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_CAP_PTR 0x0034 194251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE 0x003c 194351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN 0x003d 194451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MIN_GRANT 0x003e 194551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MAX_LATENCY 0x003f 194651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST 0x0048 194751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W 0x004c 194851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST 0x0050 194951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP 0x0052 195051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL 0x0054 195151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST 0x0064 195251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP 0x0066 195351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP 0x0068 195451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL 0x006c 195551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS 0x006e 195651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP 0x0070 195751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL 0x0074 195851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS 0x0076 195951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2 0x0088 196051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2 0x008c 196151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2 0x008e 196251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP2 0x0090 196351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL2 0x0094 196451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS2 0x0096 196551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CAP2 0x0098 196651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CNTL2 0x009c 196751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_SLOT_STATUS2 0x009e 196851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST 0x00a0 196951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL 0x00a2 197051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 197151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 197251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA 0x00a8 197351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK 0x00ac 197451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64 0x00ac 197551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK_64 0x00b0 197651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING 0x00b0 197751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64 0x00b4 197851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST 0x00c0 197951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL 0x00c2 198051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_TABLE 0x00c4 198151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_PBA 0x00c8 198251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_0 0x00d0 198351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_1 0x00d4 198451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX 0x00d8 198551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA 0x00dc 198651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 198751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 198851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 198951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c 199051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 199151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 199251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 199351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL 0x011c 199451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS 0x011e 199551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 199651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 199751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a 199851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c 199951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 200051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 200151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 200251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 200351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 200451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 200551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 200651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 200751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 200851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0 0x016c 200951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1 0x0170 201051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2 0x0174 201151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3 0x0178 201251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 201351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c 201451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 201551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 201651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 201751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP 0x0204 201851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL 0x0208 201951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP 0x020c 202051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL 0x0210 202151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP 0x0214 202251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL 0x0218 202351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP 0x021c 202451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL 0x0220 202551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP 0x0224 202651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL 0x0228 202751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP 0x022c 202851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL 0x0230 202951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 203051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 203151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 203251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c 203351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 203451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP 0x0254 203551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 203651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS 0x025c 203751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL 0x025e 203851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 203951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 204051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 204151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 204251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 204351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 204451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 204551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 204651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 204751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3 0x0274 204851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 204951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 205051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 205151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 205251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 205351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 205451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 205551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 205651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 205751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 205851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 205951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 206051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 206151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 206251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 206351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 206451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 206551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 206651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP 0x02a4 206751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL 0x02a6 206851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 206951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP 0x0324 207051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 207151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP 0x032c 207251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL 0x032e 207351199920SFeifei Xu 207451199920SFeifei Xu 207551199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp 207651199920SFeifei Xu // base address: 0x0 207751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_ID 0x0000 207851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_ID 0x0002 207951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_COMMAND 0x0004 208051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_STATUS 0x0006 208151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_REVISION_ID 0x0008 208251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE 0x0009 208351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_SUB_CLASS 0x000a 208451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_BASE_CLASS 0x000b 208551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_CACHE_LINE 0x000c 208651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_LATENCY 0x000d 208751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_HEADER 0x000e 208851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_BIST 0x000f 208951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1 0x0010 209051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2 0x0014 209151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3 0x0018 209251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4 0x001c 209351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5 0x0020 209451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6 0x0024 209551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID 0x002c 209651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR 0x0030 209751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_CAP_PTR 0x0034 209851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE 0x003c 209951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN 0x003d 210051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MIN_GRANT 0x003e 210151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MAX_LATENCY 0x003f 210251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST 0x0048 210351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W 0x004c 210451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST 0x0050 210551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP 0x0052 210651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL 0x0054 210751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_SBRN 0x0060 210851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_FLADJ 0x0061 210951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD 0x0062 211051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST 0x0064 211151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP 0x0066 211251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP 0x0068 211351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL 0x006c 211451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS 0x006e 211551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP 0x0070 211651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL 0x0074 211751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS 0x0076 211851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2 0x0088 211951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2 0x008c 212051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2 0x008e 212151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP2 0x0090 212251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL2 0x0094 212351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS2 0x0096 212451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CAP2 0x0098 212551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CNTL2 0x009c 212651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_SLOT_STATUS2 0x009e 212751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST 0x00a0 212851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL 0x00a2 212951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 213051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 213151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA 0x00a8 213251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK 0x00ac 213351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64 0x00ac 213451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK_64 0x00b0 213551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING 0x00b0 213651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64 0x00b4 213751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST 0x00c0 213851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL 0x00c2 213951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_TABLE 0x00c4 214051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_PBA 0x00c8 214151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_0 0x00d0 214251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_1 0x00d4 214351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX 0x00d8 214451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA 0x00dc 214551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 214651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 214751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 214851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c 214951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 215051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 215151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 215251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 215351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 215451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 215551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 215651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0 0x016c 215751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1 0x0170 215851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2 0x0174 215951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3 0x0178 216051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 216151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c 216251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 216351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 216451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 216551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP 0x0204 216651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL 0x0208 216751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP 0x020c 216851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL 0x0210 216951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP 0x0214 217051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL 0x0218 217151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP 0x021c 217251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL 0x0220 217351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP 0x0224 217451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL 0x0228 217551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP 0x022c 217651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL 0x0230 217751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 217851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 217951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 218051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c 218151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 218251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP 0x0254 218351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 218451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS 0x025c 218551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL 0x025e 218651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 218751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 218851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 218951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 219051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 219151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 219251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 219351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 219451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 219551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP 0x02a4 219651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL 0x02a6 219751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 219851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP 0x032c 219951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL 0x032e 220051199920SFeifei Xu 220151199920SFeifei Xu 220251199920SFeifei Xu // addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp 220351199920SFeifei Xu // base address: 0x0 220451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_ID 0x0000 220551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_ID 0x0002 220651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_COMMAND 0x0004 220751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_STATUS 0x0006 220851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_REVISION_ID 0x0008 220951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PROG_INTERFACE 0x0009 221051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_SUB_CLASS 0x000a 221151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_BASE_CLASS 0x000b 221251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_CACHE_LINE 0x000c 221351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_LATENCY 0x000d 221451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_HEADER 0x000e 221551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_BIST 0x000f 221651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_1 0x0010 221751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_2 0x0014 221851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_3 0x0018 221951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_4 0x001c 222051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_5 0x0020 222151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_6 0x0024 222251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID 0x002c 222351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR 0x0030 222451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_CAP_PTR 0x0034 222551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE 0x003c 222651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN 0x003d 222751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MIN_GRANT 0x003e 222851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MAX_LATENCY 0x003f 222951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST 0x0048 223051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W 0x004c 223151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST 0x0050 223251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP 0x0052 223351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL 0x0054 223451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_SBRN 0x0060 223551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_FLADJ 0x0061 223651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_DBESL_DBESLD 0x0062 223751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST 0x0064 223851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP 0x0066 223951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP 0x0068 224051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL 0x006c 224151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS 0x006e 224251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP 0x0070 224351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL 0x0074 224451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS 0x0076 224551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP2 0x0088 224651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2 0x008c 224751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2 0x008e 224851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP2 0x0090 224951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL2 0x0094 225051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS2 0x0096 225151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CAP2 0x0098 225251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CNTL2 0x009c 225351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_SLOT_STATUS2 0x009e 225451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST 0x00a0 225551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL 0x00a2 225651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO 0x00a4 225751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI 0x00a8 225851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA 0x00a8 225951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK 0x00ac 226051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64 0x00ac 226151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK_64 0x00b0 226251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING 0x00b0 226351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING_64 0x00b4 226451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST 0x00c0 226551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL 0x00c2 226651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_TABLE 0x00c4 226751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_PBA 0x00c8 226851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_0 0x00d0 226951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_1 0x00d4 227051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX 0x00d8 227151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA 0x00dc 227251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 227351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 227451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 227551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x010c 227651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 227751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 227851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK 0x0158 227951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 228051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS 0x0160 228151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK 0x0164 228251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 228351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0 0x016c 228451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1 0x0170 228551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2 0x0174 228651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3 0x0178 228751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 228851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x018c 228951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 229051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 229151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x0200 229251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP 0x0204 229351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL 0x0208 229451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP 0x020c 229551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL 0x0210 229651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP 0x0214 229751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL 0x0218 229851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP 0x021c 229951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL 0x0220 230051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP 0x0224 230151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL 0x0228 230251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP 0x022c 230351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL 0x0230 230451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 230551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 230651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA 0x0248 230751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c 230851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x0250 230951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP 0x0254 231051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 231151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS 0x025c 231251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL 0x025e 231351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 231451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 231551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 231651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 231751199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 231851199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 231951199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 232051199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 232151199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 232251199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP 0x02a4 232351199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL 0x02a6 232451199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 232551199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP 0x032c 232651199920SFeifei Xu #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL 0x032e 232751199920SFeifei Xu 232851199920SFeifei Xu 232951199920SFeifei Xu // addressBlock: nbio_pcie0_bifplr0_cfgdecp 233051199920SFeifei Xu // base address: 0x0 233151199920SFeifei Xu #define cfgBIFPLR0_0_VENDOR_ID 0x0000 233251199920SFeifei Xu #define cfgBIFPLR0_0_DEVICE_ID 0x0002 233351199920SFeifei Xu #define cfgBIFPLR0_0_COMMAND 0x0004 233451199920SFeifei Xu #define cfgBIFPLR0_0_STATUS 0x0006 233551199920SFeifei Xu #define cfgBIFPLR0_0_REVISION_ID 0x0008 233651199920SFeifei Xu #define cfgBIFPLR0_0_PROG_INTERFACE 0x0009 233751199920SFeifei Xu #define cfgBIFPLR0_0_SUB_CLASS 0x000a 233851199920SFeifei Xu #define cfgBIFPLR0_0_BASE_CLASS 0x000b 233951199920SFeifei Xu #define cfgBIFPLR0_0_CACHE_LINE 0x000c 234051199920SFeifei Xu #define cfgBIFPLR0_0_LATENCY 0x000d 234151199920SFeifei Xu #define cfgBIFPLR0_0_HEADER 0x000e 234251199920SFeifei Xu #define cfgBIFPLR0_0_BIST 0x000f 234351199920SFeifei Xu #define cfgBIFPLR0_0_SUB_BUS_NUMBER_LATENCY 0x0018 234451199920SFeifei Xu #define cfgBIFPLR0_0_IO_BASE_LIMIT 0x001c 234551199920SFeifei Xu #define cfgBIFPLR0_0_SECONDARY_STATUS 0x001e 234651199920SFeifei Xu #define cfgBIFPLR0_0_MEM_BASE_LIMIT 0x0020 234751199920SFeifei Xu #define cfgBIFPLR0_0_PREF_BASE_LIMIT 0x0024 234851199920SFeifei Xu #define cfgBIFPLR0_0_PREF_BASE_UPPER 0x0028 234951199920SFeifei Xu #define cfgBIFPLR0_0_PREF_LIMIT_UPPER 0x002c 235051199920SFeifei Xu #define cfgBIFPLR0_0_IO_BASE_LIMIT_HI 0x0030 235151199920SFeifei Xu #define cfgBIFPLR0_0_CAP_PTR 0x0034 235251199920SFeifei Xu #define cfgBIFPLR0_0_INTERRUPT_LINE 0x003c 235351199920SFeifei Xu #define cfgBIFPLR0_0_INTERRUPT_PIN 0x003d 235451199920SFeifei Xu #define cfgBIFPLR0_0_IRQ_BRIDGE_CNTL 0x003e 235551199920SFeifei Xu #define cfgBIFPLR0_0_EXT_BRIDGE_CNTL 0x0040 235651199920SFeifei Xu #define cfgBIFPLR0_0_PMI_CAP_LIST 0x0050 235751199920SFeifei Xu #define cfgBIFPLR0_0_PMI_CAP 0x0052 235851199920SFeifei Xu #define cfgBIFPLR0_0_PMI_STATUS_CNTL 0x0054 235951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_CAP_LIST 0x0058 236051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_CAP 0x005a 236151199920SFeifei Xu #define cfgBIFPLR0_0_DEVICE_CAP 0x005c 236251199920SFeifei Xu #define cfgBIFPLR0_0_DEVICE_CNTL 0x0060 236351199920SFeifei Xu #define cfgBIFPLR0_0_DEVICE_STATUS 0x0062 236451199920SFeifei Xu #define cfgBIFPLR0_0_LINK_CAP 0x0064 236551199920SFeifei Xu #define cfgBIFPLR0_0_LINK_CNTL 0x0068 236651199920SFeifei Xu #define cfgBIFPLR0_0_LINK_STATUS 0x006a 236751199920SFeifei Xu #define cfgBIFPLR0_0_SLOT_CAP 0x006c 236851199920SFeifei Xu #define cfgBIFPLR0_0_SLOT_CNTL 0x0070 236951199920SFeifei Xu #define cfgBIFPLR0_0_SLOT_STATUS 0x0072 237051199920SFeifei Xu #define cfgBIFPLR0_0_ROOT_CNTL 0x0074 237151199920SFeifei Xu #define cfgBIFPLR0_0_ROOT_CAP 0x0076 237251199920SFeifei Xu #define cfgBIFPLR0_0_ROOT_STATUS 0x0078 237351199920SFeifei Xu #define cfgBIFPLR0_0_DEVICE_CAP2 0x007c 237451199920SFeifei Xu #define cfgBIFPLR0_0_DEVICE_CNTL2 0x0080 237551199920SFeifei Xu #define cfgBIFPLR0_0_DEVICE_STATUS2 0x0082 237651199920SFeifei Xu #define cfgBIFPLR0_0_LINK_CAP2 0x0084 237751199920SFeifei Xu #define cfgBIFPLR0_0_LINK_CNTL2 0x0088 237851199920SFeifei Xu #define cfgBIFPLR0_0_LINK_STATUS2 0x008a 237951199920SFeifei Xu #define cfgBIFPLR0_0_SLOT_CAP2 0x008c 238051199920SFeifei Xu #define cfgBIFPLR0_0_SLOT_CNTL2 0x0090 238151199920SFeifei Xu #define cfgBIFPLR0_0_SLOT_STATUS2 0x0092 238251199920SFeifei Xu #define cfgBIFPLR0_0_MSI_CAP_LIST 0x00a0 238351199920SFeifei Xu #define cfgBIFPLR0_0_MSI_MSG_CNTL 0x00a2 238451199920SFeifei Xu #define cfgBIFPLR0_0_MSI_MSG_ADDR_LO 0x00a4 238551199920SFeifei Xu #define cfgBIFPLR0_0_MSI_MSG_ADDR_HI 0x00a8 238651199920SFeifei Xu #define cfgBIFPLR0_0_MSI_MSG_DATA 0x00a8 238751199920SFeifei Xu #define cfgBIFPLR0_0_MSI_MSG_DATA_64 0x00ac 238851199920SFeifei Xu #define cfgBIFPLR0_0_SSID_CAP_LIST 0x00c0 238951199920SFeifei Xu #define cfgBIFPLR0_0_SSID_CAP 0x00c4 239051199920SFeifei Xu #define cfgBIFPLR0_0_MSI_MAP_CAP_LIST 0x00c8 239151199920SFeifei Xu #define cfgBIFPLR0_0_MSI_MAP_CAP 0x00ca 239251199920SFeifei Xu #define cfgBIFPLR0_0_MSI_MAP_ADDR_LO 0x00cc 239351199920SFeifei Xu #define cfgBIFPLR0_0_MSI_MAP_ADDR_HI 0x00d0 239451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 239551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 239651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC1 0x0108 239751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC2 0x010c 239851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VC_ENH_CAP_LIST 0x0110 239951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG1 0x0114 240051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG2 0x0118 240151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_PORT_VC_CNTL 0x011c 240251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_PORT_VC_STATUS 0x011e 240351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CAP 0x0120 240451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 240551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS 0x012a 240651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CAP 0x012c 240751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 240851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 240951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 241051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 241151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 241251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 241351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_UNCORR_ERR_STATUS 0x0154 241451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_UNCORR_ERR_MASK 0x0158 241551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 241651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_CORR_ERR_STATUS 0x0160 241751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_CORR_ERR_MASK 0x0164 241851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 241951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_HDR_LOG0 0x016c 242051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_HDR_LOG1 0x0170 242151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_HDR_LOG2 0x0174 242251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_HDR_LOG3 0x0178 242351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ROOT_ERR_CMD 0x017c 242451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ROOT_ERR_STATUS 0x0180 242551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ERR_SRC_ID 0x0184 242651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG0 0x0188 242751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG1 0x018c 242851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG2 0x0190 242951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG3 0x0194 243051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 243151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LINK_CNTL3 0x0274 243251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_ERROR_STATUS 0x0278 243351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 243451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 243551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 243651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 243751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 243851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 243951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 244051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 244151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 244251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 244351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 244451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 244551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 244651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 244751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 244851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 244951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 245051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ACS_CAP 0x02a4 245151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ACS_CNTL 0x02a6 245251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 245351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_CAP 0x02f4 245451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_CNTL 0x02f6 245551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_ADDR0 0x02f8 245651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_ADDR1 0x02fc 245751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_RCV0 0x0300 245851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_RCV1 0x0304 245951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL0 0x0308 246051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL1 0x030c 246151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 246251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 246351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR0 0x0318 246451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR1 0x031c 246551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 246651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP 0x0374 246751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL 0x0378 246851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2 0x037c 246951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST 0x0380 247051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_DPC_CAP_LIST 0x0384 247151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_DPC_CNTL 0x0386 247251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_DPC_STATUS 0x0388 247351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a 247451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_STATUS 0x038c 247551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_MASK 0x0390 247651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_SEVERITY 0x0394 247751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_SYSERROR 0x0398 247851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_EXCEPTION 0x039c 247951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 248051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 248151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 248251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3 0x03ac 248351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 248451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 248551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 248651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc 248751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 248851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_CAP_LIST 0x03c4 248951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_HEADER_1 0x03c8 249051199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_HEADER_2 0x03cc 249151199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_STATUS 0x03ce 249251199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_CTRL 0x03d0 249351199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_CAP_1 0x03d4 249451199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_CAP_2 0x03d8 249551199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_CAP_3 0x03dc 249651199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_CAP_4 0x03e0 249751199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_CAP_5 0x03e4 249851199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_CAP_6 0x03e8 249951199920SFeifei Xu #define cfgBIFPLR0_0_PCIE_ESM_CAP_7 0x03ec 250051199920SFeifei Xu 250151199920SFeifei Xu 250251199920SFeifei Xu // addressBlock: nbio_pcie0_bifplr1_cfgdecp 250351199920SFeifei Xu // base address: 0x0 250451199920SFeifei Xu #define cfgBIFPLR1_0_VENDOR_ID 0x0000 250551199920SFeifei Xu #define cfgBIFPLR1_0_DEVICE_ID 0x0002 250651199920SFeifei Xu #define cfgBIFPLR1_0_COMMAND 0x0004 250751199920SFeifei Xu #define cfgBIFPLR1_0_STATUS 0x0006 250851199920SFeifei Xu #define cfgBIFPLR1_0_REVISION_ID 0x0008 250951199920SFeifei Xu #define cfgBIFPLR1_0_PROG_INTERFACE 0x0009 251051199920SFeifei Xu #define cfgBIFPLR1_0_SUB_CLASS 0x000a 251151199920SFeifei Xu #define cfgBIFPLR1_0_BASE_CLASS 0x000b 251251199920SFeifei Xu #define cfgBIFPLR1_0_CACHE_LINE 0x000c 251351199920SFeifei Xu #define cfgBIFPLR1_0_LATENCY 0x000d 251451199920SFeifei Xu #define cfgBIFPLR1_0_HEADER 0x000e 251551199920SFeifei Xu #define cfgBIFPLR1_0_BIST 0x000f 251651199920SFeifei Xu #define cfgBIFPLR1_0_SUB_BUS_NUMBER_LATENCY 0x0018 251751199920SFeifei Xu #define cfgBIFPLR1_0_IO_BASE_LIMIT 0x001c 251851199920SFeifei Xu #define cfgBIFPLR1_0_SECONDARY_STATUS 0x001e 251951199920SFeifei Xu #define cfgBIFPLR1_0_MEM_BASE_LIMIT 0x0020 252051199920SFeifei Xu #define cfgBIFPLR1_0_PREF_BASE_LIMIT 0x0024 252151199920SFeifei Xu #define cfgBIFPLR1_0_PREF_BASE_UPPER 0x0028 252251199920SFeifei Xu #define cfgBIFPLR1_0_PREF_LIMIT_UPPER 0x002c 252351199920SFeifei Xu #define cfgBIFPLR1_0_IO_BASE_LIMIT_HI 0x0030 252451199920SFeifei Xu #define cfgBIFPLR1_0_CAP_PTR 0x0034 252551199920SFeifei Xu #define cfgBIFPLR1_0_INTERRUPT_LINE 0x003c 252651199920SFeifei Xu #define cfgBIFPLR1_0_INTERRUPT_PIN 0x003d 252751199920SFeifei Xu #define cfgBIFPLR1_0_IRQ_BRIDGE_CNTL 0x003e 252851199920SFeifei Xu #define cfgBIFPLR1_0_EXT_BRIDGE_CNTL 0x0040 252951199920SFeifei Xu #define cfgBIFPLR1_0_PMI_CAP_LIST 0x0050 253051199920SFeifei Xu #define cfgBIFPLR1_0_PMI_CAP 0x0052 253151199920SFeifei Xu #define cfgBIFPLR1_0_PMI_STATUS_CNTL 0x0054 253251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_CAP_LIST 0x0058 253351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_CAP 0x005a 253451199920SFeifei Xu #define cfgBIFPLR1_0_DEVICE_CAP 0x005c 253551199920SFeifei Xu #define cfgBIFPLR1_0_DEVICE_CNTL 0x0060 253651199920SFeifei Xu #define cfgBIFPLR1_0_DEVICE_STATUS 0x0062 253751199920SFeifei Xu #define cfgBIFPLR1_0_LINK_CAP 0x0064 253851199920SFeifei Xu #define cfgBIFPLR1_0_LINK_CNTL 0x0068 253951199920SFeifei Xu #define cfgBIFPLR1_0_LINK_STATUS 0x006a 254051199920SFeifei Xu #define cfgBIFPLR1_0_SLOT_CAP 0x006c 254151199920SFeifei Xu #define cfgBIFPLR1_0_SLOT_CNTL 0x0070 254251199920SFeifei Xu #define cfgBIFPLR1_0_SLOT_STATUS 0x0072 254351199920SFeifei Xu #define cfgBIFPLR1_0_ROOT_CNTL 0x0074 254451199920SFeifei Xu #define cfgBIFPLR1_0_ROOT_CAP 0x0076 254551199920SFeifei Xu #define cfgBIFPLR1_0_ROOT_STATUS 0x0078 254651199920SFeifei Xu #define cfgBIFPLR1_0_DEVICE_CAP2 0x007c 254751199920SFeifei Xu #define cfgBIFPLR1_0_DEVICE_CNTL2 0x0080 254851199920SFeifei Xu #define cfgBIFPLR1_0_DEVICE_STATUS2 0x0082 254951199920SFeifei Xu #define cfgBIFPLR1_0_LINK_CAP2 0x0084 255051199920SFeifei Xu #define cfgBIFPLR1_0_LINK_CNTL2 0x0088 255151199920SFeifei Xu #define cfgBIFPLR1_0_LINK_STATUS2 0x008a 255251199920SFeifei Xu #define cfgBIFPLR1_0_SLOT_CAP2 0x008c 255351199920SFeifei Xu #define cfgBIFPLR1_0_SLOT_CNTL2 0x0090 255451199920SFeifei Xu #define cfgBIFPLR1_0_SLOT_STATUS2 0x0092 255551199920SFeifei Xu #define cfgBIFPLR1_0_MSI_CAP_LIST 0x00a0 255651199920SFeifei Xu #define cfgBIFPLR1_0_MSI_MSG_CNTL 0x00a2 255751199920SFeifei Xu #define cfgBIFPLR1_0_MSI_MSG_ADDR_LO 0x00a4 255851199920SFeifei Xu #define cfgBIFPLR1_0_MSI_MSG_ADDR_HI 0x00a8 255951199920SFeifei Xu #define cfgBIFPLR1_0_MSI_MSG_DATA 0x00a8 256051199920SFeifei Xu #define cfgBIFPLR1_0_MSI_MSG_DATA_64 0x00ac 256151199920SFeifei Xu #define cfgBIFPLR1_0_SSID_CAP_LIST 0x00c0 256251199920SFeifei Xu #define cfgBIFPLR1_0_SSID_CAP 0x00c4 256351199920SFeifei Xu #define cfgBIFPLR1_0_MSI_MAP_CAP_LIST 0x00c8 256451199920SFeifei Xu #define cfgBIFPLR1_0_MSI_MAP_CAP 0x00ca 256551199920SFeifei Xu #define cfgBIFPLR1_0_MSI_MAP_ADDR_LO 0x00cc 256651199920SFeifei Xu #define cfgBIFPLR1_0_MSI_MAP_ADDR_HI 0x00d0 256751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 256851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 256951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC1 0x0108 257051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC2 0x010c 257151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VC_ENH_CAP_LIST 0x0110 257251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG1 0x0114 257351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG2 0x0118 257451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_PORT_VC_CNTL 0x011c 257551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_PORT_VC_STATUS 0x011e 257651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CAP 0x0120 257751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 257851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS 0x012a 257951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CAP 0x012c 258051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 258151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 258251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 258351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 258451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 258551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 258651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_UNCORR_ERR_STATUS 0x0154 258751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_UNCORR_ERR_MASK 0x0158 258851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 258951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_CORR_ERR_STATUS 0x0160 259051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_CORR_ERR_MASK 0x0164 259151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 259251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_HDR_LOG0 0x016c 259351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_HDR_LOG1 0x0170 259451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_HDR_LOG2 0x0174 259551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_HDR_LOG3 0x0178 259651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ROOT_ERR_CMD 0x017c 259751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ROOT_ERR_STATUS 0x0180 259851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ERR_SRC_ID 0x0184 259951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG0 0x0188 260051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG1 0x018c 260151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG2 0x0190 260251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG3 0x0194 260351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 260451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LINK_CNTL3 0x0274 260551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_ERROR_STATUS 0x0278 260651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 260751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 260851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 260951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 261051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 261151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 261251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 261351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 261451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 261551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 261651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 261751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 261851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 261951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 262051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 262151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 262251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 262351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ACS_CAP 0x02a4 262451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ACS_CNTL 0x02a6 262551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 262651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_CAP 0x02f4 262751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_CNTL 0x02f6 262851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_ADDR0 0x02f8 262951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_ADDR1 0x02fc 263051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_RCV0 0x0300 263151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_RCV1 0x0304 263251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL0 0x0308 263351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL1 0x030c 263451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 263551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 263651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR0 0x0318 263751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR1 0x031c 263851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 263951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP 0x0374 264051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL 0x0378 264151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2 0x037c 264251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST 0x0380 264351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_DPC_CAP_LIST 0x0384 264451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_DPC_CNTL 0x0386 264551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_DPC_STATUS 0x0388 264651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a 264751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_STATUS 0x038c 264851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_MASK 0x0390 264951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_SEVERITY 0x0394 265051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_SYSERROR 0x0398 265151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_EXCEPTION 0x039c 265251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 265351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 265451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 265551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3 0x03ac 265651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 265751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 265851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 265951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc 266051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 266151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_CAP_LIST 0x03c4 266251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_HEADER_1 0x03c8 266351199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_HEADER_2 0x03cc 266451199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_STATUS 0x03ce 266551199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_CTRL 0x03d0 266651199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_CAP_1 0x03d4 266751199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_CAP_2 0x03d8 266851199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_CAP_3 0x03dc 266951199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_CAP_4 0x03e0 267051199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_CAP_5 0x03e4 267151199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_CAP_6 0x03e8 267251199920SFeifei Xu #define cfgBIFPLR1_0_PCIE_ESM_CAP_7 0x03ec 267351199920SFeifei Xu 267451199920SFeifei Xu 267551199920SFeifei Xu // addressBlock: nbio_pcie0_bifplr2_cfgdecp 267651199920SFeifei Xu // base address: 0x0 267751199920SFeifei Xu #define cfgBIFPLR2_0_VENDOR_ID 0x0000 267851199920SFeifei Xu #define cfgBIFPLR2_0_DEVICE_ID 0x0002 267951199920SFeifei Xu #define cfgBIFPLR2_0_COMMAND 0x0004 268051199920SFeifei Xu #define cfgBIFPLR2_0_STATUS 0x0006 268151199920SFeifei Xu #define cfgBIFPLR2_0_REVISION_ID 0x0008 268251199920SFeifei Xu #define cfgBIFPLR2_0_PROG_INTERFACE 0x0009 268351199920SFeifei Xu #define cfgBIFPLR2_0_SUB_CLASS 0x000a 268451199920SFeifei Xu #define cfgBIFPLR2_0_BASE_CLASS 0x000b 268551199920SFeifei Xu #define cfgBIFPLR2_0_CACHE_LINE 0x000c 268651199920SFeifei Xu #define cfgBIFPLR2_0_LATENCY 0x000d 268751199920SFeifei Xu #define cfgBIFPLR2_0_HEADER 0x000e 268851199920SFeifei Xu #define cfgBIFPLR2_0_BIST 0x000f 268951199920SFeifei Xu #define cfgBIFPLR2_0_SUB_BUS_NUMBER_LATENCY 0x0018 269051199920SFeifei Xu #define cfgBIFPLR2_0_IO_BASE_LIMIT 0x001c 269151199920SFeifei Xu #define cfgBIFPLR2_0_SECONDARY_STATUS 0x001e 269251199920SFeifei Xu #define cfgBIFPLR2_0_MEM_BASE_LIMIT 0x0020 269351199920SFeifei Xu #define cfgBIFPLR2_0_PREF_BASE_LIMIT 0x0024 269451199920SFeifei Xu #define cfgBIFPLR2_0_PREF_BASE_UPPER 0x0028 269551199920SFeifei Xu #define cfgBIFPLR2_0_PREF_LIMIT_UPPER 0x002c 269651199920SFeifei Xu #define cfgBIFPLR2_0_IO_BASE_LIMIT_HI 0x0030 269751199920SFeifei Xu #define cfgBIFPLR2_0_CAP_PTR 0x0034 269851199920SFeifei Xu #define cfgBIFPLR2_0_INTERRUPT_LINE 0x003c 269951199920SFeifei Xu #define cfgBIFPLR2_0_INTERRUPT_PIN 0x003d 270051199920SFeifei Xu #define cfgBIFPLR2_0_IRQ_BRIDGE_CNTL 0x003e 270151199920SFeifei Xu #define cfgBIFPLR2_0_EXT_BRIDGE_CNTL 0x0040 270251199920SFeifei Xu #define cfgBIFPLR2_0_PMI_CAP_LIST 0x0050 270351199920SFeifei Xu #define cfgBIFPLR2_0_PMI_CAP 0x0052 270451199920SFeifei Xu #define cfgBIFPLR2_0_PMI_STATUS_CNTL 0x0054 270551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_CAP_LIST 0x0058 270651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_CAP 0x005a 270751199920SFeifei Xu #define cfgBIFPLR2_0_DEVICE_CAP 0x005c 270851199920SFeifei Xu #define cfgBIFPLR2_0_DEVICE_CNTL 0x0060 270951199920SFeifei Xu #define cfgBIFPLR2_0_DEVICE_STATUS 0x0062 271051199920SFeifei Xu #define cfgBIFPLR2_0_LINK_CAP 0x0064 271151199920SFeifei Xu #define cfgBIFPLR2_0_LINK_CNTL 0x0068 271251199920SFeifei Xu #define cfgBIFPLR2_0_LINK_STATUS 0x006a 271351199920SFeifei Xu #define cfgBIFPLR2_0_SLOT_CAP 0x006c 271451199920SFeifei Xu #define cfgBIFPLR2_0_SLOT_CNTL 0x0070 271551199920SFeifei Xu #define cfgBIFPLR2_0_SLOT_STATUS 0x0072 271651199920SFeifei Xu #define cfgBIFPLR2_0_ROOT_CNTL 0x0074 271751199920SFeifei Xu #define cfgBIFPLR2_0_ROOT_CAP 0x0076 271851199920SFeifei Xu #define cfgBIFPLR2_0_ROOT_STATUS 0x0078 271951199920SFeifei Xu #define cfgBIFPLR2_0_DEVICE_CAP2 0x007c 272051199920SFeifei Xu #define cfgBIFPLR2_0_DEVICE_CNTL2 0x0080 272151199920SFeifei Xu #define cfgBIFPLR2_0_DEVICE_STATUS2 0x0082 272251199920SFeifei Xu #define cfgBIFPLR2_0_LINK_CAP2 0x0084 272351199920SFeifei Xu #define cfgBIFPLR2_0_LINK_CNTL2 0x0088 272451199920SFeifei Xu #define cfgBIFPLR2_0_LINK_STATUS2 0x008a 272551199920SFeifei Xu #define cfgBIFPLR2_0_SLOT_CAP2 0x008c 272651199920SFeifei Xu #define cfgBIFPLR2_0_SLOT_CNTL2 0x0090 272751199920SFeifei Xu #define cfgBIFPLR2_0_SLOT_STATUS2 0x0092 272851199920SFeifei Xu #define cfgBIFPLR2_0_MSI_CAP_LIST 0x00a0 272951199920SFeifei Xu #define cfgBIFPLR2_0_MSI_MSG_CNTL 0x00a2 273051199920SFeifei Xu #define cfgBIFPLR2_0_MSI_MSG_ADDR_LO 0x00a4 273151199920SFeifei Xu #define cfgBIFPLR2_0_MSI_MSG_ADDR_HI 0x00a8 273251199920SFeifei Xu #define cfgBIFPLR2_0_MSI_MSG_DATA 0x00a8 273351199920SFeifei Xu #define cfgBIFPLR2_0_MSI_MSG_DATA_64 0x00ac 273451199920SFeifei Xu #define cfgBIFPLR2_0_SSID_CAP_LIST 0x00c0 273551199920SFeifei Xu #define cfgBIFPLR2_0_SSID_CAP 0x00c4 273651199920SFeifei Xu #define cfgBIFPLR2_0_MSI_MAP_CAP_LIST 0x00c8 273751199920SFeifei Xu #define cfgBIFPLR2_0_MSI_MAP_CAP 0x00ca 273851199920SFeifei Xu #define cfgBIFPLR2_0_MSI_MAP_ADDR_LO 0x00cc 273951199920SFeifei Xu #define cfgBIFPLR2_0_MSI_MAP_ADDR_HI 0x00d0 274051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 274151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 274251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC1 0x0108 274351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC2 0x010c 274451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VC_ENH_CAP_LIST 0x0110 274551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG1 0x0114 274651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG2 0x0118 274751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_PORT_VC_CNTL 0x011c 274851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_PORT_VC_STATUS 0x011e 274951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CAP 0x0120 275051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL 0x0124 275151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS 0x012a 275251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CAP 0x012c 275351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL 0x0130 275451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS 0x0136 275551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 275651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 275751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 275851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 275951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_UNCORR_ERR_STATUS 0x0154 276051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_UNCORR_ERR_MASK 0x0158 276151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 276251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_CORR_ERR_STATUS 0x0160 276351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_CORR_ERR_MASK 0x0164 276451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 276551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_HDR_LOG0 0x016c 276651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_HDR_LOG1 0x0170 276751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_HDR_LOG2 0x0174 276851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_HDR_LOG3 0x0178 276951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ROOT_ERR_CMD 0x017c 277051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ROOT_ERR_STATUS 0x0180 277151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ERR_SRC_ID 0x0184 277251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG0 0x0188 277351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG1 0x018c 277451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG2 0x0190 277551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG3 0x0194 277651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 277751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LINK_CNTL3 0x0274 277851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_ERROR_STATUS 0x0278 277951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 278051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 278151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 278251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 278351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 278451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 278551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 278651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 278751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 278851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 278951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 279051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 279151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 279251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 279351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 279451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 279551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 279651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ACS_CAP 0x02a4 279751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ACS_CNTL 0x02a6 279851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_ENH_CAP_LIST 0x02f0 279951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_CAP 0x02f4 280051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_CNTL 0x02f6 280151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_ADDR0 0x02f8 280251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_ADDR1 0x02fc 280351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_RCV0 0x0300 280451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_RCV1 0x0304 280551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL0 0x0308 280651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL1 0x030c 280751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 280851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 280951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR0 0x0318 281051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR1 0x031c 281151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 281251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP 0x0374 281351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL 0x0378 281451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2 0x037c 281551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST 0x0380 281651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_DPC_CAP_LIST 0x0384 281751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_DPC_CNTL 0x0386 281851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_DPC_STATUS 0x0388 281951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a 282051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_STATUS 0x038c 282151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_MASK 0x0390 282251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_SEVERITY 0x0394 282351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_SYSERROR 0x0398 282451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_EXCEPTION 0x039c 282551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 282651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 282751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 282851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3 0x03ac 282951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 283051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 283151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 283251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc 283351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 283451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_CAP_LIST 0x03c4 283551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_HEADER_1 0x03c8 283651199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_HEADER_2 0x03cc 283751199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_STATUS 0x03ce 283851199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_CTRL 0x03d0 283951199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_CAP_1 0x03d4 284051199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_CAP_2 0x03d8 284151199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_CAP_3 0x03dc 284251199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_CAP_4 0x03e0 284351199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_CAP_5 0x03e4 284451199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_CAP_6 0x03e8 284551199920SFeifei Xu #define cfgBIFPLR2_0_PCIE_ESM_CAP_7 0x03ec 284651199920SFeifei Xu 284751199920SFeifei Xu 284851199920SFeifei Xu // addressBlock: nbio_pcie0_bifplr3_cfgdecp 284951199920SFeifei Xu // base address: 0x0 285051199920SFeifei Xu #define cfgBIFPLR3_0_VENDOR_ID 0x0000 285151199920SFeifei Xu #define cfgBIFPLR3_0_DEVICE_ID 0x0002 285251199920SFeifei Xu #define cfgBIFPLR3_0_COMMAND 0x0004 285351199920SFeifei Xu #define cfgBIFPLR3_0_STATUS 0x0006 285451199920SFeifei Xu #define cfgBIFPLR3_0_REVISION_ID 0x0008 285551199920SFeifei Xu #define cfgBIFPLR3_0_PROG_INTERFACE 0x0009 285651199920SFeifei Xu #define cfgBIFPLR3_0_SUB_CLASS 0x000a 285751199920SFeifei Xu #define cfgBIFPLR3_0_BASE_CLASS 0x000b 285851199920SFeifei Xu #define cfgBIFPLR3_0_CACHE_LINE 0x000c 285951199920SFeifei Xu #define cfgBIFPLR3_0_LATENCY 0x000d 286051199920SFeifei Xu #define cfgBIFPLR3_0_HEADER 0x000e 286151199920SFeifei Xu #define cfgBIFPLR3_0_BIST 0x000f 286251199920SFeifei Xu #define cfgBIFPLR3_0_SUB_BUS_NUMBER_LATENCY 0x0018 286351199920SFeifei Xu #define cfgBIFPLR3_0_IO_BASE_LIMIT 0x001c 286451199920SFeifei Xu #define cfgBIFPLR3_0_SECONDARY_STATUS 0x001e 286551199920SFeifei Xu #define cfgBIFPLR3_0_MEM_BASE_LIMIT 0x0020 286651199920SFeifei Xu #define cfgBIFPLR3_0_PREF_BASE_LIMIT 0x0024 286751199920SFeifei Xu #define cfgBIFPLR3_0_PREF_BASE_UPPER 0x0028 286851199920SFeifei Xu #define cfgBIFPLR3_0_PREF_LIMIT_UPPER 0x002c 286951199920SFeifei Xu #define cfgBIFPLR3_0_IO_BASE_LIMIT_HI 0x0030 287051199920SFeifei Xu #define cfgBIFPLR3_0_CAP_PTR 0x0034 287151199920SFeifei Xu #define cfgBIFPLR3_0_INTERRUPT_LINE 0x003c 287251199920SFeifei Xu #define cfgBIFPLR3_0_INTERRUPT_PIN 0x003d 287351199920SFeifei Xu #define cfgBIFPLR3_0_IRQ_BRIDGE_CNTL 0x003e 287451199920SFeifei Xu #define cfgBIFPLR3_0_EXT_BRIDGE_CNTL 0x0040 287551199920SFeifei Xu #define cfgBIFPLR3_0_PMI_CAP_LIST 0x0050 287651199920SFeifei Xu #define cfgBIFPLR3_0_PMI_CAP 0x0052 287751199920SFeifei Xu #define cfgBIFPLR3_0_PMI_STATUS_CNTL 0x0054 287851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_CAP_LIST 0x0058 287951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_CAP 0x005a 288051199920SFeifei Xu #define cfgBIFPLR3_0_DEVICE_CAP 0x005c 288151199920SFeifei Xu #define cfgBIFPLR3_0_DEVICE_CNTL 0x0060 288251199920SFeifei Xu #define cfgBIFPLR3_0_DEVICE_STATUS 0x0062 288351199920SFeifei Xu #define cfgBIFPLR3_0_LINK_CAP 0x0064 288451199920SFeifei Xu #define cfgBIFPLR3_0_LINK_CNTL 0x0068 288551199920SFeifei Xu #define cfgBIFPLR3_0_LINK_STATUS 0x006a 288651199920SFeifei Xu #define cfgBIFPLR3_0_SLOT_CAP 0x006c 288751199920SFeifei Xu #define cfgBIFPLR3_0_SLOT_CNTL 0x0070 288851199920SFeifei Xu #define cfgBIFPLR3_0_SLOT_STATUS 0x0072 288951199920SFeifei Xu #define cfgBIFPLR3_0_ROOT_CNTL 0x0074 289051199920SFeifei Xu #define cfgBIFPLR3_0_ROOT_CAP 0x0076 289151199920SFeifei Xu #define cfgBIFPLR3_0_ROOT_STATUS 0x0078 289251199920SFeifei Xu #define cfgBIFPLR3_0_DEVICE_CAP2 0x007c 289351199920SFeifei Xu #define cfgBIFPLR3_0_DEVICE_CNTL2 0x0080 289451199920SFeifei Xu #define cfgBIFPLR3_0_DEVICE_STATUS2 0x0082 289551199920SFeifei Xu #define cfgBIFPLR3_0_LINK_CAP2 0x0084 289651199920SFeifei Xu #define cfgBIFPLR3_0_LINK_CNTL2 0x0088 289751199920SFeifei Xu #define cfgBIFPLR3_0_LINK_STATUS2 0x008a 289851199920SFeifei Xu #define cfgBIFPLR3_0_SLOT_CAP2 0x008c 289951199920SFeifei Xu #define cfgBIFPLR3_0_SLOT_CNTL2 0x0090 290051199920SFeifei Xu #define cfgBIFPLR3_0_SLOT_STATUS2 0x0092 290151199920SFeifei Xu #define cfgBIFPLR3_0_MSI_CAP_LIST 0x00a0 290251199920SFeifei Xu #define cfgBIFPLR3_0_MSI_MSG_CNTL 0x00a2 290351199920SFeifei Xu #define cfgBIFPLR3_0_MSI_MSG_ADDR_LO 0x00a4 290451199920SFeifei Xu #define cfgBIFPLR3_0_MSI_MSG_ADDR_HI 0x00a8 290551199920SFeifei Xu #define cfgBIFPLR3_0_MSI_MSG_DATA 0x00a8 290651199920SFeifei Xu #define cfgBIFPLR3_0_MSI_MSG_DATA_64 0x00ac 290751199920SFeifei Xu #define cfgBIFPLR3_0_SSID_CAP_LIST 0x00c0 290851199920SFeifei Xu #define cfgBIFPLR3_0_SSID_CAP 0x00c4 290951199920SFeifei Xu #define cfgBIFPLR3_0_MSI_MAP_CAP_LIST 0x00c8 291051199920SFeifei Xu #define cfgBIFPLR3_0_MSI_MAP_CAP 0x00ca 291151199920SFeifei Xu #define cfgBIFPLR3_0_MSI_MAP_ADDR_LO 0x00cc 291251199920SFeifei Xu #define cfgBIFPLR3_0_MSI_MAP_ADDR_HI 0x00d0 291351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 291451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 291551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC1 0x0108 291651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC2 0x010c 291751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VC_ENH_CAP_LIST 0x0110 291851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG1 0x0114 291951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG2 0x0118 292051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_PORT_VC_CNTL 0x011c 292151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_PORT_VC_STATUS 0x011e 292251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CAP 0x0120 292351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL 0x0124 292451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS 0x012a 292551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CAP 0x012c 292651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL 0x0130 292751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS 0x0136 292851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 292951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 293051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 293151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 293251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_UNCORR_ERR_STATUS 0x0154 293351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_UNCORR_ERR_MASK 0x0158 293451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 293551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_CORR_ERR_STATUS 0x0160 293651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_CORR_ERR_MASK 0x0164 293751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 293851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_HDR_LOG0 0x016c 293951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_HDR_LOG1 0x0170 294051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_HDR_LOG2 0x0174 294151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_HDR_LOG3 0x0178 294251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ROOT_ERR_CMD 0x017c 294351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ROOT_ERR_STATUS 0x0180 294451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ERR_SRC_ID 0x0184 294551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG0 0x0188 294651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG1 0x018c 294751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG2 0x0190 294851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG3 0x0194 294951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 295051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LINK_CNTL3 0x0274 295151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_ERROR_STATUS 0x0278 295251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 295351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 295451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 295551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 295651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 295751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 295851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 295951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 296051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 296151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 296251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 296351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 296451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 296551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 296651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 296751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 296851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 296951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ACS_CAP 0x02a4 297051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ACS_CNTL 0x02a6 297151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_ENH_CAP_LIST 0x02f0 297251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_CAP 0x02f4 297351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_CNTL 0x02f6 297451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_ADDR0 0x02f8 297551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_ADDR1 0x02fc 297651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_RCV0 0x0300 297751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_RCV1 0x0304 297851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL0 0x0308 297951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL1 0x030c 298051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 298151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 298251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR0 0x0318 298351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR1 0x031c 298451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 298551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP 0x0374 298651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL 0x0378 298751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2 0x037c 298851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST 0x0380 298951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_DPC_CAP_LIST 0x0384 299051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_DPC_CNTL 0x0386 299151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_DPC_STATUS 0x0388 299251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a 299351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_STATUS 0x038c 299451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_MASK 0x0390 299551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_SEVERITY 0x0394 299651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_SYSERROR 0x0398 299751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_EXCEPTION 0x039c 299851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 299951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 300051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 300151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3 0x03ac 300251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 300351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 300451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 300551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc 300651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 300751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_CAP_LIST 0x03c4 300851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_HEADER_1 0x03c8 300951199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_HEADER_2 0x03cc 301051199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_STATUS 0x03ce 301151199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_CTRL 0x03d0 301251199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_CAP_1 0x03d4 301351199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_CAP_2 0x03d8 301451199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_CAP_3 0x03dc 301551199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_CAP_4 0x03e0 301651199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_CAP_5 0x03e4 301751199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_CAP_6 0x03e8 301851199920SFeifei Xu #define cfgBIFPLR3_0_PCIE_ESM_CAP_7 0x03ec 301951199920SFeifei Xu 302051199920SFeifei Xu 302151199920SFeifei Xu // addressBlock: nbio_pcie0_bifplr4_cfgdecp 302251199920SFeifei Xu // base address: 0x0 302351199920SFeifei Xu #define cfgBIFPLR4_0_VENDOR_ID 0x0000 302451199920SFeifei Xu #define cfgBIFPLR4_0_DEVICE_ID 0x0002 302551199920SFeifei Xu #define cfgBIFPLR4_0_COMMAND 0x0004 302651199920SFeifei Xu #define cfgBIFPLR4_0_STATUS 0x0006 302751199920SFeifei Xu #define cfgBIFPLR4_0_REVISION_ID 0x0008 302851199920SFeifei Xu #define cfgBIFPLR4_0_PROG_INTERFACE 0x0009 302951199920SFeifei Xu #define cfgBIFPLR4_0_SUB_CLASS 0x000a 303051199920SFeifei Xu #define cfgBIFPLR4_0_BASE_CLASS 0x000b 303151199920SFeifei Xu #define cfgBIFPLR4_0_CACHE_LINE 0x000c 303251199920SFeifei Xu #define cfgBIFPLR4_0_LATENCY 0x000d 303351199920SFeifei Xu #define cfgBIFPLR4_0_HEADER 0x000e 303451199920SFeifei Xu #define cfgBIFPLR4_0_BIST 0x000f 303551199920SFeifei Xu #define cfgBIFPLR4_0_SUB_BUS_NUMBER_LATENCY 0x0018 303651199920SFeifei Xu #define cfgBIFPLR4_0_IO_BASE_LIMIT 0x001c 303751199920SFeifei Xu #define cfgBIFPLR4_0_SECONDARY_STATUS 0x001e 303851199920SFeifei Xu #define cfgBIFPLR4_0_MEM_BASE_LIMIT 0x0020 303951199920SFeifei Xu #define cfgBIFPLR4_0_PREF_BASE_LIMIT 0x0024 304051199920SFeifei Xu #define cfgBIFPLR4_0_PREF_BASE_UPPER 0x0028 304151199920SFeifei Xu #define cfgBIFPLR4_0_PREF_LIMIT_UPPER 0x002c 304251199920SFeifei Xu #define cfgBIFPLR4_0_IO_BASE_LIMIT_HI 0x0030 304351199920SFeifei Xu #define cfgBIFPLR4_0_CAP_PTR 0x0034 304451199920SFeifei Xu #define cfgBIFPLR4_0_INTERRUPT_LINE 0x003c 304551199920SFeifei Xu #define cfgBIFPLR4_0_INTERRUPT_PIN 0x003d 304651199920SFeifei Xu #define cfgBIFPLR4_0_IRQ_BRIDGE_CNTL 0x003e 304751199920SFeifei Xu #define cfgBIFPLR4_0_EXT_BRIDGE_CNTL 0x0040 304851199920SFeifei Xu #define cfgBIFPLR4_0_PMI_CAP_LIST 0x0050 304951199920SFeifei Xu #define cfgBIFPLR4_0_PMI_CAP 0x0052 305051199920SFeifei Xu #define cfgBIFPLR4_0_PMI_STATUS_CNTL 0x0054 305151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_CAP_LIST 0x0058 305251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_CAP 0x005a 305351199920SFeifei Xu #define cfgBIFPLR4_0_DEVICE_CAP 0x005c 305451199920SFeifei Xu #define cfgBIFPLR4_0_DEVICE_CNTL 0x0060 305551199920SFeifei Xu #define cfgBIFPLR4_0_DEVICE_STATUS 0x0062 305651199920SFeifei Xu #define cfgBIFPLR4_0_LINK_CAP 0x0064 305751199920SFeifei Xu #define cfgBIFPLR4_0_LINK_CNTL 0x0068 305851199920SFeifei Xu #define cfgBIFPLR4_0_LINK_STATUS 0x006a 305951199920SFeifei Xu #define cfgBIFPLR4_0_SLOT_CAP 0x006c 306051199920SFeifei Xu #define cfgBIFPLR4_0_SLOT_CNTL 0x0070 306151199920SFeifei Xu #define cfgBIFPLR4_0_SLOT_STATUS 0x0072 306251199920SFeifei Xu #define cfgBIFPLR4_0_ROOT_CNTL 0x0074 306351199920SFeifei Xu #define cfgBIFPLR4_0_ROOT_CAP 0x0076 306451199920SFeifei Xu #define cfgBIFPLR4_0_ROOT_STATUS 0x0078 306551199920SFeifei Xu #define cfgBIFPLR4_0_DEVICE_CAP2 0x007c 306651199920SFeifei Xu #define cfgBIFPLR4_0_DEVICE_CNTL2 0x0080 306751199920SFeifei Xu #define cfgBIFPLR4_0_DEVICE_STATUS2 0x0082 306851199920SFeifei Xu #define cfgBIFPLR4_0_LINK_CAP2 0x0084 306951199920SFeifei Xu #define cfgBIFPLR4_0_LINK_CNTL2 0x0088 307051199920SFeifei Xu #define cfgBIFPLR4_0_LINK_STATUS2 0x008a 307151199920SFeifei Xu #define cfgBIFPLR4_0_SLOT_CAP2 0x008c 307251199920SFeifei Xu #define cfgBIFPLR4_0_SLOT_CNTL2 0x0090 307351199920SFeifei Xu #define cfgBIFPLR4_0_SLOT_STATUS2 0x0092 307451199920SFeifei Xu #define cfgBIFPLR4_0_MSI_CAP_LIST 0x00a0 307551199920SFeifei Xu #define cfgBIFPLR4_0_MSI_MSG_CNTL 0x00a2 307651199920SFeifei Xu #define cfgBIFPLR4_0_MSI_MSG_ADDR_LO 0x00a4 307751199920SFeifei Xu #define cfgBIFPLR4_0_MSI_MSG_ADDR_HI 0x00a8 307851199920SFeifei Xu #define cfgBIFPLR4_0_MSI_MSG_DATA 0x00a8 307951199920SFeifei Xu #define cfgBIFPLR4_0_MSI_MSG_DATA_64 0x00ac 308051199920SFeifei Xu #define cfgBIFPLR4_0_SSID_CAP_LIST 0x00c0 308151199920SFeifei Xu #define cfgBIFPLR4_0_SSID_CAP 0x00c4 308251199920SFeifei Xu #define cfgBIFPLR4_0_MSI_MAP_CAP_LIST 0x00c8 308351199920SFeifei Xu #define cfgBIFPLR4_0_MSI_MAP_CAP 0x00ca 308451199920SFeifei Xu #define cfgBIFPLR4_0_MSI_MAP_ADDR_LO 0x00cc 308551199920SFeifei Xu #define cfgBIFPLR4_0_MSI_MAP_ADDR_HI 0x00d0 308651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 308751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 308851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC1 0x0108 308951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC2 0x010c 309051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VC_ENH_CAP_LIST 0x0110 309151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG1 0x0114 309251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG2 0x0118 309351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_PORT_VC_CNTL 0x011c 309451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_PORT_VC_STATUS 0x011e 309551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CAP 0x0120 309651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL 0x0124 309751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS 0x012a 309851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CAP 0x012c 309951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL 0x0130 310051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS 0x0136 310151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 310251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 310351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 310451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 310551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_UNCORR_ERR_STATUS 0x0154 310651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_UNCORR_ERR_MASK 0x0158 310751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 310851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_CORR_ERR_STATUS 0x0160 310951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_CORR_ERR_MASK 0x0164 311051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 311151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_HDR_LOG0 0x016c 311251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_HDR_LOG1 0x0170 311351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_HDR_LOG2 0x0174 311451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_HDR_LOG3 0x0178 311551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ROOT_ERR_CMD 0x017c 311651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ROOT_ERR_STATUS 0x0180 311751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ERR_SRC_ID 0x0184 311851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG0 0x0188 311951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG1 0x018c 312051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG2 0x0190 312151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG3 0x0194 312251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 312351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LINK_CNTL3 0x0274 312451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_ERROR_STATUS 0x0278 312551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 312651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 312751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 312851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 312951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 313051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 313151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 313251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 313351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 313451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 313551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 313651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 313751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 313851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 313951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 314051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 314151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 314251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ACS_CAP 0x02a4 314351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ACS_CNTL 0x02a6 314451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_ENH_CAP_LIST 0x02f0 314551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_CAP 0x02f4 314651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_CNTL 0x02f6 314751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_ADDR0 0x02f8 314851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_ADDR1 0x02fc 314951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_RCV0 0x0300 315051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_RCV1 0x0304 315151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL0 0x0308 315251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL1 0x030c 315351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 315451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 315551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR0 0x0318 315651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR1 0x031c 315751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 315851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP 0x0374 315951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL 0x0378 316051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2 0x037c 316151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST 0x0380 316251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_DPC_CAP_LIST 0x0384 316351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_DPC_CNTL 0x0386 316451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_DPC_STATUS 0x0388 316551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a 316651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_STATUS 0x038c 316751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_MASK 0x0390 316851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_SEVERITY 0x0394 316951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_SYSERROR 0x0398 317051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_EXCEPTION 0x039c 317151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 317251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 317351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 317451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3 0x03ac 317551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 317651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 317751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 317851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc 317951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 318051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_CAP_LIST 0x03c4 318151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_HEADER_1 0x03c8 318251199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_HEADER_2 0x03cc 318351199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_STATUS 0x03ce 318451199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_CTRL 0x03d0 318551199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_CAP_1 0x03d4 318651199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_CAP_2 0x03d8 318751199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_CAP_3 0x03dc 318851199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_CAP_4 0x03e0 318951199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_CAP_5 0x03e4 319051199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_CAP_6 0x03e8 319151199920SFeifei Xu #define cfgBIFPLR4_0_PCIE_ESM_CAP_7 0x03ec 319251199920SFeifei Xu 319351199920SFeifei Xu 319451199920SFeifei Xu // addressBlock: nbio_pcie0_bifplr5_cfgdecp 319551199920SFeifei Xu // base address: 0x0 319651199920SFeifei Xu #define cfgBIFPLR5_0_VENDOR_ID 0x0000 319751199920SFeifei Xu #define cfgBIFPLR5_0_DEVICE_ID 0x0002 319851199920SFeifei Xu #define cfgBIFPLR5_0_COMMAND 0x0004 319951199920SFeifei Xu #define cfgBIFPLR5_0_STATUS 0x0006 320051199920SFeifei Xu #define cfgBIFPLR5_0_REVISION_ID 0x0008 320151199920SFeifei Xu #define cfgBIFPLR5_0_PROG_INTERFACE 0x0009 320251199920SFeifei Xu #define cfgBIFPLR5_0_SUB_CLASS 0x000a 320351199920SFeifei Xu #define cfgBIFPLR5_0_BASE_CLASS 0x000b 320451199920SFeifei Xu #define cfgBIFPLR5_0_CACHE_LINE 0x000c 320551199920SFeifei Xu #define cfgBIFPLR5_0_LATENCY 0x000d 320651199920SFeifei Xu #define cfgBIFPLR5_0_HEADER 0x000e 320751199920SFeifei Xu #define cfgBIFPLR5_0_BIST 0x000f 320851199920SFeifei Xu #define cfgBIFPLR5_0_SUB_BUS_NUMBER_LATENCY 0x0018 320951199920SFeifei Xu #define cfgBIFPLR5_0_IO_BASE_LIMIT 0x001c 321051199920SFeifei Xu #define cfgBIFPLR5_0_SECONDARY_STATUS 0x001e 321151199920SFeifei Xu #define cfgBIFPLR5_0_MEM_BASE_LIMIT 0x0020 321251199920SFeifei Xu #define cfgBIFPLR5_0_PREF_BASE_LIMIT 0x0024 321351199920SFeifei Xu #define cfgBIFPLR5_0_PREF_BASE_UPPER 0x0028 321451199920SFeifei Xu #define cfgBIFPLR5_0_PREF_LIMIT_UPPER 0x002c 321551199920SFeifei Xu #define cfgBIFPLR5_0_IO_BASE_LIMIT_HI 0x0030 321651199920SFeifei Xu #define cfgBIFPLR5_0_CAP_PTR 0x0034 321751199920SFeifei Xu #define cfgBIFPLR5_0_INTERRUPT_LINE 0x003c 321851199920SFeifei Xu #define cfgBIFPLR5_0_INTERRUPT_PIN 0x003d 321951199920SFeifei Xu #define cfgBIFPLR5_0_IRQ_BRIDGE_CNTL 0x003e 322051199920SFeifei Xu #define cfgBIFPLR5_0_EXT_BRIDGE_CNTL 0x0040 322151199920SFeifei Xu #define cfgBIFPLR5_0_PMI_CAP_LIST 0x0050 322251199920SFeifei Xu #define cfgBIFPLR5_0_PMI_CAP 0x0052 322351199920SFeifei Xu #define cfgBIFPLR5_0_PMI_STATUS_CNTL 0x0054 322451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_CAP_LIST 0x0058 322551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_CAP 0x005a 322651199920SFeifei Xu #define cfgBIFPLR5_0_DEVICE_CAP 0x005c 322751199920SFeifei Xu #define cfgBIFPLR5_0_DEVICE_CNTL 0x0060 322851199920SFeifei Xu #define cfgBIFPLR5_0_DEVICE_STATUS 0x0062 322951199920SFeifei Xu #define cfgBIFPLR5_0_LINK_CAP 0x0064 323051199920SFeifei Xu #define cfgBIFPLR5_0_LINK_CNTL 0x0068 323151199920SFeifei Xu #define cfgBIFPLR5_0_LINK_STATUS 0x006a 323251199920SFeifei Xu #define cfgBIFPLR5_0_SLOT_CAP 0x006c 323351199920SFeifei Xu #define cfgBIFPLR5_0_SLOT_CNTL 0x0070 323451199920SFeifei Xu #define cfgBIFPLR5_0_SLOT_STATUS 0x0072 323551199920SFeifei Xu #define cfgBIFPLR5_0_ROOT_CNTL 0x0074 323651199920SFeifei Xu #define cfgBIFPLR5_0_ROOT_CAP 0x0076 323751199920SFeifei Xu #define cfgBIFPLR5_0_ROOT_STATUS 0x0078 323851199920SFeifei Xu #define cfgBIFPLR5_0_DEVICE_CAP2 0x007c 323951199920SFeifei Xu #define cfgBIFPLR5_0_DEVICE_CNTL2 0x0080 324051199920SFeifei Xu #define cfgBIFPLR5_0_DEVICE_STATUS2 0x0082 324151199920SFeifei Xu #define cfgBIFPLR5_0_LINK_CAP2 0x0084 324251199920SFeifei Xu #define cfgBIFPLR5_0_LINK_CNTL2 0x0088 324351199920SFeifei Xu #define cfgBIFPLR5_0_LINK_STATUS2 0x008a 324451199920SFeifei Xu #define cfgBIFPLR5_0_SLOT_CAP2 0x008c 324551199920SFeifei Xu #define cfgBIFPLR5_0_SLOT_CNTL2 0x0090 324651199920SFeifei Xu #define cfgBIFPLR5_0_SLOT_STATUS2 0x0092 324751199920SFeifei Xu #define cfgBIFPLR5_0_MSI_CAP_LIST 0x00a0 324851199920SFeifei Xu #define cfgBIFPLR5_0_MSI_MSG_CNTL 0x00a2 324951199920SFeifei Xu #define cfgBIFPLR5_0_MSI_MSG_ADDR_LO 0x00a4 325051199920SFeifei Xu #define cfgBIFPLR5_0_MSI_MSG_ADDR_HI 0x00a8 325151199920SFeifei Xu #define cfgBIFPLR5_0_MSI_MSG_DATA 0x00a8 325251199920SFeifei Xu #define cfgBIFPLR5_0_MSI_MSG_DATA_64 0x00ac 325351199920SFeifei Xu #define cfgBIFPLR5_0_SSID_CAP_LIST 0x00c0 325451199920SFeifei Xu #define cfgBIFPLR5_0_SSID_CAP 0x00c4 325551199920SFeifei Xu #define cfgBIFPLR5_0_MSI_MAP_CAP_LIST 0x00c8 325651199920SFeifei Xu #define cfgBIFPLR5_0_MSI_MAP_CAP 0x00ca 325751199920SFeifei Xu #define cfgBIFPLR5_0_MSI_MAP_ADDR_LO 0x00cc 325851199920SFeifei Xu #define cfgBIFPLR5_0_MSI_MAP_ADDR_HI 0x00d0 325951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 326051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 326151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC1 0x0108 326251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC2 0x010c 326351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VC_ENH_CAP_LIST 0x0110 326451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG1 0x0114 326551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG2 0x0118 326651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_PORT_VC_CNTL 0x011c 326751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_PORT_VC_STATUS 0x011e 326851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CAP 0x0120 326951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL 0x0124 327051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS 0x012a 327151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CAP 0x012c 327251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL 0x0130 327351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS 0x0136 327451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 327551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 327651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 327751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 327851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_UNCORR_ERR_STATUS 0x0154 327951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_UNCORR_ERR_MASK 0x0158 328051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 328151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_CORR_ERR_STATUS 0x0160 328251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_CORR_ERR_MASK 0x0164 328351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 328451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_HDR_LOG0 0x016c 328551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_HDR_LOG1 0x0170 328651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_HDR_LOG2 0x0174 328751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_HDR_LOG3 0x0178 328851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ROOT_ERR_CMD 0x017c 328951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ROOT_ERR_STATUS 0x0180 329051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ERR_SRC_ID 0x0184 329151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG0 0x0188 329251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG1 0x018c 329351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG2 0x0190 329451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG3 0x0194 329551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 329651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LINK_CNTL3 0x0274 329751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_ERROR_STATUS 0x0278 329851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 329951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 330051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 330151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 330251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 330351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 330451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 330551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 330651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 330751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 330851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 330951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 331051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 331151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 331251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 331351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 331451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 331551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ACS_CAP 0x02a4 331651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ACS_CNTL 0x02a6 331751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_ENH_CAP_LIST 0x02f0 331851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_CAP 0x02f4 331951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_CNTL 0x02f6 332051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_ADDR0 0x02f8 332151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_ADDR1 0x02fc 332251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_RCV0 0x0300 332351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_RCV1 0x0304 332451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL0 0x0308 332551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL1 0x030c 332651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 332751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 332851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR0 0x0318 332951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR1 0x031c 333051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 333151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP 0x0374 333251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL 0x0378 333351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2 0x037c 333451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST 0x0380 333551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_DPC_CAP_LIST 0x0384 333651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_DPC_CNTL 0x0386 333751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_DPC_STATUS 0x0388 333851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a 333951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_STATUS 0x038c 334051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_MASK 0x0390 334151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_SEVERITY 0x0394 334251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_SYSERROR 0x0398 334351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_EXCEPTION 0x039c 334451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 334551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 334651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 334751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3 0x03ac 334851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 334951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 335051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 335151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc 335251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 335351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_CAP_LIST 0x03c4 335451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_HEADER_1 0x03c8 335551199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_HEADER_2 0x03cc 335651199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_STATUS 0x03ce 335751199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_CTRL 0x03d0 335851199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_CAP_1 0x03d4 335951199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_CAP_2 0x03d8 336051199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_CAP_3 0x03dc 336151199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_CAP_4 0x03e0 336251199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_CAP_5 0x03e4 336351199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_CAP_6 0x03e8 336451199920SFeifei Xu #define cfgBIFPLR5_0_PCIE_ESM_CAP_7 0x03ec 336551199920SFeifei Xu 336651199920SFeifei Xu 336751199920SFeifei Xu // addressBlock: nbio_pcie0_bifplr6_cfgdecp 336851199920SFeifei Xu // base address: 0x0 336951199920SFeifei Xu #define cfgBIFPLR6_0_VENDOR_ID 0x0000 337051199920SFeifei Xu #define cfgBIFPLR6_0_DEVICE_ID 0x0002 337151199920SFeifei Xu #define cfgBIFPLR6_0_COMMAND 0x0004 337251199920SFeifei Xu #define cfgBIFPLR6_0_STATUS 0x0006 337351199920SFeifei Xu #define cfgBIFPLR6_0_REVISION_ID 0x0008 337451199920SFeifei Xu #define cfgBIFPLR6_0_PROG_INTERFACE 0x0009 337551199920SFeifei Xu #define cfgBIFPLR6_0_SUB_CLASS 0x000a 337651199920SFeifei Xu #define cfgBIFPLR6_0_BASE_CLASS 0x000b 337751199920SFeifei Xu #define cfgBIFPLR6_0_CACHE_LINE 0x000c 337851199920SFeifei Xu #define cfgBIFPLR6_0_LATENCY 0x000d 337951199920SFeifei Xu #define cfgBIFPLR6_0_HEADER 0x000e 338051199920SFeifei Xu #define cfgBIFPLR6_0_BIST 0x000f 338151199920SFeifei Xu #define cfgBIFPLR6_0_SUB_BUS_NUMBER_LATENCY 0x0018 338251199920SFeifei Xu #define cfgBIFPLR6_0_IO_BASE_LIMIT 0x001c 338351199920SFeifei Xu #define cfgBIFPLR6_0_SECONDARY_STATUS 0x001e 338451199920SFeifei Xu #define cfgBIFPLR6_0_MEM_BASE_LIMIT 0x0020 338551199920SFeifei Xu #define cfgBIFPLR6_0_PREF_BASE_LIMIT 0x0024 338651199920SFeifei Xu #define cfgBIFPLR6_0_PREF_BASE_UPPER 0x0028 338751199920SFeifei Xu #define cfgBIFPLR6_0_PREF_LIMIT_UPPER 0x002c 338851199920SFeifei Xu #define cfgBIFPLR6_0_IO_BASE_LIMIT_HI 0x0030 338951199920SFeifei Xu #define cfgBIFPLR6_0_CAP_PTR 0x0034 339051199920SFeifei Xu #define cfgBIFPLR6_0_INTERRUPT_LINE 0x003c 339151199920SFeifei Xu #define cfgBIFPLR6_0_INTERRUPT_PIN 0x003d 339251199920SFeifei Xu #define cfgBIFPLR6_0_IRQ_BRIDGE_CNTL 0x003e 339351199920SFeifei Xu #define cfgBIFPLR6_0_EXT_BRIDGE_CNTL 0x0040 339451199920SFeifei Xu #define cfgBIFPLR6_0_PMI_CAP_LIST 0x0050 339551199920SFeifei Xu #define cfgBIFPLR6_0_PMI_CAP 0x0052 339651199920SFeifei Xu #define cfgBIFPLR6_0_PMI_STATUS_CNTL 0x0054 339751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_CAP_LIST 0x0058 339851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_CAP 0x005a 339951199920SFeifei Xu #define cfgBIFPLR6_0_DEVICE_CAP 0x005c 340051199920SFeifei Xu #define cfgBIFPLR6_0_DEVICE_CNTL 0x0060 340151199920SFeifei Xu #define cfgBIFPLR6_0_DEVICE_STATUS 0x0062 340251199920SFeifei Xu #define cfgBIFPLR6_0_LINK_CAP 0x0064 340351199920SFeifei Xu #define cfgBIFPLR6_0_LINK_CNTL 0x0068 340451199920SFeifei Xu #define cfgBIFPLR6_0_LINK_STATUS 0x006a 340551199920SFeifei Xu #define cfgBIFPLR6_0_SLOT_CAP 0x006c 340651199920SFeifei Xu #define cfgBIFPLR6_0_SLOT_CNTL 0x0070 340751199920SFeifei Xu #define cfgBIFPLR6_0_SLOT_STATUS 0x0072 340851199920SFeifei Xu #define cfgBIFPLR6_0_ROOT_CNTL 0x0074 340951199920SFeifei Xu #define cfgBIFPLR6_0_ROOT_CAP 0x0076 341051199920SFeifei Xu #define cfgBIFPLR6_0_ROOT_STATUS 0x0078 341151199920SFeifei Xu #define cfgBIFPLR6_0_DEVICE_CAP2 0x007c 341251199920SFeifei Xu #define cfgBIFPLR6_0_DEVICE_CNTL2 0x0080 341351199920SFeifei Xu #define cfgBIFPLR6_0_DEVICE_STATUS2 0x0082 341451199920SFeifei Xu #define cfgBIFPLR6_0_LINK_CAP2 0x0084 341551199920SFeifei Xu #define cfgBIFPLR6_0_LINK_CNTL2 0x0088 341651199920SFeifei Xu #define cfgBIFPLR6_0_LINK_STATUS2 0x008a 341751199920SFeifei Xu #define cfgBIFPLR6_0_SLOT_CAP2 0x008c 341851199920SFeifei Xu #define cfgBIFPLR6_0_SLOT_CNTL2 0x0090 341951199920SFeifei Xu #define cfgBIFPLR6_0_SLOT_STATUS2 0x0092 342051199920SFeifei Xu #define cfgBIFPLR6_0_MSI_CAP_LIST 0x00a0 342151199920SFeifei Xu #define cfgBIFPLR6_0_MSI_MSG_CNTL 0x00a2 342251199920SFeifei Xu #define cfgBIFPLR6_0_MSI_MSG_ADDR_LO 0x00a4 342351199920SFeifei Xu #define cfgBIFPLR6_0_MSI_MSG_ADDR_HI 0x00a8 342451199920SFeifei Xu #define cfgBIFPLR6_0_MSI_MSG_DATA 0x00a8 342551199920SFeifei Xu #define cfgBIFPLR6_0_MSI_MSG_DATA_64 0x00ac 342651199920SFeifei Xu #define cfgBIFPLR6_0_SSID_CAP_LIST 0x00c0 342751199920SFeifei Xu #define cfgBIFPLR6_0_SSID_CAP 0x00c4 342851199920SFeifei Xu #define cfgBIFPLR6_0_MSI_MAP_CAP_LIST 0x00c8 342951199920SFeifei Xu #define cfgBIFPLR6_0_MSI_MAP_CAP 0x00ca 343051199920SFeifei Xu #define cfgBIFPLR6_0_MSI_MAP_ADDR_LO 0x00cc 343151199920SFeifei Xu #define cfgBIFPLR6_0_MSI_MAP_ADDR_HI 0x00d0 343251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 343351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 343451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC1 0x0108 343551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC2 0x010c 343651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VC_ENH_CAP_LIST 0x0110 343751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG1 0x0114 343851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG2 0x0118 343951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_PORT_VC_CNTL 0x011c 344051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_PORT_VC_STATUS 0x011e 344151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CAP 0x0120 344251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CNTL 0x0124 344351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_STATUS 0x012a 344451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CAP 0x012c 344551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CNTL 0x0130 344651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_STATUS 0x0136 344751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 344851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 344951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 345051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 345151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_UNCORR_ERR_STATUS 0x0154 345251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_UNCORR_ERR_MASK 0x0158 345351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c 345451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_CORR_ERR_STATUS 0x0160 345551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_CORR_ERR_MASK 0x0164 345651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 345751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_HDR_LOG0 0x016c 345851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_HDR_LOG1 0x0170 345951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_HDR_LOG2 0x0174 346051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_HDR_LOG3 0x0178 346151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ROOT_ERR_CMD 0x017c 346251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ROOT_ERR_STATUS 0x0180 346351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ERR_SRC_ID 0x0184 346451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG0 0x0188 346551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG1 0x018c 346651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG2 0x0190 346751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG3 0x0194 346851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 346951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LINK_CNTL3 0x0274 347051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_ERROR_STATUS 0x0278 347151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 347251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 347351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 347451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 347551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 347651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 347751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 347851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 347951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 348051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 348151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 348251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 348351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 348451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 348551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 348651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 348751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 348851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ACS_CAP 0x02a4 348951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ACS_CNTL 0x02a6 349051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_ENH_CAP_LIST 0x02f0 349151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_CAP 0x02f4 349251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_CNTL 0x02f6 349351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_ADDR0 0x02f8 349451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_ADDR1 0x02fc 349551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_RCV0 0x0300 349651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_RCV1 0x0304 349751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL0 0x0308 349851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL1 0x030c 349951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 350051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 350151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR0 0x0318 350251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR1 0x031c 350351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 350451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP 0x0374 350551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL 0x0378 350651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL2 0x037c 350751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_DPC_ENH_CAP_LIST 0x0380 350851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_DPC_CAP_LIST 0x0384 350951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_DPC_CNTL 0x0386 351051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_DPC_STATUS 0x0388 351151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a 351251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_STATUS 0x038c 351351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_MASK 0x0390 351451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_SEVERITY 0x0394 351551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_SYSERROR 0x0398 351651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_EXCEPTION 0x039c 351751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 351851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 351951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 352051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG3 0x03ac 352151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 352251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 352351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 352451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc 352551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 352651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_CAP_LIST 0x03c4 352751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_HEADER_1 0x03c8 352851199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_HEADER_2 0x03cc 352951199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_STATUS 0x03ce 353051199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_CTRL 0x03d0 353151199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_CAP_1 0x03d4 353251199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_CAP_2 0x03d8 353351199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_CAP_3 0x03dc 353451199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_CAP_4 0x03e0 353551199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_CAP_5 0x03e4 353651199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_CAP_6 0x03e8 353751199920SFeifei Xu #define cfgBIFPLR6_0_PCIE_ESM_CAP_7 0x03ec 353851199920SFeifei Xu 353951199920SFeifei Xu 354051199920SFeifei Xu // addressBlock: nbio_dbgu0_dbgudec 354151199920SFeifei Xu // base address: 0x700 354251199920SFeifei Xu #define mmport_a_addr 0x01ac 354351199920SFeifei Xu #define mmport_a_addr_BASE_IDX 1 354451199920SFeifei Xu #define mmport_a_data_lo 0x01ad 354551199920SFeifei Xu #define mmport_a_data_lo_BASE_IDX 1 354651199920SFeifei Xu #define mmport_a_data_hi 0x01ae 354751199920SFeifei Xu #define mmport_a_data_hi_BASE_IDX 1 354851199920SFeifei Xu #define mmport_b_addr 0x01af 354951199920SFeifei Xu #define mmport_b_addr_BASE_IDX 1 355051199920SFeifei Xu #define mmport_b_data_lo 0x01b0 355151199920SFeifei Xu #define mmport_b_data_lo_BASE_IDX 1 355251199920SFeifei Xu #define mmport_b_data_hi 0x01b1 355351199920SFeifei Xu #define mmport_b_data_hi_BASE_IDX 1 355451199920SFeifei Xu #define mmport_c_addr 0x01b2 355551199920SFeifei Xu #define mmport_c_addr_BASE_IDX 1 355651199920SFeifei Xu #define mmport_c_data_lo 0x01b3 355751199920SFeifei Xu #define mmport_c_data_lo_BASE_IDX 1 355851199920SFeifei Xu #define mmport_c_data_hi 0x01b4 355951199920SFeifei Xu #define mmport_c_data_hi_BASE_IDX 1 356051199920SFeifei Xu #define mmport_d_addr 0x01b5 356151199920SFeifei Xu #define mmport_d_addr_BASE_IDX 1 356251199920SFeifei Xu #define mmport_d_data_lo 0x01b6 356351199920SFeifei Xu #define mmport_d_data_lo_BASE_IDX 1 356451199920SFeifei Xu #define mmport_d_data_hi 0x01b7 356551199920SFeifei Xu #define mmport_d_data_hi_BASE_IDX 1 356651199920SFeifei Xu 356751199920SFeifei Xu 356851199920SFeifei Xu // addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg 356951199920SFeifei Xu // base address: 0x0 357051199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_BASE_0 0x0000 357151199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_BASE_0_BASE_IDX 0 357251199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_BASE_1 0x0001 357351199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_BASE_1_BASE_IDX 0 357451199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BASE_0 0x0002 357551199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BASE_0_BASE_IDX 0 357651199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BASE_1 0x0003 357751199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BASE_1_BASE_IDX 0 357851199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BASE_0 0x0004 357951199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BASE_0_BASE_IDX 0 358051199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BASE_1 0x0005 358151199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BASE_1_BASE_IDX 0 358251199920SFeifei Xu #define mmIOMMU_MMIO_CNTRL_0 0x0006 358351199920SFeifei Xu #define mmIOMMU_MMIO_CNTRL_0_BASE_IDX 0 358451199920SFeifei Xu #define mmIOMMU_MMIO_CNTRL_1 0x0007 358551199920SFeifei Xu #define mmIOMMU_MMIO_CNTRL_1_BASE_IDX 0 358651199920SFeifei Xu #define mmIOMMU_MMIO_EXCL_BASE_0 0x0008 358751199920SFeifei Xu #define mmIOMMU_MMIO_EXCL_BASE_0_BASE_IDX 0 358851199920SFeifei Xu #define mmIOMMU_MMIO_EXCL_BASE_1 0x0009 358951199920SFeifei Xu #define mmIOMMU_MMIO_EXCL_BASE_1_BASE_IDX 0 359051199920SFeifei Xu #define mmIOMMU_MMIO_EXCL_LIM_0 0x000a 359151199920SFeifei Xu #define mmIOMMU_MMIO_EXCL_LIM_0_BASE_IDX 0 359251199920SFeifei Xu #define mmIOMMU_MMIO_EXCL_LIM_1 0x000b 359351199920SFeifei Xu #define mmIOMMU_MMIO_EXCL_LIM_1_BASE_IDX 0 359451199920SFeifei Xu #define mmIOMMU_MMIO_EFR_0 0x000c 359551199920SFeifei Xu #define mmIOMMU_MMIO_EFR_0_BASE_IDX 0 359651199920SFeifei Xu #define mmIOMMU_MMIO_EFR_1 0x000d 359751199920SFeifei Xu #define mmIOMMU_MMIO_EFR_1_BASE_IDX 0 359851199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BASE_0 0x000e 359951199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BASE_0_BASE_IDX 0 360051199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BASE_1 0x000f 360151199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BASE_1_BASE_IDX 0 360251199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_UPPER_0 0x0010 360351199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_UPPER_0_BASE_IDX 0 360451199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_UPPER_1 0x0011 360551199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_UPPER_1_BASE_IDX 0 360651199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_LOWER_0 0x0012 360751199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_LOWER_0_BASE_IDX 0 360851199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_LOWER_1 0x0013 360951199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_LOWER_1_BASE_IDX 0 361051199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_STATUS_0 0x0000 361151199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_STATUS_0_BASE_IDX 1 361251199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_STATUS_1 0x0001 361351199920SFeifei Xu #define mmIOMMU_MMIO_HW_ERR_STATUS_1_BASE_IDX 1 361451199920SFeifei Xu #define mmSMI_FILTER_REGISTER_0_0 0x0004 361551199920SFeifei Xu #define mmSMI_FILTER_REGISTER_0_0_BASE_IDX 1 361651199920SFeifei Xu #define mmSMI_FILTER_REGISTER_0_1 0x0005 361751199920SFeifei Xu #define mmSMI_FILTER_REGISTER_0_1_BASE_IDX 1 361851199920SFeifei Xu #define mmSMI_FILTER_REGISTER_1_0 0x0006 361951199920SFeifei Xu #define mmSMI_FILTER_REGISTER_1_0_BASE_IDX 1 362051199920SFeifei Xu #define mmSMI_FILTER_REGISTER_1_1 0x0007 362151199920SFeifei Xu #define mmSMI_FILTER_REGISTER_1_1_BASE_IDX 1 362251199920SFeifei Xu #define mmSMI_FILTER_REGISTER_2_0 0x0008 362351199920SFeifei Xu #define mmSMI_FILTER_REGISTER_2_0_BASE_IDX 1 362451199920SFeifei Xu #define mmSMI_FILTER_REGISTER_2_1 0x0009 362551199920SFeifei Xu #define mmSMI_FILTER_REGISTER_2_1_BASE_IDX 1 362651199920SFeifei Xu #define mmSMI_FILTER_REGISTER_3_0 0x000a 362751199920SFeifei Xu #define mmSMI_FILTER_REGISTER_3_0_BASE_IDX 1 362851199920SFeifei Xu #define mmSMI_FILTER_REGISTER_3_1 0x000b 362951199920SFeifei Xu #define mmSMI_FILTER_REGISTER_3_1_BASE_IDX 1 363051199920SFeifei Xu #define mmIOMMU_MMIO_GA_LOG_BASE_0 0x0024 363151199920SFeifei Xu #define mmIOMMU_MMIO_GA_LOG_BASE_0_BASE_IDX 1 363251199920SFeifei Xu #define mmIOMMU_MMIO_GA_LOG_BASE_1 0x0025 363351199920SFeifei Xu #define mmIOMMU_MMIO_GA_LOG_BASE_1_BASE_IDX 1 363451199920SFeifei Xu #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0 0x0026 363551199920SFeifei Xu #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0_BASE_IDX 1 363651199920SFeifei Xu #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1 0x0027 363751199920SFeifei Xu #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1_BASE_IDX 1 363851199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BASE_0 0x0028 363951199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BASE_0_BASE_IDX 1 364051199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BASE_1 0x0029 364151199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BASE_1_BASE_IDX 1 364251199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BASE_0 0x002a 364351199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BASE_0_BASE_IDX 1 364451199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BASE_1 0x002b 364551199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BASE_1_BASE_IDX 1 364651199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_1_BASE_0 0x002c 364751199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_1_BASE_0_BASE_IDX 1 364851199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_1_BASE_1 0x002d 364951199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_1_BASE_1_BASE_IDX 1 365051199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_2_BASE_0 0x002e 365151199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_2_BASE_0_BASE_IDX 1 365251199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_2_BASE_1 0x002f 365351199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_2_BASE_1_BASE_IDX 1 365451199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_3_BASE_0 0x0030 365551199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_3_BASE_0_BASE_IDX 1 365651199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_3_BASE_1 0x0031 365751199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_3_BASE_1_BASE_IDX 1 365851199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_4_BASE_0 0x0032 365951199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_4_BASE_0_BASE_IDX 1 366051199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_4_BASE_1 0x0033 366151199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_4_BASE_1_BASE_IDX 1 366251199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_5_BASE_0 0x0034 366351199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_5_BASE_0_BASE_IDX 1 366451199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_5_BASE_1 0x0035 366551199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_5_BASE_1_BASE_IDX 1 366651199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_6_BASE_0 0x0036 366751199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_6_BASE_0_BASE_IDX 1 366851199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_6_BASE_1 0x0037 366951199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_6_BASE_1_BASE_IDX 1 367051199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_7_BASE_0 0x0038 367151199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_7_BASE_0_BASE_IDX 1 367251199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_7_BASE_1 0x0039 367351199920SFeifei Xu #define mmIOMMU_MMIO_DEVTBL_7_BASE_1_BASE_IDX 1 367451199920SFeifei Xu #define mmIOMMU_MMIO_DSFX 0x003a 367551199920SFeifei Xu #define mmIOMMU_MMIO_DSFX_BASE_IDX 1 367651199920SFeifei Xu #define mmIOMMU_MMIO_DSCX 0x003c 367751199920SFeifei Xu #define mmIOMMU_MMIO_DSCX_BASE_IDX 1 367851199920SFeifei Xu #define mmIOMMU_MMIO_DSSX 0x003e 367951199920SFeifei Xu #define mmIOMMU_MMIO_DSSX_BASE_IDX 1 368051199920SFeifei Xu #define mmIOMMU_MMIO_CAP_MISC 0x0040 368151199920SFeifei Xu #define mmIOMMU_MMIO_CAP_MISC_BASE_IDX 1 368251199920SFeifei Xu #define mmIOMMU_MMIO_CAP_MISC_1 0x0041 368351199920SFeifei Xu #define mmIOMMU_MMIO_CAP_MISC_1_BASE_IDX 1 368451199920SFeifei Xu #define mmIOMMU_MMIO_MSI_CAP 0x0042 368551199920SFeifei Xu #define mmIOMMU_MMIO_MSI_CAP_BASE_IDX 1 368651199920SFeifei Xu #define mmIOMMU_MMIO_MSI_ADDR_LO 0x0043 368751199920SFeifei Xu #define mmIOMMU_MMIO_MSI_ADDR_LO_BASE_IDX 1 368851199920SFeifei Xu #define mmIOMMU_MMIO_MSI_ADDR_HI 0x0044 368951199920SFeifei Xu #define mmIOMMU_MMIO_MSI_ADDR_HI_BASE_IDX 1 369051199920SFeifei Xu #define mmIOMMU_MMIO_MSI_DATA 0x0045 369151199920SFeifei Xu #define mmIOMMU_MMIO_MSI_DATA_BASE_IDX 1 369251199920SFeifei Xu #define mmIOMMU_MMIO_MSI_MAPPING_CAP 0x0046 369351199920SFeifei Xu #define mmIOMMU_MMIO_MSI_MAPPING_CAP_BASE_IDX 1 369451199920SFeifei Xu #define mmIOMMU_MMIO_CONTROL_W 0x0047 369551199920SFeifei Xu #define mmIOMMU_MMIO_CONTROL_W_BASE_IDX 1 369651199920SFeifei Xu #define mmIOMMU_MARC_BASE_LO_0 0x006c 369751199920SFeifei Xu #define mmIOMMU_MARC_BASE_LO_0_BASE_IDX 1 369851199920SFeifei Xu #define mmIOMMU_MARC_BASE_HI_0 0x006d 369951199920SFeifei Xu #define mmIOMMU_MARC_BASE_HI_0_BASE_IDX 1 370051199920SFeifei Xu #define mmIOMMU_MARC_RELOC_LO_0 0x006e 370151199920SFeifei Xu #define mmIOMMU_MARC_RELOC_LO_0_BASE_IDX 1 370251199920SFeifei Xu #define mmIOMMU_MARC_RELOC_HI_0 0x006f 370351199920SFeifei Xu #define mmIOMMU_MARC_RELOC_HI_0_BASE_IDX 1 370451199920SFeifei Xu #define mmIOMMU_MARC_LEN_LO_0 0x0070 370551199920SFeifei Xu #define mmIOMMU_MARC_LEN_LO_0_BASE_IDX 1 370651199920SFeifei Xu #define mmIOMMU_MARC_LEN_HI_0 0x0071 370751199920SFeifei Xu #define mmIOMMU_MARC_LEN_HI_0_BASE_IDX 1 370851199920SFeifei Xu #define mmIOMMU_MARC_BASE_LO_1 0x0072 370951199920SFeifei Xu #define mmIOMMU_MARC_BASE_LO_1_BASE_IDX 1 371051199920SFeifei Xu #define mmIOMMU_MARC_BASE_HI_1 0x0073 371151199920SFeifei Xu #define mmIOMMU_MARC_BASE_HI_1_BASE_IDX 1 371251199920SFeifei Xu #define mmIOMMU_MARC_RELOC_LO_1 0x0074 371351199920SFeifei Xu #define mmIOMMU_MARC_RELOC_LO_1_BASE_IDX 1 371451199920SFeifei Xu #define mmIOMMU_MARC_RELOC_HI_1 0x0075 371551199920SFeifei Xu #define mmIOMMU_MARC_RELOC_HI_1_BASE_IDX 1 371651199920SFeifei Xu #define mmIOMMU_MARC_LEN_LO_1 0x0076 371751199920SFeifei Xu #define mmIOMMU_MARC_LEN_LO_1_BASE_IDX 1 371851199920SFeifei Xu #define mmIOMMU_MARC_LEN_HI_1 0x0077 371951199920SFeifei Xu #define mmIOMMU_MARC_LEN_HI_1_BASE_IDX 1 372051199920SFeifei Xu #define mmIOMMU_MARC_BASE_LO_2 0x0078 372151199920SFeifei Xu #define mmIOMMU_MARC_BASE_LO_2_BASE_IDX 1 372251199920SFeifei Xu #define mmIOMMU_MARC_BASE_HI_2 0x0079 372351199920SFeifei Xu #define mmIOMMU_MARC_BASE_HI_2_BASE_IDX 1 372451199920SFeifei Xu #define mmIOMMU_MARC_RELOC_LO_2 0x007a 372551199920SFeifei Xu #define mmIOMMU_MARC_RELOC_LO_2_BASE_IDX 1 372651199920SFeifei Xu #define mmIOMMU_MARC_RELOC_HI_2 0x007b 372751199920SFeifei Xu #define mmIOMMU_MARC_RELOC_HI_2_BASE_IDX 1 372851199920SFeifei Xu #define mmIOMMU_MARC_LEN_LO_2 0x007c 372951199920SFeifei Xu #define mmIOMMU_MARC_LEN_LO_2_BASE_IDX 1 373051199920SFeifei Xu #define mmIOMMU_MARC_LEN_HI_2 0x007d 373151199920SFeifei Xu #define mmIOMMU_MARC_LEN_HI_2_BASE_IDX 1 373251199920SFeifei Xu #define mmIOMMU_MARC_BASE_LO_3 0x007e 373351199920SFeifei Xu #define mmIOMMU_MARC_BASE_LO_3_BASE_IDX 1 373451199920SFeifei Xu #define mmIOMMU_MARC_BASE_HI_3 0x007f 373551199920SFeifei Xu #define mmIOMMU_MARC_BASE_HI_3_BASE_IDX 1 373651199920SFeifei Xu #define mmIOMMU_MARC_RELOC_LO_3 0x0080 373751199920SFeifei Xu #define mmIOMMU_MARC_RELOC_LO_3_BASE_IDX 1 373851199920SFeifei Xu #define mmIOMMU_MARC_RELOC_HI_3 0x0081 373951199920SFeifei Xu #define mmIOMMU_MARC_RELOC_HI_3_BASE_IDX 1 374051199920SFeifei Xu #define mmIOMMU_MARC_LEN_LO_3 0x0082 374151199920SFeifei Xu #define mmIOMMU_MARC_LEN_LO_3_BASE_IDX 1 374251199920SFeifei Xu #define mmIOMMU_MARC_LEN_HI_3 0x0083 374351199920SFeifei Xu #define mmIOMMU_MARC_LEN_HI_3_BASE_IDX 1 374451199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BUF_HDPTR_0 0x07ec 374551199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BUF_HDPTR_0_BASE_IDX 1 374651199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BUF_HDPTR_1 0x07ed 374751199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BUF_HDPTR_1_BASE_IDX 1 374851199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_0 0x07ee 374951199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_0_BASE_IDX 1 375051199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_1 0x07ef 375151199920SFeifei Xu #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_1_BASE_IDX 1 375251199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_0 0x07f0 375351199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_0_BASE_IDX 1 375451199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_1 0x07f1 375551199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_1_BASE_IDX 1 375651199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0 0x07f2 375751199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0_BASE_IDX 1 375851199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1 0x07f3 375951199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1_BASE_IDX 1 376051199920SFeifei Xu #define mmIOMMU_MMIO_STATUS_0 0x07f4 376151199920SFeifei Xu #define mmIOMMU_MMIO_STATUS_0_BASE_IDX 1 376251199920SFeifei Xu #define mmIOMMU_MMIO_STATUS_1 0x07f5 376351199920SFeifei Xu #define mmIOMMU_MMIO_STATUS_1_BASE_IDX 1 376451199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BUF_HDPTR_0 0x07f8 376551199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BUF_HDPTR_0_BASE_IDX 1 376651199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BUF_HDPTR_1 0x07f9 376751199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BUF_HDPTR_1_BASE_IDX 1 376851199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_0 0x07fa 376951199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_0_BASE_IDX 1 377051199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_1 0x07fb 377151199920SFeifei Xu #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_1_BASE_IDX 1 377251199920SFeifei Xu #define mmIOMMU_MMIO_GA_BUF_HDPTR_0 0x07fc 377351199920SFeifei Xu #define mmIOMMU_MMIO_GA_BUF_HDPTR_0_BASE_IDX 1 377451199920SFeifei Xu #define mmIOMMU_MMIO_GA_BUF_HDPTR_1 0x07fd 377551199920SFeifei Xu #define mmIOMMU_MMIO_GA_BUF_HDPTR_1_BASE_IDX 1 377651199920SFeifei Xu #define mmIOMMU_MMIO_GA_BUF_TAILPTR_0 0x07fe 377751199920SFeifei Xu #define mmIOMMU_MMIO_GA_BUF_TAILPTR_0_BASE_IDX 1 377851199920SFeifei Xu #define mmIOMMU_MMIO_GA_BUF_TAILPTR_1 0x07ff 377951199920SFeifei Xu #define mmIOMMU_MMIO_GA_BUF_TAILPTR_1_BASE_IDX 1 378051199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0 0x0800 378151199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0_BASE_IDX 1 378251199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1 0x0801 378351199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1_BASE_IDX 1 378451199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0 0x0802 378551199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0_BASE_IDX 1 378651199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1 0x0803 378751199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1_BASE_IDX 1 378851199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0 0x0808 378951199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0_BASE_IDX 1 379051199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1 0x0809 379151199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1_BASE_IDX 1 379251199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0 0x080a 379351199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0_BASE_IDX 1 379451199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1 0x080b 379551199920SFeifei Xu #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1_BASE_IDX 1 379651199920SFeifei Xu #define mmIOMMU_MMIO_PPR_AUTORESP_0 0x080c 379751199920SFeifei Xu #define mmIOMMU_MMIO_PPR_AUTORESP_0_BASE_IDX 1 379851199920SFeifei Xu #define mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0 0x080e 379951199920SFeifei Xu #define mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0_BASE_IDX 1 380051199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0 0x0810 380151199920SFeifei Xu #define mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0_BASE_IDX 1 380251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_CONFIG_0 0x02e0 380351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_CONFIG_0_BASE_IDX 2 380451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_CONFIG_1 0x02e1 380551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_CONFIG_1_BASE_IDX 2 380651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 0x02e2 380751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_BASE_IDX 2 380851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 0x02e3 380951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_BASE_IDX 2 381051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 0x02e4 381151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_BASE_IDX 2 381251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 0x02e5 381351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_BASE_IDX 2 381451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 0x02e6 381551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_BASE_IDX 2 381651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 0x02e7 381751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_BASE_IDX 2 381851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0 0xf2e0 381951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0_BASE_IDX 2 382051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1 0xf2e1 382151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1_BASE_IDX 2 382251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 0xf2e2 382351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_BASE_IDX 2 382451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1 0xf2e3 382551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1_BASE_IDX 2 382651199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 0xf2e4 382751199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_BASE_IDX 2 382851199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 0xf2e5 382951199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_BASE_IDX 2 383051199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 0xf2e6 383151199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_BASE_IDX 2 383251199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 0xf2e7 383351199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_BASE_IDX 2 383451199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 0xf2e8 383551199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_BASE_IDX 2 383651199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 0xf2e9 383751199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_BASE_IDX 2 383851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0 0xf2ea 383951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0_BASE_IDX 2 384051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1 0xf2eb 384151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1_BASE_IDX 2 384251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0 0xf320 384351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0_BASE_IDX 2 384451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1 0xf321 384551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1_BASE_IDX 2 384651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 0xf322 384751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_BASE_IDX 2 384851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1 0xf323 384951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1_BASE_IDX 2 385051199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 0xf324 385151199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_BASE_IDX 2 385251199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 0xf325 385351199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_BASE_IDX 2 385451199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 0xf326 385551199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_BASE_IDX 2 385651199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 0xf327 385751199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_BASE_IDX 2 385851199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 0xf328 385951199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_BASE_IDX 2 386051199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 0xf329 386151199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_BASE_IDX 2 386251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0 0xf32a 386351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0_BASE_IDX 2 386451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1 0xf32b 386551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1_BASE_IDX 2 386651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0 0xf360 386751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0_BASE_IDX 2 386851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1 0xf361 386951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1_BASE_IDX 2 387051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 0xf362 387151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_BASE_IDX 2 387251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1 0xf363 387351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1_BASE_IDX 2 387451199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 0xf364 387551199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_BASE_IDX 2 387651199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 0xf365 387751199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_BASE_IDX 2 387851199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 0xf366 387951199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_BASE_IDX 2 388051199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 0xf367 388151199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_BASE_IDX 2 388251199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 0xf368 388351199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_BASE_IDX 2 388451199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 0xf369 388551199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_BASE_IDX 2 388651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0 0xf36a 388751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0_BASE_IDX 2 388851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1 0xf36b 388951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1_BASE_IDX 2 389051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0 0xf3a0 389151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0_BASE_IDX 2 389251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1 0xf3a1 389351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1_BASE_IDX 2 389451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 0xf3a2 389551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_BASE_IDX 2 389651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1 0xf3a3 389751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1_BASE_IDX 2 389851199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 0xf3a4 389951199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_BASE_IDX 2 390051199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 0xf3a5 390151199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_BASE_IDX 2 390251199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 0xf3a6 390351199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_BASE_IDX 2 390451199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 0xf3a7 390551199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_BASE_IDX 2 390651199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 0xf3a8 390751199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_BASE_IDX 2 390851199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 0xf3a9 390951199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_BASE_IDX 2 391051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0 0xf3aa 391151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0_BASE_IDX 2 391251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1 0xf3ab 391351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1_BASE_IDX 2 391451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0 0x0000 391551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0_BASE_IDX 3 391651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1 0x0001 391751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1_BASE_IDX 3 391851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 0x0002 391951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_BASE_IDX 3 392051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1 0x0003 392151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1_BASE_IDX 3 392251199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 0x0004 392351199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_BASE_IDX 3 392451199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 0x0005 392551199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_BASE_IDX 3 392651199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 0x0006 392751199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_BASE_IDX 3 392851199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 0x0007 392951199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_BASE_IDX 3 393051199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 0x0008 393151199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_BASE_IDX 3 393251199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 0x0009 393351199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_BASE_IDX 3 393451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0 0x000a 393551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0_BASE_IDX 3 393651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1 0x000b 393751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1_BASE_IDX 3 393851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0 0x0040 393951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0_BASE_IDX 3 394051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1 0x0041 394151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1_BASE_IDX 3 394251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 0x0042 394351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_BASE_IDX 3 394451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1 0x0043 394551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1_BASE_IDX 3 394651199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 0x0044 394751199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_BASE_IDX 3 394851199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 0x0045 394951199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_BASE_IDX 3 395051199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 0x0046 395151199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_BASE_IDX 3 395251199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 0x0047 395351199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_BASE_IDX 3 395451199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 0x0048 395551199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_BASE_IDX 3 395651199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 0x0049 395751199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_BASE_IDX 3 395851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0 0x004a 395951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0_BASE_IDX 3 396051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1 0x004b 396151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1_BASE_IDX 3 396251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0 0x0080 396351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0_BASE_IDX 3 396451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1 0x0081 396551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1_BASE_IDX 3 396651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 0x0082 396751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_BASE_IDX 3 396851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1 0x0083 396951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1_BASE_IDX 3 397051199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 0x0084 397151199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_BASE_IDX 3 397251199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 0x0085 397351199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_BASE_IDX 3 397451199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 0x0086 397551199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_BASE_IDX 3 397651199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 0x0087 397751199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_BASE_IDX 3 397851199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 0x0088 397951199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_BASE_IDX 3 398051199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 0x0089 398151199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_BASE_IDX 3 398251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0 0x008a 398351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0_BASE_IDX 3 398451199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1 0x008b 398551199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1_BASE_IDX 3 398651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0 0x00c0 398751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0_BASE_IDX 3 398851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1 0x00c1 398951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1_BASE_IDX 3 399051199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 0x00c2 399151199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_BASE_IDX 3 399251199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1 0x00c3 399351199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1_BASE_IDX 3 399451199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 0x00c4 399551199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_BASE_IDX 3 399651199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 0x00c5 399751199920SFeifei Xu #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_BASE_IDX 3 399851199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 0x00c6 399951199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_BASE_IDX 3 400051199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 0x00c7 400151199920SFeifei Xu #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_BASE_IDX 3 400251199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 0x00c8 400351199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_BASE_IDX 3 400451199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 0x00c9 400551199920SFeifei Xu #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_BASE_IDX 3 400651199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0 0x00ca 400751199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0_BASE_IDX 3 400851199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1 0x00cb 400951199920SFeifei Xu #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1_BASE_IDX 3 401051199920SFeifei Xu 401151199920SFeifei Xu 401251199920SFeifei Xu // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 401351199920SFeifei Xu // base address: 0x0 401451199920SFeifei Xu #define mmMM_INDEX 0x0000 401551199920SFeifei Xu #define mmMM_INDEX_BASE_IDX 0 401651199920SFeifei Xu #define mmMM_DATA 0x0001 401751199920SFeifei Xu #define mmMM_DATA_BASE_IDX 0 401851199920SFeifei Xu #define mmMM_INDEX_HI 0x0006 401951199920SFeifei Xu #define mmMM_INDEX_HI_BASE_IDX 0 402051199920SFeifei Xu 402151199920SFeifei Xu 402251199920SFeifei Xu // addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC 402351199920SFeifei Xu // base address: 0x0 402451199920SFeifei Xu #define mmSYSHUB_INDEX_OVLP 0x0008 402551199920SFeifei Xu #define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 402651199920SFeifei Xu #define mmSYSHUB_DATA_OVLP 0x0009 402751199920SFeifei Xu #define mmSYSHUB_DATA_OVLP_BASE_IDX 0 402851199920SFeifei Xu #define mmPCIE_INDEX 0x000c 402951199920SFeifei Xu #define mmPCIE_INDEX_BASE_IDX 0 403051199920SFeifei Xu #define mmPCIE_DATA 0x000d 403151199920SFeifei Xu #define mmPCIE_DATA_BASE_IDX 0 403251199920SFeifei Xu #define mmPCIE_INDEX2 0x000e 403351199920SFeifei Xu #define mmPCIE_INDEX2_BASE_IDX 0 403451199920SFeifei Xu #define mmPCIE_DATA2 0x000f 403551199920SFeifei Xu #define mmPCIE_DATA2_BASE_IDX 0 403651199920SFeifei Xu #define mmSBIOS_SCRATCH_0 0x0034 403751199920SFeifei Xu #define mmSBIOS_SCRATCH_0_BASE_IDX 1 403851199920SFeifei Xu #define mmSBIOS_SCRATCH_1 0x0035 403951199920SFeifei Xu #define mmSBIOS_SCRATCH_1_BASE_IDX 1 404051199920SFeifei Xu #define mmSBIOS_SCRATCH_2 0x0036 404151199920SFeifei Xu #define mmSBIOS_SCRATCH_2_BASE_IDX 1 404251199920SFeifei Xu #define mmSBIOS_SCRATCH_3 0x0037 404351199920SFeifei Xu #define mmSBIOS_SCRATCH_3_BASE_IDX 1 404451199920SFeifei Xu #define mmBIOS_SCRATCH_0 0x0038 404551199920SFeifei Xu #define mmBIOS_SCRATCH_0_BASE_IDX 1 404651199920SFeifei Xu #define mmBIOS_SCRATCH_1 0x0039 404751199920SFeifei Xu #define mmBIOS_SCRATCH_1_BASE_IDX 1 404851199920SFeifei Xu #define mmBIOS_SCRATCH_2 0x003a 404951199920SFeifei Xu #define mmBIOS_SCRATCH_2_BASE_IDX 1 405051199920SFeifei Xu #define mmBIOS_SCRATCH_3 0x003b 405151199920SFeifei Xu #define mmBIOS_SCRATCH_3_BASE_IDX 1 405251199920SFeifei Xu #define mmBIOS_SCRATCH_4 0x003c 405351199920SFeifei Xu #define mmBIOS_SCRATCH_4_BASE_IDX 1 405451199920SFeifei Xu #define mmBIOS_SCRATCH_5 0x003d 405551199920SFeifei Xu #define mmBIOS_SCRATCH_5_BASE_IDX 1 405651199920SFeifei Xu #define mmBIOS_SCRATCH_6 0x003e 405751199920SFeifei Xu #define mmBIOS_SCRATCH_6_BASE_IDX 1 405851199920SFeifei Xu #define mmBIOS_SCRATCH_7 0x003f 405951199920SFeifei Xu #define mmBIOS_SCRATCH_7_BASE_IDX 1 406051199920SFeifei Xu #define mmBIOS_SCRATCH_8 0x0040 406151199920SFeifei Xu #define mmBIOS_SCRATCH_8_BASE_IDX 1 406251199920SFeifei Xu #define mmBIOS_SCRATCH_9 0x0041 406351199920SFeifei Xu #define mmBIOS_SCRATCH_9_BASE_IDX 1 406451199920SFeifei Xu #define mmBIOS_SCRATCH_10 0x0042 406551199920SFeifei Xu #define mmBIOS_SCRATCH_10_BASE_IDX 1 406651199920SFeifei Xu #define mmBIOS_SCRATCH_11 0x0043 406751199920SFeifei Xu #define mmBIOS_SCRATCH_11_BASE_IDX 1 406851199920SFeifei Xu #define mmBIOS_SCRATCH_12 0x0044 406951199920SFeifei Xu #define mmBIOS_SCRATCH_12_BASE_IDX 1 407051199920SFeifei Xu #define mmBIOS_SCRATCH_13 0x0045 407151199920SFeifei Xu #define mmBIOS_SCRATCH_13_BASE_IDX 1 407251199920SFeifei Xu #define mmBIOS_SCRATCH_14 0x0046 407351199920SFeifei Xu #define mmBIOS_SCRATCH_14_BASE_IDX 1 407451199920SFeifei Xu #define mmBIOS_SCRATCH_15 0x0047 407551199920SFeifei Xu #define mmBIOS_SCRATCH_15_BASE_IDX 1 407651199920SFeifei Xu #define mmBIF_RLC_INTR_CNTL 0x004c 407751199920SFeifei Xu #define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 407851199920SFeifei Xu #define mmBIF_VCE_INTR_CNTL 0x004d 407951199920SFeifei Xu #define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 408051199920SFeifei Xu #define mmBIF_UVD_INTR_CNTL 0x004e 408151199920SFeifei Xu #define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 408251199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR0 0x006c 408351199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 408451199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d 408551199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 408651199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR1 0x006e 408751199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 408851199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f 408951199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 409051199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR2 0x0070 409151199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 409251199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 409351199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 409451199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR3 0x0072 409551199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 409651199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 409751199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 409851199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR4 0x0074 409951199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 410051199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 410151199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 410251199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR5 0x0076 410351199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 410451199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 410551199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 410651199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR6 0x0078 410751199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 410851199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 410951199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 411051199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR7 0x007a 411151199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 411251199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b 411351199920SFeifei Xu #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 411451199920SFeifei Xu #define mmGFX_MMIOREG_CAM_CNTL 0x007c 411551199920SFeifei Xu #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 411651199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d 411751199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 411851199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e 411951199920SFeifei Xu #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 412051199920SFeifei Xu #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f 412151199920SFeifei Xu #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 412251199920SFeifei Xu 412351199920SFeifei Xu 412451199920SFeifei Xu // addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec 412551199920SFeifei Xu // base address: 0x0 412651199920SFeifei Xu #define mmSYSHUB_INDEX 0x0008 412751199920SFeifei Xu #define mmSYSHUB_INDEX_BASE_IDX 0 412851199920SFeifei Xu #define mmSYSHUB_DATA 0x0009 412951199920SFeifei Xu #define mmSYSHUB_DATA_BASE_IDX 0 413051199920SFeifei Xu 413151199920SFeifei Xu 413251199920SFeifei Xu // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 413351199920SFeifei Xu // base address: 0x0 413451199920SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP0 0x000f 413551199920SFeifei Xu #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 413651199920SFeifei Xu 413751199920SFeifei Xu 413851199920SFeifei Xu // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 413951199920SFeifei Xu // base address: 0x0 414051199920SFeifei Xu #define mmEP_PCIE_SCRATCH 0x0023 414151199920SFeifei Xu #define mmEP_PCIE_SCRATCH_BASE_IDX 2 414251199920SFeifei Xu #define mmEP_PCIE_CNTL 0x0025 414351199920SFeifei Xu #define mmEP_PCIE_CNTL_BASE_IDX 2 414451199920SFeifei Xu #define mmEP_PCIE_INT_CNTL 0x0026 414551199920SFeifei Xu #define mmEP_PCIE_INT_CNTL_BASE_IDX 2 414651199920SFeifei Xu #define mmEP_PCIE_INT_STATUS 0x0027 414751199920SFeifei Xu #define mmEP_PCIE_INT_STATUS_BASE_IDX 2 414851199920SFeifei Xu #define mmEP_PCIE_RX_CNTL2 0x0028 414951199920SFeifei Xu #define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 415051199920SFeifei Xu #define mmEP_PCIE_BUS_CNTL 0x0029 415151199920SFeifei Xu #define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 415251199920SFeifei Xu #define mmEP_PCIE_CFG_CNTL 0x002a 415351199920SFeifei Xu #define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 415451199920SFeifei Xu #define mmEP_PCIE_TX_LTR_CNTL 0x002c 415551199920SFeifei Xu #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 415651199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002d 415751199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 415851199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002d 415951199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 416051199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002d 416151199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 416251199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002d 416351199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 416451199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x002e 416551199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 416651199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x002e 416751199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 416851199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x002e 416951199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 417051199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x002e 417151199920SFeifei Xu #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 417251199920SFeifei Xu #define mmEP_PCIE_F0_DPA_CAP 0x0032 417351199920SFeifei Xu #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 417451199920SFeifei Xu #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0033 417551199920SFeifei Xu #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 417651199920SFeifei Xu #define mmEP_PCIE_F0_DPA_CNTL 0x0033 417751199920SFeifei Xu #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 417851199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0033 417951199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 418051199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0034 418151199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 418251199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0034 418351199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 418451199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0034 418551199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 418651199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0034 418751199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 418851199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0035 418951199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 419051199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0035 419151199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 419251199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0035 419351199920SFeifei Xu #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 419451199920SFeifei Xu #define mmEP_PCIE_PME_CONTROL 0x0035 419551199920SFeifei Xu #define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 419651199920SFeifei Xu #define mmEP_PCIEP_RESERVED 0x0036 419751199920SFeifei Xu #define mmEP_PCIEP_RESERVED_BASE_IDX 2 419851199920SFeifei Xu #define mmEP_PCIE_TX_CNTL 0x0038 419951199920SFeifei Xu #define mmEP_PCIE_TX_CNTL_BASE_IDX 2 420051199920SFeifei Xu #define mmEP_PCIE_TX_REQUESTER_ID 0x0039 420151199920SFeifei Xu #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 420251199920SFeifei Xu #define mmEP_PCIE_ERR_CNTL 0x003a 420351199920SFeifei Xu #define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 420451199920SFeifei Xu #define mmEP_PCIE_RX_CNTL 0x003b 420551199920SFeifei Xu #define mmEP_PCIE_RX_CNTL_BASE_IDX 2 420651199920SFeifei Xu #define mmEP_PCIE_LC_SPEED_CNTL 0x003c 420751199920SFeifei Xu #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 420851199920SFeifei Xu 420951199920SFeifei Xu 421051199920SFeifei Xu // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 421151199920SFeifei Xu // base address: 0x0 421251199920SFeifei Xu #define mmDN_PCIE_RESERVED 0x0040 421351199920SFeifei Xu #define mmDN_PCIE_RESERVED_BASE_IDX 2 421451199920SFeifei Xu #define mmDN_PCIE_SCRATCH 0x0041 421551199920SFeifei Xu #define mmDN_PCIE_SCRATCH_BASE_IDX 2 421651199920SFeifei Xu #define mmDN_PCIE_CNTL 0x0043 421751199920SFeifei Xu #define mmDN_PCIE_CNTL_BASE_IDX 2 421851199920SFeifei Xu #define mmDN_PCIE_CONFIG_CNTL 0x0044 421951199920SFeifei Xu #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 422051199920SFeifei Xu #define mmDN_PCIE_RX_CNTL2 0x0045 422151199920SFeifei Xu #define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 422251199920SFeifei Xu #define mmDN_PCIE_BUS_CNTL 0x0046 422351199920SFeifei Xu #define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 422451199920SFeifei Xu #define mmDN_PCIE_CFG_CNTL 0x0047 422551199920SFeifei Xu #define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 422651199920SFeifei Xu 422751199920SFeifei Xu 422851199920SFeifei Xu // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 422951199920SFeifei Xu // base address: 0x0 423051199920SFeifei Xu #define mmPCIE_ERR_CNTL 0x004f 423151199920SFeifei Xu #define mmPCIE_ERR_CNTL_BASE_IDX 2 423251199920SFeifei Xu #define mmPCIE_RX_CNTL 0x0050 423351199920SFeifei Xu #define mmPCIE_RX_CNTL_BASE_IDX 2 423451199920SFeifei Xu #define mmPCIE_LC_SPEED_CNTL 0x0051 423551199920SFeifei Xu #define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 423651199920SFeifei Xu #define mmPCIE_LC_CNTL2 0x0052 423751199920SFeifei Xu #define mmPCIE_LC_CNTL2_BASE_IDX 2 423851199920SFeifei Xu #define mmPCIEP_STRAP_MISC 0x0053 423951199920SFeifei Xu #define mmPCIEP_STRAP_MISC_BASE_IDX 2 424051199920SFeifei Xu #define mmLTR_MSG_INFO_FROM_EP 0x0054 424151199920SFeifei Xu #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 424251199920SFeifei Xu 424351199920SFeifei Xu 424451199920SFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_BIFPFVFDEC1 424551199920SFeifei Xu // base address: 0x0 424651199920SFeifei Xu #define mmRCC_ERR_LOG 0x0085 424751199920SFeifei Xu #define mmRCC_ERR_LOG_BASE_IDX 2 424851199920SFeifei Xu #define mmRCC_DOORBELL_APER_EN 0x00c0 424951199920SFeifei Xu #define mmRCC_DOORBELL_APER_EN_BASE_IDX 2 425051199920SFeifei Xu #define mmRCC_CONFIG_MEMSIZE 0x00c3 425151199920SFeifei Xu #define mmRCC_CONFIG_MEMSIZE_BASE_IDX 2 425251199920SFeifei Xu #define mmRCC_CONFIG_RESERVED 0x00c4 425351199920SFeifei Xu #define mmRCC_CONFIG_RESERVED_BASE_IDX 2 42543aa0115dSMonk Liu #ifndef mmRCC_IOV_FUNC_IDENTIFIER 425551199920SFeifei Xu #define mmRCC_IOV_FUNC_IDENTIFIER 0x00c5 425651199920SFeifei Xu #define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 42573aa0115dSMonk Liu #endif 425851199920SFeifei Xu 425951199920SFeifei Xu 426051199920SFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 426151199920SFeifei Xu // base address: 0x0 426251199920SFeifei Xu #define mmRCC_ERR_INT_CNTL 0x0086 426351199920SFeifei Xu #define mmRCC_ERR_INT_CNTL_BASE_IDX 2 426451199920SFeifei Xu #define mmRCC_BACO_CNTL_MISC 0x0087 426551199920SFeifei Xu #define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 426651199920SFeifei Xu #define mmRCC_RESET_EN 0x0088 426751199920SFeifei Xu #define mmRCC_RESET_EN_BASE_IDX 2 426851199920SFeifei Xu #define mmRCC_VDM_SUPPORT 0x0089 426951199920SFeifei Xu #define mmRCC_VDM_SUPPORT_BASE_IDX 2 427051199920SFeifei Xu #define mmRCC_PEER_REG_RANGE0 0x00be 427151199920SFeifei Xu #define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 427251199920SFeifei Xu #define mmRCC_PEER_REG_RANGE1 0x00bf 427351199920SFeifei Xu #define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 427451199920SFeifei Xu #define mmRCC_BUS_CNTL 0x00c1 427551199920SFeifei Xu #define mmRCC_BUS_CNTL_BASE_IDX 2 427651199920SFeifei Xu #define mmRCC_CONFIG_CNTL 0x00c2 427751199920SFeifei Xu #define mmRCC_CONFIG_CNTL_BASE_IDX 2 427851199920SFeifei Xu #define mmRCC_CONFIG_F0_BASE 0x00c6 427951199920SFeifei Xu #define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 428051199920SFeifei Xu #define mmRCC_CONFIG_APER_SIZE 0x00c7 428151199920SFeifei Xu #define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 428251199920SFeifei Xu #define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 428351199920SFeifei Xu #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 428451199920SFeifei Xu #define mmRCC_XDMA_LO 0x00c9 428551199920SFeifei Xu #define mmRCC_XDMA_LO_BASE_IDX 2 428651199920SFeifei Xu #define mmRCC_XDMA_HI 0x00ca 428751199920SFeifei Xu #define mmRCC_XDMA_HI_BASE_IDX 2 428851199920SFeifei Xu #define mmRCC_FEATURES_CONTROL_MISC 0x00cb 428951199920SFeifei Xu #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 429051199920SFeifei Xu #define mmRCC_BUSNUM_CNTL1 0x00cc 429151199920SFeifei Xu #define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 429251199920SFeifei Xu #define mmRCC_BUSNUM_LIST0 0x00cd 429351199920SFeifei Xu #define mmRCC_BUSNUM_LIST0_BASE_IDX 2 429451199920SFeifei Xu #define mmRCC_BUSNUM_LIST1 0x00ce 429551199920SFeifei Xu #define mmRCC_BUSNUM_LIST1_BASE_IDX 2 429651199920SFeifei Xu #define mmRCC_BUSNUM_CNTL2 0x00cf 429751199920SFeifei Xu #define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 429851199920SFeifei Xu #define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 429951199920SFeifei Xu #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 430051199920SFeifei Xu #define mmRCC_HOST_BUSNUM 0x00d1 430151199920SFeifei Xu #define mmRCC_HOST_BUSNUM_BASE_IDX 2 430251199920SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 430351199920SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 430451199920SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 430551199920SFeifei Xu #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 430651199920SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 430751199920SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 430851199920SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 430951199920SFeifei Xu #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 431051199920SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 431151199920SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 431251199920SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 431351199920SFeifei Xu #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 431451199920SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 431551199920SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 431651199920SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 431751199920SFeifei Xu #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 431851199920SFeifei Xu #define mmRCC_CMN_LINK_CNTL 0x00de 431951199920SFeifei Xu #define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 432051199920SFeifei Xu #define mmRCC_EP_REQUESTERID_RESTORE 0x00df 432151199920SFeifei Xu #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 432251199920SFeifei Xu #define mmRCC_LTR_LSWITCH_CNTL 0x00e0 432351199920SFeifei Xu #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 432451199920SFeifei Xu #define mmRCC_MH_ARB_CNTL 0x00e1 432551199920SFeifei Xu #define mmRCC_MH_ARB_CNTL_BASE_IDX 2 432651199920SFeifei Xu 432751199920SFeifei Xu 432851199920SFeifei Xu // addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 432951199920SFeifei Xu // base address: 0x0 433051199920SFeifei Xu #define mmBIF_MM_INDACCESS_CNTL 0x00e6 433151199920SFeifei Xu #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 433251199920SFeifei Xu #define mmBUS_CNTL 0x00e7 433351199920SFeifei Xu #define mmBUS_CNTL_BASE_IDX 2 433451199920SFeifei Xu #define mmBIF_SCRATCH0 0x00e8 433551199920SFeifei Xu #define mmBIF_SCRATCH0_BASE_IDX 2 433651199920SFeifei Xu #define mmBIF_SCRATCH1 0x00e9 433751199920SFeifei Xu #define mmBIF_SCRATCH1_BASE_IDX 2 433851199920SFeifei Xu #define mmBX_RESET_EN 0x00ed 433951199920SFeifei Xu #define mmBX_RESET_EN_BASE_IDX 2 434051199920SFeifei Xu #define mmMM_CFGREGS_CNTL 0x00ee 434151199920SFeifei Xu #define mmMM_CFGREGS_CNTL_BASE_IDX 2 434251199920SFeifei Xu #define mmBX_RESET_CNTL 0x00f0 434351199920SFeifei Xu #define mmBX_RESET_CNTL_BASE_IDX 2 434451199920SFeifei Xu #define mmINTERRUPT_CNTL 0x00f1 434551199920SFeifei Xu #define mmINTERRUPT_CNTL_BASE_IDX 2 434651199920SFeifei Xu #define mmINTERRUPT_CNTL2 0x00f2 434751199920SFeifei Xu #define mmINTERRUPT_CNTL2_BASE_IDX 2 434851199920SFeifei Xu #define mmCLKREQB_PAD_CNTL 0x00f8 434951199920SFeifei Xu #define mmCLKREQB_PAD_CNTL_BASE_IDX 2 435051199920SFeifei Xu #define mmBIF_FEATURES_CONTROL_MISC 0x00fb 435151199920SFeifei Xu #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 435251199920SFeifei Xu #define mmBIF_DOORBELL_CNTL 0x00fc 435351199920SFeifei Xu #define mmBIF_DOORBELL_CNTL_BASE_IDX 2 435451199920SFeifei Xu #define mmBIF_DOORBELL_INT_CNTL 0x00fd 435551199920SFeifei Xu #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 435651199920SFeifei Xu #define mmBIF_FB_EN 0x00ff 435751199920SFeifei Xu #define mmBIF_FB_EN_BASE_IDX 2 435851199920SFeifei Xu #define mmBIF_BUSY_DELAY_CNTR 0x0100 435951199920SFeifei Xu #define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2 436051199920SFeifei Xu #define mmBIF_MST_TRANS_PENDING_VF 0x0109 436151199920SFeifei Xu #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 436251199920SFeifei Xu #define mmBIF_SLV_TRANS_PENDING_VF 0x010a 436351199920SFeifei Xu #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 436451199920SFeifei Xu #define mmBACO_CNTL 0x010b 436551199920SFeifei Xu #define mmBACO_CNTL_BASE_IDX 2 436651199920SFeifei Xu #define mmBIF_BACO_EXIT_TIME0 0x010c 436751199920SFeifei Xu #define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 436851199920SFeifei Xu #define mmBIF_BACO_EXIT_TIMER1 0x010d 436951199920SFeifei Xu #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 437051199920SFeifei Xu #define mmBIF_BACO_EXIT_TIMER2 0x010e 437151199920SFeifei Xu #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 437251199920SFeifei Xu #define mmBIF_BACO_EXIT_TIMER3 0x010f 437351199920SFeifei Xu #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 437451199920SFeifei Xu #define mmBIF_BACO_EXIT_TIMER4 0x0110 437551199920SFeifei Xu #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 437651199920SFeifei Xu #define mmMEM_TYPE_CNTL 0x0111 437751199920SFeifei Xu #define mmMEM_TYPE_CNTL_BASE_IDX 2 437851199920SFeifei Xu #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0113 437951199920SFeifei Xu #define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 2 438051199920SFeifei Xu #define mmBIF_VDDGFX_GFX0_LOWER 0x0114 438151199920SFeifei Xu #define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 2 438251199920SFeifei Xu #define mmBIF_VDDGFX_GFX0_UPPER 0x0115 438351199920SFeifei Xu #define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 2 438451199920SFeifei Xu #define mmBIF_VDDGFX_GFX1_LOWER 0x0116 438551199920SFeifei Xu #define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 2 438651199920SFeifei Xu #define mmBIF_VDDGFX_GFX1_UPPER 0x0117 438751199920SFeifei Xu #define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 2 438851199920SFeifei Xu #define mmBIF_VDDGFX_GFX2_LOWER 0x0118 438951199920SFeifei Xu #define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 2 439051199920SFeifei Xu #define mmBIF_VDDGFX_GFX2_UPPER 0x0119 439151199920SFeifei Xu #define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 2 439251199920SFeifei Xu #define mmBIF_VDDGFX_GFX3_LOWER 0x011a 439351199920SFeifei Xu #define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 2 439451199920SFeifei Xu #define mmBIF_VDDGFX_GFX3_UPPER 0x011b 439551199920SFeifei Xu #define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 2 439651199920SFeifei Xu #define mmBIF_VDDGFX_GFX4_LOWER 0x011c 439751199920SFeifei Xu #define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 2 439851199920SFeifei Xu #define mmBIF_VDDGFX_GFX4_UPPER 0x011d 439951199920SFeifei Xu #define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 2 440051199920SFeifei Xu #define mmBIF_VDDGFX_GFX5_LOWER 0x011e 440151199920SFeifei Xu #define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 2 440251199920SFeifei Xu #define mmBIF_VDDGFX_GFX5_UPPER 0x011f 440351199920SFeifei Xu #define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 2 440451199920SFeifei Xu #define mmBIF_VDDGFX_RSV1_LOWER 0x0120 440551199920SFeifei Xu #define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 2 440651199920SFeifei Xu #define mmBIF_VDDGFX_RSV1_UPPER 0x0121 440751199920SFeifei Xu #define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 2 440851199920SFeifei Xu #define mmBIF_VDDGFX_RSV2_LOWER 0x0122 440951199920SFeifei Xu #define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 2 441051199920SFeifei Xu #define mmBIF_VDDGFX_RSV2_UPPER 0x0123 441151199920SFeifei Xu #define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 2 441251199920SFeifei Xu #define mmBIF_VDDGFX_RSV3_LOWER 0x0124 441351199920SFeifei Xu #define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 2 441451199920SFeifei Xu #define mmBIF_VDDGFX_RSV3_UPPER 0x0125 441551199920SFeifei Xu #define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 2 441651199920SFeifei Xu #define mmBIF_VDDGFX_RSV4_LOWER 0x0126 441751199920SFeifei Xu #define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 2 441851199920SFeifei Xu #define mmBIF_VDDGFX_RSV4_UPPER 0x0127 441951199920SFeifei Xu #define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 2 442051199920SFeifei Xu #define mmBIF_VDDGFX_FB_CMP 0x0128 442151199920SFeifei Xu #define mmBIF_VDDGFX_FB_CMP_BASE_IDX 2 442251199920SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0129 442351199920SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 2 442451199920SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x012a 442551199920SFeifei Xu #define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 2 442651199920SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x012b 442751199920SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 2 442851199920SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x012c 442951199920SFeifei Xu #define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 2 443051199920SFeifei Xu #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d 443151199920SFeifei Xu #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 443251199920SFeifei Xu #define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e 443351199920SFeifei Xu #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 443451199920SFeifei Xu #define mmBIF_RB_CNTL 0x012f 443551199920SFeifei Xu #define mmBIF_RB_CNTL_BASE_IDX 2 443651199920SFeifei Xu #define mmBIF_RB_BASE 0x0130 443751199920SFeifei Xu #define mmBIF_RB_BASE_BASE_IDX 2 443851199920SFeifei Xu #define mmBIF_RB_RPTR 0x0131 443951199920SFeifei Xu #define mmBIF_RB_RPTR_BASE_IDX 2 444051199920SFeifei Xu #define mmBIF_RB_WPTR 0x0132 444151199920SFeifei Xu #define mmBIF_RB_WPTR_BASE_IDX 2 444251199920SFeifei Xu #define mmBIF_RB_WPTR_ADDR_HI 0x0133 444351199920SFeifei Xu #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 444451199920SFeifei Xu #define mmBIF_RB_WPTR_ADDR_LO 0x0134 444551199920SFeifei Xu #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 444651199920SFeifei Xu #define mmMAILBOX_INDEX 0x0135 444751199920SFeifei Xu #define mmMAILBOX_INDEX_BASE_IDX 2 444851199920SFeifei Xu #define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 444951199920SFeifei Xu #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 445051199920SFeifei Xu #define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 445151199920SFeifei Xu #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 445251199920SFeifei Xu #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 445351199920SFeifei Xu #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 445451199920SFeifei Xu #define mmBIF_PERSTB_PAD_CNTL 0x0148 445551199920SFeifei Xu #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 445651199920SFeifei Xu #define mmBIF_PX_EN_PAD_CNTL 0x0149 445751199920SFeifei Xu #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 445851199920SFeifei Xu #define mmBIF_REFPADKIN_PAD_CNTL 0x014a 445951199920SFeifei Xu #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 446051199920SFeifei Xu #define mmBIF_CLKREQB_PAD_CNTL 0x014b 446151199920SFeifei Xu #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 446251199920SFeifei Xu 446351199920SFeifei Xu 446451199920SFeifei Xu // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 446551199920SFeifei Xu // base address: 0x0 446651199920SFeifei Xu #define mmBIF_BME_STATUS 0x00eb 446751199920SFeifei Xu #define mmBIF_BME_STATUS_BASE_IDX 2 446851199920SFeifei Xu #define mmBIF_ATOMIC_ERR_LOG 0x00ec 446951199920SFeifei Xu #define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 2 447051199920SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 447151199920SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 447251199920SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 447351199920SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 447451199920SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 447551199920SFeifei Xu #define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 447651199920SFeifei Xu #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 447751199920SFeifei Xu #define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 447851199920SFeifei Xu #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 447951199920SFeifei Xu #define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 448051199920SFeifei Xu #define mmGPU_HDP_FLUSH_REQ 0x0106 448151199920SFeifei Xu #define mmGPU_HDP_FLUSH_REQ_BASE_IDX 2 448251199920SFeifei Xu #define mmGPU_HDP_FLUSH_DONE 0x0107 448351199920SFeifei Xu #define mmGPU_HDP_FLUSH_DONE_BASE_IDX 2 448451199920SFeifei Xu #define mmBIF_TRANS_PENDING 0x0108 448551199920SFeifei Xu #define mmBIF_TRANS_PENDING_BASE_IDX 2 448651199920SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW0 0x0136 448751199920SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 448851199920SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW1 0x0137 448951199920SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 449051199920SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW2 0x0138 449151199920SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 449251199920SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW3 0x0139 449351199920SFeifei Xu #define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 449451199920SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW0 0x013a 449551199920SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 449651199920SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW1 0x013b 449751199920SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 449851199920SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW2 0x013c 449951199920SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 450051199920SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW3 0x013d 450151199920SFeifei Xu #define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 450251199920SFeifei Xu #define mmMAILBOX_CONTROL 0x013e 450351199920SFeifei Xu #define mmMAILBOX_CONTROL_BASE_IDX 2 450451199920SFeifei Xu #define mmMAILBOX_INT_CNTL 0x013f 450551199920SFeifei Xu #define mmMAILBOX_INT_CNTL_BASE_IDX 2 450651199920SFeifei Xu #define mmBIF_VMHV_MAILBOX 0x0140 450751199920SFeifei Xu #define mmBIF_VMHV_MAILBOX_BASE_IDX 2 450851199920SFeifei Xu 450951199920SFeifei Xu 451051199920SFeifei Xu // addressBlock: nbio_nbif0_gdc_GDCDEC 451151199920SFeifei Xu // base address: 0x0 451251199920SFeifei Xu #define mmNGDC_SDP_PORT_CTRL 0x01c2 451351199920SFeifei Xu #define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 451451199920SFeifei Xu #define mmSHUB_REGS_IF_CTL 0x01c3 451551199920SFeifei Xu #define mmSHUB_REGS_IF_CTL_BASE_IDX 2 451651199920SFeifei Xu #define mmNGDC_RESERVED_0 0x01cb 451751199920SFeifei Xu #define mmNGDC_RESERVED_0_BASE_IDX 2 451851199920SFeifei Xu #define mmNGDC_RESERVED_1 0x01cc 451951199920SFeifei Xu #define mmNGDC_RESERVED_1_BASE_IDX 2 452051199920SFeifei Xu #define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd 452151199920SFeifei Xu #define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 452251199920SFeifei Xu #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 452351199920SFeifei Xu #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 452451199920SFeifei Xu #define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 452551199920SFeifei Xu #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 452651199920SFeifei Xu #define mmBIF_IH_DOORBELL_RANGE 0x01d2 452751199920SFeifei Xu #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 452851199920SFeifei Xu #define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 452951199920SFeifei Xu #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 453051199920SFeifei Xu #define mmATDMA_MISC_CNTL 0x01dd 453151199920SFeifei Xu #define mmATDMA_MISC_CNTL_BASE_IDX 2 453251199920SFeifei Xu #define mmBIF_DOORBELL_FENCE_CNTL 0x01de 453351199920SFeifei Xu #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 453451199920SFeifei Xu #define mmS2A_MISC_CNTL 0x01df 453551199920SFeifei Xu #define mmS2A_MISC_CNTL_BASE_IDX 2 453651199920SFeifei Xu #define mmGDC_PG_MISC_CNTL 0x01f0 453751199920SFeifei Xu #define mmGDC_PG_MISC_CNTL_BASE_IDX 2 453851199920SFeifei Xu 453951199920SFeifei Xu 454051199920SFeifei Xu // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC2 454151199920SFeifei Xu // base address: 0x0 454251199920SFeifei Xu #define mmGFXMSIX_VECT0_ADDR_LO 0x0400 454351199920SFeifei Xu #define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 454451199920SFeifei Xu #define mmGFXMSIX_VECT0_ADDR_HI 0x0401 454551199920SFeifei Xu #define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 454651199920SFeifei Xu #define mmGFXMSIX_VECT0_MSG_DATA 0x0402 454751199920SFeifei Xu #define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 454851199920SFeifei Xu #define mmGFXMSIX_VECT0_CONTROL 0x0403 454951199920SFeifei Xu #define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 3 455051199920SFeifei Xu #define mmGFXMSIX_VECT1_ADDR_LO 0x0404 455151199920SFeifei Xu #define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 455251199920SFeifei Xu #define mmGFXMSIX_VECT1_ADDR_HI 0x0405 455351199920SFeifei Xu #define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 455451199920SFeifei Xu #define mmGFXMSIX_VECT1_MSG_DATA 0x0406 455551199920SFeifei Xu #define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 455651199920SFeifei Xu #define mmGFXMSIX_VECT1_CONTROL 0x0407 455751199920SFeifei Xu #define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 3 455851199920SFeifei Xu #define mmGFXMSIX_VECT2_ADDR_LO 0x0408 455951199920SFeifei Xu #define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 456051199920SFeifei Xu #define mmGFXMSIX_VECT2_ADDR_HI 0x0409 456151199920SFeifei Xu #define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 456251199920SFeifei Xu #define mmGFXMSIX_VECT2_MSG_DATA 0x040a 456351199920SFeifei Xu #define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 456451199920SFeifei Xu #define mmGFXMSIX_VECT2_CONTROL 0x040b 456551199920SFeifei Xu #define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 3 456651199920SFeifei Xu #define mmGFXMSIX_PBA 0x0800 456751199920SFeifei Xu #define mmGFXMSIX_PBA_BASE_IDX 3 456851199920SFeifei Xu 456951199920SFeifei Xu 457051199920SFeifei Xu // addressBlock: syshub_mmreg_ind_syshubind 457151199920SFeifei Xu // base address: 0x0 457251199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK 0x10000 457351199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 457451199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 457551199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c 457651199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 457751199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 457851199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL 0x10018 457951199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL 0x1001c 458051199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL 0x10020 458151199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL 0x10024 458251199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL 0x10028 458351199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL 0x1002c 458451199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL 0x10030 458551199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL 0x10034 458651199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL 0x10038 458751199920SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL 0x10100 458851199920SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL 0x10104 458951199920SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL 0x10108 459051199920SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL 0x1010c 459151199920SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL 0x10110 459251199920SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL 0x10114 459351199920SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL 0x10118 459451199920SFeifei Xu #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL 0x1011c 459551199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL 0x10300 459651199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE 0x10308 459751199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER 0x1030c 459851199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK 0x10310 459951199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET 0x10314 460051199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH 0x10f00 460151199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK 0x10f04 460251199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 460351199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 460451199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 460551199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c 460651199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 460751199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 460851199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL 0x11018 460951199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL 0x1101c 461051199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL 0x11020 461151199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL 0x11024 461251199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL 0x11028 461351199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL 0x1102c 461451199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL 0x11030 461551199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL 0x11034 461651199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL 0x11038 461751199920SFeifei Xu #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL 0x1103c 461851199920SFeifei Xu #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK 0x11040 461951199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD 0x20108 462051199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS 0x30008 462151199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS 0x31008 462251199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD 0x40108 462351199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD 0x50008 462451199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD 0x51008 462551199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD 0x52008 462651199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD 0x60108 462751199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD 0x61108 462851199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD 0x62108 462951199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD 0x63108 463051199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD 0x64108 463151199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS 0x70008 463251199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD 0xc0108 463351199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD 0xc1108 463451199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD 0xc2108 463551199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD 0xc3108 463651199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD 0xc4108 463751199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD 0xd0008 463851199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD 0xe0108 463951199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD 0xe1108 464051199920SFeifei Xu #define ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD 0xf0008 464151199920SFeifei Xu 464251199920SFeifei Xu #endif 4643