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/openbmc/linux/drivers/media/usb/gspca/
H A Dspca508.c23 #define CreativeVista 0
51 .priv = 0},
62 {0x0000, 0x870b},
64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */
65 {0x0003, 0x8111}, /* Reset compression & memory */
66 {0x0000, 0x8110}, /* Disable all outputs */
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
68 {0x0000, 0x8114}, /* SW GPIO data */
69 {0x0008, 0x8110}, /* Enable charge pump output */
70 {0x0002, 0x8116}, /* 200 kHz pump clock */
[all …]
H A Dspca501.c29 #define Arowana300KCMOSCamera 0
53 .priv = 0},
56 #define SPCA50X_REG_USB 0x2 /* spca505 501 */
65 #define SPCA501_SNAPBIT 0x80
66 #define SPCA501_SNAPCTRL 0x10
78 #define SPCA501_PROP_SNAP(d) ((d) & 0x40)
79 #define SPCA501_PROP_SNAP_CTRL(d) ((d) & 0x10)
80 #define SPCA501_PROP_COMP_THRESH(d) (((d) & 0x0e) >> 1)
81 #define SPCA501_PROP_COMP_QUANT(d) (((d) & 0x70) >> 4)
84 #define SPCA501_REG_CCDSP 0x01
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dtables_phy_lcn.c30 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
31 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
32 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
33 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
34 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
35 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
36 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
37 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
38 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
39 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
[all …]
/openbmc/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/openbmc/linux/drivers/media/i2c/s5c73m3/
H A Ds5c73m3.h44 #define AHB_MSB_ADDR_PTR 0xfcfc
45 #define REG_CMDWR_ADDRH 0x0050
46 #define REG_CMDWR_ADDRL 0x0054
47 #define REG_CMDRD_ADDRH 0x0058
48 #define REG_CMDRD_ADDRL 0x005c
49 #define REG_CMDBUF_ADDR 0x0f14
51 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52 #define SEQ_END_PLL (1<<0x0)
53 #define SEQ_END_SENSOR (1<<0x1)
54 #define SEQ_END_GPIO (1<<0x2)
[all …]
/openbmc/linux/drivers/net/ethernet/atheros/atl1c/
H A Datl1c.h43 #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
44 #define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
45 #define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
46 #define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
47 #define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
50 _tag = ((((_vlan) >> 8) & 0xFF) |\
51 (((_vlan) & 0xFF) << 8))
54 _vlan = ((((_tag) >> 8) & 0xFF) |\
55 (((_tag) & 0xFF) << 8))
57 #define SPEED_0 0xffff
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dps3av.h13 #define PS3AV_VERSION 0x205 /* version of ps3av command */
15 #define PS3AV_CID_AV_INIT 0x00000001
16 #define PS3AV_CID_AV_FIN 0x00000002
17 #define PS3AV_CID_AV_GET_HW_CONF 0x00000003
18 #define PS3AV_CID_AV_GET_MONITOR_INFO 0x00000004
19 #define PS3AV_CID_AV_ENABLE_EVENT 0x00000006
20 #define PS3AV_CID_AV_DISABLE_EVENT 0x00000007
21 #define PS3AV_CID_AV_TV_MUTE 0x0000000a
23 #define PS3AV_CID_AV_VIDEO_CS 0x00010001
24 #define PS3AV_CID_AV_VIDEO_MUTE 0x00010002
[all …]
/openbmc/linux/drivers/net/phy/mscc/
H A Dmscc_ptp.h13 #define BIU_ADDR_EXE 0x8000
14 #define BIU_ADDR_READ 0x4000
15 #define BIU_ADDR_WRITE 0x0000
23 #define MSCC_PHY_1588_INGR_VSC85XX_INT_STATUS 0x002d
24 #define MSCC_PHY_1588_VSC85XX_INT_STATUS 0x004d
25 #define VSC85XX_1588_INT_FIFO_ADD 0x0004
26 #define VSC85XX_1588_INT_FIFO_OVERFLOW 0x0001
28 #define MSCC_PHY_1588_INGR_VSC85XX_INT_MASK 0x002e
29 #define MSCC_PHY_1588_VSC85XX_INT_MASK 0x004e
34 #define MSCC_PHY_ANA_ETH1_NTX_PROT 0x0000
[all …]
/openbmc/linux/include/linux/mfd/wm8350/
H A Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
/openbmc/u-boot/drivers/sound/
H A Dwm8994_registers.h12 #define WM8994_SOFTWARE_RESET 0x00
13 #define WM8994_POWER_MANAGEMENT_1 0x01
14 #define WM8994_POWER_MANAGEMENT_2 0x02
15 #define WM8994_POWER_MANAGEMENT_4 0x04
16 #define WM8994_POWER_MANAGEMENT_5 0x05
17 #define WM8994_LEFT_OUTPUT_VOLUME 0x1C
18 #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
19 #define WM8994_OUTPUT_MIXER_1 0x2D
20 #define WM8994_OUTPUT_MIXER_2 0x2E
21 #define WM8994_CHARGE_PUMP_1 0x4C
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm8903.h22 #define WM8903_SW_RESET_AND_ID 0x00
23 #define WM8903_REVISION_NUMBER 0x01
24 #define WM8903_BIAS_CONTROL_0 0x04
25 #define WM8903_VMID_CONTROL_0 0x05
26 #define WM8903_MIC_BIAS_CONTROL_0 0x06
27 #define WM8903_ANALOGUE_DAC_0 0x08
28 #define WM8903_ANALOGUE_ADC_0 0x0A
29 #define WM8903_POWER_MANAGEMENT_0 0x0C
30 #define WM8903_POWER_MANAGEMENT_1 0x0D
31 #define WM8903_POWER_MANAGEMENT_2 0x0E
[all …]
H A Dtlv320aic23.h19 #define TLV320AIC23_LINVOL 0x00
20 #define TLV320AIC23_RINVOL 0x01
21 #define TLV320AIC23_LCHNVOL 0x02
22 #define TLV320AIC23_RCHNVOL 0x03
23 #define TLV320AIC23_ANLG 0x04
24 #define TLV320AIC23_DIGT 0x05
25 #define TLV320AIC23_PWR 0x06
26 #define TLV320AIC23_DIGT_FMT 0x07
27 #define TLV320AIC23_SRATE 0x08
28 #define TLV320AIC23_ACTIVE 0x09
[all …]
H A Dwm8904.h13 #define WM8904_CLK_AUTO 0
25 #define WM8904_SW_RESET_AND_ID 0x00
26 #define WM8904_REVISION 0x01
27 #define WM8904_BIAS_CONTROL_0 0x04
28 #define WM8904_VMID_CONTROL_0 0x05
29 #define WM8904_MIC_BIAS_CONTROL_0 0x06
30 #define WM8904_MIC_BIAS_CONTROL_1 0x07
31 #define WM8904_ANALOGUE_DAC_0 0x08
32 #define WM8904_MIC_FILTER_CONTROL 0x09
33 #define WM8904_ANALOGUE_ADC_0 0x0A
[all …]
/openbmc/linux/drivers/net/ethernet/atheros/alx/
H A Dhw.h45 * 31 16 0
60 * if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
68 * 0-+ 0-+
72 * 4 | (7:0) 4 | (7:0)
76 * 8 Custom csum enable = 1 8 Custom csum enable = 0
115 #define TPD_CXSUMSTART_MASK 0x00FF
116 #define TPD_CXSUMSTART_SHIFT 0
117 #define TPD_L4HDROFFSET_MASK 0x00FF
118 #define TPD_L4HDROFFSET_SHIFT 0
119 #define TPD_CXSUM_EN_MASK 0x0001
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_powertune.c41 …TL, 0xFFFFFFFF, 0, …
42 …TL, 0xFFFFFFFF, 0, …
43 …TL, 0xFFFFFFFF, 0, …
44 …TL, 0xFFFFFFFF, 0, …
45 …TL, 0xFFFFFFFF, 0, …
46 …TL, 0xFFFFFFFF, 0, …
47 …TL, 0xFFFFFFFF, 0, …
48 …TL, 0xFFFFFFFF, 0, …
49 …TL, 0xFFFFFFFF, 0, …
51 …TL, 0xFFFFFFFF, 0, …
[all …]
/openbmc/u-boot/include/linux/
H A Dmdio.h65 #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
66 #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
67 #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
68 #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
69 #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
70 #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
76 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
80 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001
87 #define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
88 #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
[all …]
H A Dapm_bios.h34 #define APM_16_BIT_SUPPORT 0x0001
35 #define APM_32_BIT_SUPPORT 0x0002
36 #define APM_IDLE_SLOWS_CLOCK 0x0004
37 #define APM_BIOS_DISABLED 0x0008
38 #define APM_BIOS_DISENGAGED 0x0010
57 #define APM_FUNC_INST_CHECK 0x5300
58 #define APM_FUNC_REAL_CONN 0x5301
59 #define APM_FUNC_16BIT_CONN 0x5302
60 #define APM_FUNC_32BIT_CONN 0x5303
61 #define APM_FUNC_DISCONN 0x5304
[all …]
/openbmc/u-boot/drivers/usb/eth/
H A Dr8152.h12 #define PLA_IDR 0xc000
13 #define PLA_RCR 0xc010
14 #define PLA_RMS 0xc016
15 #define PLA_RXFIFO_CTRL0 0xc0a0
16 #define PLA_RXFIFO_CTRL1 0xc0a4
17 #define PLA_RXFIFO_CTRL2 0xc0a8
18 #define PLA_DMY_REG0 0xc0b0
19 #define PLA_FMC 0xc0b4
20 #define PLA_CFG_WOL 0xc0b6
21 #define PLA_TEREDO_CFG 0xc0bc
[all …]
/openbmc/linux/include/uapi/linux/
H A Dmdio.h76 #define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
79 #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
89 #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
90 #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
91 #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
92 #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
93 #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
94 #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
100 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
104 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001
[all …]
/openbmc/linux/drivers/net/ethernet/atheros/atl1e/
H A Datl1e.h43 #define PCI_REG_COMMAND 0x04 /* PCI Command Register */
44 #define CMD_IO_SPACE 0x0001
45 #define CMD_MEMORY_SPACE 0x0002
46 #define CMD_BUS_MASTER 0x0004
48 #define BAR_0 0
53 #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
54 #define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
55 #define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
56 #define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
57 #define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/openbmc/linux/drivers/media/pci/pluto2/
H A Dpluto2.c35 #define REG_PCAR 0x0020 /* PC address register */
36 #define REG_TSCR 0x0024 /* TS ctrl & status */
37 #define REG_MISC 0x0028 /* miscellaneous */
38 #define REG_MMAC 0x002c /* MSB MAC address */
39 #define REG_IMAC 0x0030 /* ISB MAC address */
40 #define REG_LMAC 0x0034 /* LSB MAC address */
41 #define REG_SPID 0x0038 /* SPI data */
42 #define REG_SLCS 0x003c /* serial links ctrl/status */
44 #define PID0_NOFIL (0x0001 << 16)
45 #define PIDn_ENP (0x0001 << 15)
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_emac.h57 #define AT91_EMAC_CTL_LB 0x0001
58 #define AT91_EMAC_CTL_LBL 0x0002
59 #define AT91_EMAC_CTL_RE 0x0004
60 #define AT91_EMAC_CTL_TE 0x0008
61 #define AT91_EMAC_CTL_MPE 0x0010
62 #define AT91_EMAC_CTL_CSR 0x0020
63 #define AT91_EMAC_CTL_ISR 0x0040
64 #define AT91_EMAC_CTL_WES 0x0080
65 #define AT91_EMAC_CTL_BP 0x1000
67 #define AT91_EMAC_CFG_SPD 0x0001
[all …]
/openbmc/linux/include/sound/
H A Dwm8903.h15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
/openbmc/linux/include/linux/mfd/arizona/
H A Dregisters.h16 #define ARIZONA_SOFTWARE_RESET 0x00
17 #define ARIZONA_DEVICE_REVISION 0x01
18 #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
19 #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
20 #define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A
21 #define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B
22 #define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C
23 #define ARIZONA_CTRL_IF_STATUS_1 0x0D
24 #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
25 #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
[all …]

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