12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2f1c0a02fSMark Brown /* 3f1c0a02fSMark Brown * wm8903.h - WM8903 audio codec interface 4f1c0a02fSMark Brown * 5f1c0a02fSMark Brown * Copyright 2008 Wolfson Microelectronics PLC. 6f1c0a02fSMark Brown * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7f1c0a02fSMark Brown */ 8f1c0a02fSMark Brown 9f1c0a02fSMark Brown #ifndef _WM8903_H 10f1c0a02fSMark Brown #define _WM8903_H 11f1c0a02fSMark Brown 12f1c0a02fSMark Brown #include <linux/i2c.h> 13f1c0a02fSMark Brown 1458bd2934SKuninori Morimoto extern int wm8903_mic_detect(struct snd_soc_component *component, 157245387eSMark Brown struct snd_soc_jack *jack, 167245387eSMark Brown int det, int shrt); 177245387eSMark Brown 18f1c0a02fSMark Brown 19f1c0a02fSMark Brown /* 20f1c0a02fSMark Brown * Register values. 21f1c0a02fSMark Brown */ 22f1c0a02fSMark Brown #define WM8903_SW_RESET_AND_ID 0x00 23f1c0a02fSMark Brown #define WM8903_REVISION_NUMBER 0x01 24f1c0a02fSMark Brown #define WM8903_BIAS_CONTROL_0 0x04 25f1c0a02fSMark Brown #define WM8903_VMID_CONTROL_0 0x05 26f1c0a02fSMark Brown #define WM8903_MIC_BIAS_CONTROL_0 0x06 27f1c0a02fSMark Brown #define WM8903_ANALOGUE_DAC_0 0x08 28f1c0a02fSMark Brown #define WM8903_ANALOGUE_ADC_0 0x0A 29f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_0 0x0C 30f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_1 0x0D 31f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_2 0x0E 32f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_3 0x0F 33f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_4 0x10 34f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_5 0x11 35f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_6 0x12 36f1c0a02fSMark Brown #define WM8903_CLOCK_RATES_0 0x14 37f1c0a02fSMark Brown #define WM8903_CLOCK_RATES_1 0x15 38f1c0a02fSMark Brown #define WM8903_CLOCK_RATES_2 0x16 39f1c0a02fSMark Brown #define WM8903_AUDIO_INTERFACE_0 0x18 40f1c0a02fSMark Brown #define WM8903_AUDIO_INTERFACE_1 0x19 41f1c0a02fSMark Brown #define WM8903_AUDIO_INTERFACE_2 0x1A 42f1c0a02fSMark Brown #define WM8903_AUDIO_INTERFACE_3 0x1B 43f1c0a02fSMark Brown #define WM8903_DAC_DIGITAL_VOLUME_LEFT 0x1E 44f1c0a02fSMark Brown #define WM8903_DAC_DIGITAL_VOLUME_RIGHT 0x1F 45f1c0a02fSMark Brown #define WM8903_DAC_DIGITAL_0 0x20 46f1c0a02fSMark Brown #define WM8903_DAC_DIGITAL_1 0x21 47f1c0a02fSMark Brown #define WM8903_ADC_DIGITAL_VOLUME_LEFT 0x24 48f1c0a02fSMark Brown #define WM8903_ADC_DIGITAL_VOLUME_RIGHT 0x25 49f1c0a02fSMark Brown #define WM8903_ADC_DIGITAL_0 0x26 50f1c0a02fSMark Brown #define WM8903_DIGITAL_MICROPHONE_0 0x27 51f1c0a02fSMark Brown #define WM8903_DRC_0 0x28 52f1c0a02fSMark Brown #define WM8903_DRC_1 0x29 53f1c0a02fSMark Brown #define WM8903_DRC_2 0x2A 54f1c0a02fSMark Brown #define WM8903_DRC_3 0x2B 55f1c0a02fSMark Brown #define WM8903_ANALOGUE_LEFT_INPUT_0 0x2C 56f1c0a02fSMark Brown #define WM8903_ANALOGUE_RIGHT_INPUT_0 0x2D 57f1c0a02fSMark Brown #define WM8903_ANALOGUE_LEFT_INPUT_1 0x2E 58f1c0a02fSMark Brown #define WM8903_ANALOGUE_RIGHT_INPUT_1 0x2F 59f1c0a02fSMark Brown #define WM8903_ANALOGUE_LEFT_MIX_0 0x32 60f1c0a02fSMark Brown #define WM8903_ANALOGUE_RIGHT_MIX_0 0x33 61f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_MIX_LEFT_0 0x34 62f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_MIX_LEFT_1 0x35 63f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_MIX_RIGHT_0 0x36 64f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_MIX_RIGHT_1 0x37 65f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT1_LEFT 0x39 66f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT1_RIGHT 0x3A 67f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT2_LEFT 0x3B 68f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT2_RIGHT 0x3C 69f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT3_LEFT 0x3E 70f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT3_RIGHT 0x3F 71f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0 0x41 72f1c0a02fSMark Brown #define WM8903_DC_SERVO_0 0x43 73f1c0a02fSMark Brown #define WM8903_DC_SERVO_2 0x45 74c5b6a9feSMark Brown #define WM8903_DC_SERVO_4 0x47 75c5b6a9feSMark Brown #define WM8903_DC_SERVO_5 0x48 76c5b6a9feSMark Brown #define WM8903_DC_SERVO_6 0x49 77c5b6a9feSMark Brown #define WM8903_DC_SERVO_7 0x4A 78c5b6a9feSMark Brown #define WM8903_DC_SERVO_READBACK_1 0x51 79c5b6a9feSMark Brown #define WM8903_DC_SERVO_READBACK_2 0x52 80c5b6a9feSMark Brown #define WM8903_DC_SERVO_READBACK_3 0x53 81c5b6a9feSMark Brown #define WM8903_DC_SERVO_READBACK_4 0x54 82f1c0a02fSMark Brown #define WM8903_ANALOGUE_HP_0 0x5A 83f1c0a02fSMark Brown #define WM8903_ANALOGUE_LINEOUT_0 0x5E 84f1c0a02fSMark Brown #define WM8903_CHARGE_PUMP_0 0x62 85f1c0a02fSMark Brown #define WM8903_CLASS_W_0 0x68 86f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_0 0x6C 87f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_1 0x6D 88f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_2 0x6E 89f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_3 0x6F 90f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_4 0x70 91f1c0a02fSMark Brown #define WM8903_CONTROL_INTERFACE 0x72 92f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_1 0x74 93f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_2 0x75 94f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_3 0x76 95f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_4 0x77 96f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_5 0x78 97f1c0a02fSMark Brown #define WM8903_INTERRUPT_STATUS_1 0x79 98f1c0a02fSMark Brown #define WM8903_INTERRUPT_STATUS_1_MASK 0x7A 99f1c0a02fSMark Brown #define WM8903_INTERRUPT_POLARITY_1 0x7B 100f1c0a02fSMark Brown #define WM8903_INTERRUPT_CONTROL 0x7E 101f1c0a02fSMark Brown #define WM8903_CLOCK_RATE_TEST_4 0xA4 102f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC 103f1c0a02fSMark Brown 104f1c0a02fSMark Brown #define WM8903_REGISTER_COUNT 75 105f1c0a02fSMark Brown #define WM8903_MAX_REGISTER 0xAC 106f1c0a02fSMark Brown 107f1c0a02fSMark Brown /* 108f1c0a02fSMark Brown * Field Definitions. 109f1c0a02fSMark Brown */ 110f1c0a02fSMark Brown 111f1c0a02fSMark Brown /* 112f1c0a02fSMark Brown * R0 (0x00) - SW Reset and ID 113f1c0a02fSMark Brown */ 114f1c0a02fSMark Brown #define WM8903_SW_RESET_DEV_ID1_MASK 0xFFFF /* SW_RESET_DEV_ID1 - [15:0] */ 115f1c0a02fSMark Brown #define WM8903_SW_RESET_DEV_ID1_SHIFT 0 /* SW_RESET_DEV_ID1 - [15:0] */ 116f1c0a02fSMark Brown #define WM8903_SW_RESET_DEV_ID1_WIDTH 16 /* SW_RESET_DEV_ID1 - [15:0] */ 117f1c0a02fSMark Brown 118f1c0a02fSMark Brown /* 119f1c0a02fSMark Brown * R1 (0x01) - Revision Number 120f1c0a02fSMark Brown */ 121f1c0a02fSMark Brown #define WM8903_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 122f1c0a02fSMark Brown #define WM8903_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 123f1c0a02fSMark Brown #define WM8903_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 124f1c0a02fSMark Brown 125f1c0a02fSMark Brown /* 126f1c0a02fSMark Brown * R4 (0x04) - Bias Control 0 127f1c0a02fSMark Brown */ 128f1c0a02fSMark Brown #define WM8903_POBCTRL 0x0010 /* POBCTRL */ 129f1c0a02fSMark Brown #define WM8903_POBCTRL_MASK 0x0010 /* POBCTRL */ 130f1c0a02fSMark Brown #define WM8903_POBCTRL_SHIFT 4 /* POBCTRL */ 131f1c0a02fSMark Brown #define WM8903_POBCTRL_WIDTH 1 /* POBCTRL */ 132f1c0a02fSMark Brown #define WM8903_ISEL_MASK 0x000C /* ISEL - [3:2] */ 133f1c0a02fSMark Brown #define WM8903_ISEL_SHIFT 2 /* ISEL - [3:2] */ 134f1c0a02fSMark Brown #define WM8903_ISEL_WIDTH 2 /* ISEL - [3:2] */ 135f1c0a02fSMark Brown #define WM8903_STARTUP_BIAS_ENA 0x0002 /* STARTUP_BIAS_ENA */ 136f1c0a02fSMark Brown #define WM8903_STARTUP_BIAS_ENA_MASK 0x0002 /* STARTUP_BIAS_ENA */ 137f1c0a02fSMark Brown #define WM8903_STARTUP_BIAS_ENA_SHIFT 1 /* STARTUP_BIAS_ENA */ 138f1c0a02fSMark Brown #define WM8903_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 139f1c0a02fSMark Brown #define WM8903_BIAS_ENA 0x0001 /* BIAS_ENA */ 140f1c0a02fSMark Brown #define WM8903_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ 141f1c0a02fSMark Brown #define WM8903_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ 142f1c0a02fSMark Brown #define WM8903_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 143f1c0a02fSMark Brown 144f1c0a02fSMark Brown /* 145f1c0a02fSMark Brown * R5 (0x05) - VMID Control 0 146f1c0a02fSMark Brown */ 147f1c0a02fSMark Brown #define WM8903_VMID_TIE_ENA 0x0080 /* VMID_TIE_ENA */ 148f1c0a02fSMark Brown #define WM8903_VMID_TIE_ENA_MASK 0x0080 /* VMID_TIE_ENA */ 149f1c0a02fSMark Brown #define WM8903_VMID_TIE_ENA_SHIFT 7 /* VMID_TIE_ENA */ 150f1c0a02fSMark Brown #define WM8903_VMID_TIE_ENA_WIDTH 1 /* VMID_TIE_ENA */ 151f1c0a02fSMark Brown #define WM8903_BUFIO_ENA 0x0040 /* BUFIO_ENA */ 152f1c0a02fSMark Brown #define WM8903_BUFIO_ENA_MASK 0x0040 /* BUFIO_ENA */ 153f1c0a02fSMark Brown #define WM8903_BUFIO_ENA_SHIFT 6 /* BUFIO_ENA */ 154f1c0a02fSMark Brown #define WM8903_BUFIO_ENA_WIDTH 1 /* BUFIO_ENA */ 155f1c0a02fSMark Brown #define WM8903_VMID_IO_ENA 0x0020 /* VMID_IO_ENA */ 156f1c0a02fSMark Brown #define WM8903_VMID_IO_ENA_MASK 0x0020 /* VMID_IO_ENA */ 157f1c0a02fSMark Brown #define WM8903_VMID_IO_ENA_SHIFT 5 /* VMID_IO_ENA */ 158f1c0a02fSMark Brown #define WM8903_VMID_IO_ENA_WIDTH 1 /* VMID_IO_ENA */ 159f1c0a02fSMark Brown #define WM8903_VMID_SOFT_MASK 0x0018 /* VMID_SOFT - [4:3] */ 160f1c0a02fSMark Brown #define WM8903_VMID_SOFT_SHIFT 3 /* VMID_SOFT - [4:3] */ 161f1c0a02fSMark Brown #define WM8903_VMID_SOFT_WIDTH 2 /* VMID_SOFT - [4:3] */ 162f1c0a02fSMark Brown #define WM8903_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */ 163f1c0a02fSMark Brown #define WM8903_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */ 164f1c0a02fSMark Brown #define WM8903_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */ 165f1c0a02fSMark Brown #define WM8903_VMID_BUF_ENA 0x0001 /* VMID_BUF_ENA */ 166f1c0a02fSMark Brown #define WM8903_VMID_BUF_ENA_MASK 0x0001 /* VMID_BUF_ENA */ 167f1c0a02fSMark Brown #define WM8903_VMID_BUF_ENA_SHIFT 0 /* VMID_BUF_ENA */ 168f1c0a02fSMark Brown #define WM8903_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 169f1c0a02fSMark Brown 170f1c0a02fSMark Brown #define WM8903_VMID_RES_50K 2 171ebb6ad73SAxel Lin #define WM8903_VMID_RES_250K 4 1728ceed344SMark Brown #define WM8903_VMID_RES_5K 6 173f1c0a02fSMark Brown 174f1c0a02fSMark Brown /* 175f1c0a02fSMark Brown * R8 (0x08) - Analogue DAC 0 176f1c0a02fSMark Brown */ 177f1c0a02fSMark Brown #define WM8903_DACBIAS_SEL_MASK 0x0018 /* DACBIAS_SEL - [4:3] */ 178f1c0a02fSMark Brown #define WM8903_DACBIAS_SEL_SHIFT 3 /* DACBIAS_SEL - [4:3] */ 179f1c0a02fSMark Brown #define WM8903_DACBIAS_SEL_WIDTH 2 /* DACBIAS_SEL - [4:3] */ 180f1c0a02fSMark Brown #define WM8903_DACVMID_BIAS_SEL_MASK 0x0006 /* DACVMID_BIAS_SEL - [2:1] */ 181f1c0a02fSMark Brown #define WM8903_DACVMID_BIAS_SEL_SHIFT 1 /* DACVMID_BIAS_SEL - [2:1] */ 182f1c0a02fSMark Brown #define WM8903_DACVMID_BIAS_SEL_WIDTH 2 /* DACVMID_BIAS_SEL - [2:1] */ 183f1c0a02fSMark Brown 184f1c0a02fSMark Brown /* 185f1c0a02fSMark Brown * R10 (0x0A) - Analogue ADC 0 186f1c0a02fSMark Brown */ 187f1c0a02fSMark Brown #define WM8903_ADC_OSR128 0x0001 /* ADC_OSR128 */ 188f1c0a02fSMark Brown #define WM8903_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */ 189f1c0a02fSMark Brown #define WM8903_ADC_OSR128_SHIFT 0 /* ADC_OSR128 */ 190f1c0a02fSMark Brown #define WM8903_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 191f1c0a02fSMark Brown 192f1c0a02fSMark Brown /* 193f1c0a02fSMark Brown * R12 (0x0C) - Power Management 0 194f1c0a02fSMark Brown */ 195f1c0a02fSMark Brown #define WM8903_INL_ENA 0x0002 /* INL_ENA */ 196f1c0a02fSMark Brown #define WM8903_INL_ENA_MASK 0x0002 /* INL_ENA */ 197f1c0a02fSMark Brown #define WM8903_INL_ENA_SHIFT 1 /* INL_ENA */ 198f1c0a02fSMark Brown #define WM8903_INL_ENA_WIDTH 1 /* INL_ENA */ 199f1c0a02fSMark Brown #define WM8903_INR_ENA 0x0001 /* INR_ENA */ 200f1c0a02fSMark Brown #define WM8903_INR_ENA_MASK 0x0001 /* INR_ENA */ 201f1c0a02fSMark Brown #define WM8903_INR_ENA_SHIFT 0 /* INR_ENA */ 202f1c0a02fSMark Brown #define WM8903_INR_ENA_WIDTH 1 /* INR_ENA */ 203f1c0a02fSMark Brown 204f1c0a02fSMark Brown /* 205f1c0a02fSMark Brown * R13 (0x0D) - Power Management 1 206f1c0a02fSMark Brown */ 207f1c0a02fSMark Brown #define WM8903_MIXOUTL_ENA 0x0002 /* MIXOUTL_ENA */ 208f1c0a02fSMark Brown #define WM8903_MIXOUTL_ENA_MASK 0x0002 /* MIXOUTL_ENA */ 209f1c0a02fSMark Brown #define WM8903_MIXOUTL_ENA_SHIFT 1 /* MIXOUTL_ENA */ 210f1c0a02fSMark Brown #define WM8903_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */ 211f1c0a02fSMark Brown #define WM8903_MIXOUTR_ENA 0x0001 /* MIXOUTR_ENA */ 212f1c0a02fSMark Brown #define WM8903_MIXOUTR_ENA_MASK 0x0001 /* MIXOUTR_ENA */ 213f1c0a02fSMark Brown #define WM8903_MIXOUTR_ENA_SHIFT 0 /* MIXOUTR_ENA */ 214f1c0a02fSMark Brown #define WM8903_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */ 215f1c0a02fSMark Brown 216f1c0a02fSMark Brown /* 217f1c0a02fSMark Brown * R14 (0x0E) - Power Management 2 218f1c0a02fSMark Brown */ 219f1c0a02fSMark Brown #define WM8903_HPL_PGA_ENA 0x0002 /* HPL_PGA_ENA */ 220f1c0a02fSMark Brown #define WM8903_HPL_PGA_ENA_MASK 0x0002 /* HPL_PGA_ENA */ 221f1c0a02fSMark Brown #define WM8903_HPL_PGA_ENA_SHIFT 1 /* HPL_PGA_ENA */ 222f1c0a02fSMark Brown #define WM8903_HPL_PGA_ENA_WIDTH 1 /* HPL_PGA_ENA */ 223f1c0a02fSMark Brown #define WM8903_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */ 224f1c0a02fSMark Brown #define WM8903_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */ 225f1c0a02fSMark Brown #define WM8903_HPR_PGA_ENA_SHIFT 0 /* HPR_PGA_ENA */ 226f1c0a02fSMark Brown #define WM8903_HPR_PGA_ENA_WIDTH 1 /* HPR_PGA_ENA */ 227f1c0a02fSMark Brown 228f1c0a02fSMark Brown /* 229f1c0a02fSMark Brown * R15 (0x0F) - Power Management 3 230f1c0a02fSMark Brown */ 231f1c0a02fSMark Brown #define WM8903_LINEOUTL_PGA_ENA 0x0002 /* LINEOUTL_PGA_ENA */ 232f1c0a02fSMark Brown #define WM8903_LINEOUTL_PGA_ENA_MASK 0x0002 /* LINEOUTL_PGA_ENA */ 233f1c0a02fSMark Brown #define WM8903_LINEOUTL_PGA_ENA_SHIFT 1 /* LINEOUTL_PGA_ENA */ 234f1c0a02fSMark Brown #define WM8903_LINEOUTL_PGA_ENA_WIDTH 1 /* LINEOUTL_PGA_ENA */ 235f1c0a02fSMark Brown #define WM8903_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */ 236f1c0a02fSMark Brown #define WM8903_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */ 237f1c0a02fSMark Brown #define WM8903_LINEOUTR_PGA_ENA_SHIFT 0 /* LINEOUTR_PGA_ENA */ 238f1c0a02fSMark Brown #define WM8903_LINEOUTR_PGA_ENA_WIDTH 1 /* LINEOUTR_PGA_ENA */ 239f1c0a02fSMark Brown 240f1c0a02fSMark Brown /* 241f1c0a02fSMark Brown * R16 (0x10) - Power Management 4 242f1c0a02fSMark Brown */ 243f1c0a02fSMark Brown #define WM8903_MIXSPKL_ENA 0x0002 /* MIXSPKL_ENA */ 244f1c0a02fSMark Brown #define WM8903_MIXSPKL_ENA_MASK 0x0002 /* MIXSPKL_ENA */ 245f1c0a02fSMark Brown #define WM8903_MIXSPKL_ENA_SHIFT 1 /* MIXSPKL_ENA */ 246f1c0a02fSMark Brown #define WM8903_MIXSPKL_ENA_WIDTH 1 /* MIXSPKL_ENA */ 247f1c0a02fSMark Brown #define WM8903_MIXSPKR_ENA 0x0001 /* MIXSPKR_ENA */ 248f1c0a02fSMark Brown #define WM8903_MIXSPKR_ENA_MASK 0x0001 /* MIXSPKR_ENA */ 249f1c0a02fSMark Brown #define WM8903_MIXSPKR_ENA_SHIFT 0 /* MIXSPKR_ENA */ 250f1c0a02fSMark Brown #define WM8903_MIXSPKR_ENA_WIDTH 1 /* MIXSPKR_ENA */ 251f1c0a02fSMark Brown 252f1c0a02fSMark Brown /* 253f1c0a02fSMark Brown * R17 (0x11) - Power Management 5 254f1c0a02fSMark Brown */ 255f1c0a02fSMark Brown #define WM8903_SPKL_ENA 0x0002 /* SPKL_ENA */ 256f1c0a02fSMark Brown #define WM8903_SPKL_ENA_MASK 0x0002 /* SPKL_ENA */ 257f1c0a02fSMark Brown #define WM8903_SPKL_ENA_SHIFT 1 /* SPKL_ENA */ 258f1c0a02fSMark Brown #define WM8903_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ 259f1c0a02fSMark Brown #define WM8903_SPKR_ENA 0x0001 /* SPKR_ENA */ 260f1c0a02fSMark Brown #define WM8903_SPKR_ENA_MASK 0x0001 /* SPKR_ENA */ 261f1c0a02fSMark Brown #define WM8903_SPKR_ENA_SHIFT 0 /* SPKR_ENA */ 262f1c0a02fSMark Brown #define WM8903_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ 263f1c0a02fSMark Brown 264f1c0a02fSMark Brown /* 265f1c0a02fSMark Brown * R18 (0x12) - Power Management 6 266f1c0a02fSMark Brown */ 267f1c0a02fSMark Brown #define WM8903_DACL_ENA 0x0008 /* DACL_ENA */ 268f1c0a02fSMark Brown #define WM8903_DACL_ENA_MASK 0x0008 /* DACL_ENA */ 269f1c0a02fSMark Brown #define WM8903_DACL_ENA_SHIFT 3 /* DACL_ENA */ 270f1c0a02fSMark Brown #define WM8903_DACL_ENA_WIDTH 1 /* DACL_ENA */ 271f1c0a02fSMark Brown #define WM8903_DACR_ENA 0x0004 /* DACR_ENA */ 272f1c0a02fSMark Brown #define WM8903_DACR_ENA_MASK 0x0004 /* DACR_ENA */ 273f1c0a02fSMark Brown #define WM8903_DACR_ENA_SHIFT 2 /* DACR_ENA */ 274f1c0a02fSMark Brown #define WM8903_DACR_ENA_WIDTH 1 /* DACR_ENA */ 275f1c0a02fSMark Brown #define WM8903_ADCL_ENA 0x0002 /* ADCL_ENA */ 276f1c0a02fSMark Brown #define WM8903_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 277f1c0a02fSMark Brown #define WM8903_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 278f1c0a02fSMark Brown #define WM8903_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 279f1c0a02fSMark Brown #define WM8903_ADCR_ENA 0x0001 /* ADCR_ENA */ 280f1c0a02fSMark Brown #define WM8903_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 281f1c0a02fSMark Brown #define WM8903_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 282f1c0a02fSMark Brown #define WM8903_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 283f1c0a02fSMark Brown 284f1c0a02fSMark Brown /* 285f1c0a02fSMark Brown * R20 (0x14) - Clock Rates 0 286f1c0a02fSMark Brown */ 287f1c0a02fSMark Brown #define WM8903_MCLKDIV2 0x0001 /* MCLKDIV2 */ 288f1c0a02fSMark Brown #define WM8903_MCLKDIV2_MASK 0x0001 /* MCLKDIV2 */ 289f1c0a02fSMark Brown #define WM8903_MCLKDIV2_SHIFT 0 /* MCLKDIV2 */ 290f1c0a02fSMark Brown #define WM8903_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */ 291f1c0a02fSMark Brown 292f1c0a02fSMark Brown /* 293f1c0a02fSMark Brown * R21 (0x15) - Clock Rates 1 294f1c0a02fSMark Brown */ 295f1c0a02fSMark Brown #define WM8903_CLK_SYS_RATE_MASK 0x3C00 /* CLK_SYS_RATE - [13:10] */ 296f1c0a02fSMark Brown #define WM8903_CLK_SYS_RATE_SHIFT 10 /* CLK_SYS_RATE - [13:10] */ 297f1c0a02fSMark Brown #define WM8903_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [13:10] */ 298f1c0a02fSMark Brown #define WM8903_CLK_SYS_MODE_MASK 0x0300 /* CLK_SYS_MODE - [9:8] */ 299f1c0a02fSMark Brown #define WM8903_CLK_SYS_MODE_SHIFT 8 /* CLK_SYS_MODE - [9:8] */ 300f1c0a02fSMark Brown #define WM8903_CLK_SYS_MODE_WIDTH 2 /* CLK_SYS_MODE - [9:8] */ 301f1c0a02fSMark Brown #define WM8903_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */ 302f1c0a02fSMark Brown #define WM8903_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */ 303f1c0a02fSMark Brown #define WM8903_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */ 304f1c0a02fSMark Brown 305f1c0a02fSMark Brown /* 306f1c0a02fSMark Brown * R22 (0x16) - Clock Rates 2 307f1c0a02fSMark Brown */ 308f1c0a02fSMark Brown #define WM8903_CLK_SYS_ENA 0x0004 /* CLK_SYS_ENA */ 309f1c0a02fSMark Brown #define WM8903_CLK_SYS_ENA_MASK 0x0004 /* CLK_SYS_ENA */ 310f1c0a02fSMark Brown #define WM8903_CLK_SYS_ENA_SHIFT 2 /* CLK_SYS_ENA */ 311f1c0a02fSMark Brown #define WM8903_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ 312f1c0a02fSMark Brown #define WM8903_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */ 313f1c0a02fSMark Brown #define WM8903_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */ 314f1c0a02fSMark Brown #define WM8903_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */ 315f1c0a02fSMark Brown #define WM8903_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ 316f1c0a02fSMark Brown #define WM8903_TO_ENA 0x0001 /* TO_ENA */ 317f1c0a02fSMark Brown #define WM8903_TO_ENA_MASK 0x0001 /* TO_ENA */ 318f1c0a02fSMark Brown #define WM8903_TO_ENA_SHIFT 0 /* TO_ENA */ 319f1c0a02fSMark Brown #define WM8903_TO_ENA_WIDTH 1 /* TO_ENA */ 320f1c0a02fSMark Brown 321f1c0a02fSMark Brown /* 322f1c0a02fSMark Brown * R24 (0x18) - Audio Interface 0 323f1c0a02fSMark Brown */ 324f1c0a02fSMark Brown #define WM8903_DACL_DATINV 0x1000 /* DACL_DATINV */ 325f1c0a02fSMark Brown #define WM8903_DACL_DATINV_MASK 0x1000 /* DACL_DATINV */ 326f1c0a02fSMark Brown #define WM8903_DACL_DATINV_SHIFT 12 /* DACL_DATINV */ 327f1c0a02fSMark Brown #define WM8903_DACL_DATINV_WIDTH 1 /* DACL_DATINV */ 328f1c0a02fSMark Brown #define WM8903_DACR_DATINV 0x0800 /* DACR_DATINV */ 329f1c0a02fSMark Brown #define WM8903_DACR_DATINV_MASK 0x0800 /* DACR_DATINV */ 330f1c0a02fSMark Brown #define WM8903_DACR_DATINV_SHIFT 11 /* DACR_DATINV */ 331f1c0a02fSMark Brown #define WM8903_DACR_DATINV_WIDTH 1 /* DACR_DATINV */ 332f1c0a02fSMark Brown #define WM8903_DAC_BOOST_MASK 0x0600 /* DAC_BOOST - [10:9] */ 333f1c0a02fSMark Brown #define WM8903_DAC_BOOST_SHIFT 9 /* DAC_BOOST - [10:9] */ 334f1c0a02fSMark Brown #define WM8903_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [10:9] */ 335f1c0a02fSMark Brown #define WM8903_LOOPBACK 0x0100 /* LOOPBACK */ 336f1c0a02fSMark Brown #define WM8903_LOOPBACK_MASK 0x0100 /* LOOPBACK */ 337f1c0a02fSMark Brown #define WM8903_LOOPBACK_SHIFT 8 /* LOOPBACK */ 338f1c0a02fSMark Brown #define WM8903_LOOPBACK_WIDTH 1 /* LOOPBACK */ 339f1c0a02fSMark Brown #define WM8903_AIFADCL_SRC 0x0080 /* AIFADCL_SRC */ 340f1c0a02fSMark Brown #define WM8903_AIFADCL_SRC_MASK 0x0080 /* AIFADCL_SRC */ 341f1c0a02fSMark Brown #define WM8903_AIFADCL_SRC_SHIFT 7 /* AIFADCL_SRC */ 342f1c0a02fSMark Brown #define WM8903_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */ 343f1c0a02fSMark Brown #define WM8903_AIFADCR_SRC 0x0040 /* AIFADCR_SRC */ 344f1c0a02fSMark Brown #define WM8903_AIFADCR_SRC_MASK 0x0040 /* AIFADCR_SRC */ 345f1c0a02fSMark Brown #define WM8903_AIFADCR_SRC_SHIFT 6 /* AIFADCR_SRC */ 346f1c0a02fSMark Brown #define WM8903_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */ 347f1c0a02fSMark Brown #define WM8903_AIFDACL_SRC 0x0020 /* AIFDACL_SRC */ 348f1c0a02fSMark Brown #define WM8903_AIFDACL_SRC_MASK 0x0020 /* AIFDACL_SRC */ 349f1c0a02fSMark Brown #define WM8903_AIFDACL_SRC_SHIFT 5 /* AIFDACL_SRC */ 350f1c0a02fSMark Brown #define WM8903_AIFDACL_SRC_WIDTH 1 /* AIFDACL_SRC */ 351f1c0a02fSMark Brown #define WM8903_AIFDACR_SRC 0x0010 /* AIFDACR_SRC */ 352f1c0a02fSMark Brown #define WM8903_AIFDACR_SRC_MASK 0x0010 /* AIFDACR_SRC */ 353f1c0a02fSMark Brown #define WM8903_AIFDACR_SRC_SHIFT 4 /* AIFDACR_SRC */ 354f1c0a02fSMark Brown #define WM8903_AIFDACR_SRC_WIDTH 1 /* AIFDACR_SRC */ 355f1c0a02fSMark Brown #define WM8903_ADC_COMP 0x0008 /* ADC_COMP */ 356f1c0a02fSMark Brown #define WM8903_ADC_COMP_MASK 0x0008 /* ADC_COMP */ 357f1c0a02fSMark Brown #define WM8903_ADC_COMP_SHIFT 3 /* ADC_COMP */ 358f1c0a02fSMark Brown #define WM8903_ADC_COMP_WIDTH 1 /* ADC_COMP */ 359f1c0a02fSMark Brown #define WM8903_ADC_COMPMODE 0x0004 /* ADC_COMPMODE */ 360f1c0a02fSMark Brown #define WM8903_ADC_COMPMODE_MASK 0x0004 /* ADC_COMPMODE */ 361f1c0a02fSMark Brown #define WM8903_ADC_COMPMODE_SHIFT 2 /* ADC_COMPMODE */ 362f1c0a02fSMark Brown #define WM8903_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */ 363f1c0a02fSMark Brown #define WM8903_DAC_COMP 0x0002 /* DAC_COMP */ 364f1c0a02fSMark Brown #define WM8903_DAC_COMP_MASK 0x0002 /* DAC_COMP */ 365f1c0a02fSMark Brown #define WM8903_DAC_COMP_SHIFT 1 /* DAC_COMP */ 366f1c0a02fSMark Brown #define WM8903_DAC_COMP_WIDTH 1 /* DAC_COMP */ 367f1c0a02fSMark Brown #define WM8903_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */ 368f1c0a02fSMark Brown #define WM8903_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */ 369f1c0a02fSMark Brown #define WM8903_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */ 370f1c0a02fSMark Brown #define WM8903_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ 371f1c0a02fSMark Brown 372f1c0a02fSMark Brown /* 373f1c0a02fSMark Brown * R25 (0x19) - Audio Interface 1 374f1c0a02fSMark Brown */ 375f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ 376f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */ 377f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */ 378f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */ 379f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ 380f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */ 381f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */ 382f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */ 383f1c0a02fSMark Brown #define WM8903_AIFADC_TDM 0x0800 /* AIFADC_TDM */ 384f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_MASK 0x0800 /* AIFADC_TDM */ 385f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_SHIFT 11 /* AIFADC_TDM */ 386f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */ 387f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_CHAN 0x0400 /* AIFADC_TDM_CHAN */ 388f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_CHAN_MASK 0x0400 /* AIFADC_TDM_CHAN */ 389f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_CHAN_SHIFT 10 /* AIFADC_TDM_CHAN */ 390f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */ 391f1c0a02fSMark Brown #define WM8903_LRCLK_DIR 0x0200 /* LRCLK_DIR */ 392f1c0a02fSMark Brown #define WM8903_LRCLK_DIR_MASK 0x0200 /* LRCLK_DIR */ 393f1c0a02fSMark Brown #define WM8903_LRCLK_DIR_SHIFT 9 /* LRCLK_DIR */ 394f1c0a02fSMark Brown #define WM8903_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */ 395f1c0a02fSMark Brown #define WM8903_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */ 396f1c0a02fSMark Brown #define WM8903_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */ 397f1c0a02fSMark Brown #define WM8903_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */ 398f1c0a02fSMark Brown #define WM8903_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */ 399f1c0a02fSMark Brown #define WM8903_BCLK_DIR 0x0040 /* BCLK_DIR */ 400f1c0a02fSMark Brown #define WM8903_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */ 401f1c0a02fSMark Brown #define WM8903_BCLK_DIR_SHIFT 6 /* BCLK_DIR */ 402f1c0a02fSMark Brown #define WM8903_BCLK_DIR_WIDTH 1 /* BCLK_DIR */ 403f1c0a02fSMark Brown #define WM8903_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */ 404f1c0a02fSMark Brown #define WM8903_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */ 405f1c0a02fSMark Brown #define WM8903_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */ 406f1c0a02fSMark Brown #define WM8903_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */ 407f1c0a02fSMark Brown #define WM8903_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */ 408f1c0a02fSMark Brown #define WM8903_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */ 409f1c0a02fSMark Brown #define WM8903_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */ 410f1c0a02fSMark Brown #define WM8903_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */ 411f1c0a02fSMark Brown #define WM8903_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */ 412f1c0a02fSMark Brown #define WM8903_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */ 413f1c0a02fSMark Brown 414f1c0a02fSMark Brown /* 415f1c0a02fSMark Brown * R26 (0x1A) - Audio Interface 2 416f1c0a02fSMark Brown */ 417f1c0a02fSMark Brown #define WM8903_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */ 418f1c0a02fSMark Brown #define WM8903_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */ 419f1c0a02fSMark Brown #define WM8903_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */ 420f1c0a02fSMark Brown 421f1c0a02fSMark Brown /* 422f1c0a02fSMark Brown * R27 (0x1B) - Audio Interface 3 423f1c0a02fSMark Brown */ 424f1c0a02fSMark Brown #define WM8903_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */ 425f1c0a02fSMark Brown #define WM8903_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */ 426f1c0a02fSMark Brown #define WM8903_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */ 427f1c0a02fSMark Brown 428f1c0a02fSMark Brown /* 429f1c0a02fSMark Brown * R30 (0x1E) - DAC Digital Volume Left 430f1c0a02fSMark Brown */ 431f1c0a02fSMark Brown #define WM8903_DACVU 0x0100 /* DACVU */ 432f1c0a02fSMark Brown #define WM8903_DACVU_MASK 0x0100 /* DACVU */ 433f1c0a02fSMark Brown #define WM8903_DACVU_SHIFT 8 /* DACVU */ 434f1c0a02fSMark Brown #define WM8903_DACVU_WIDTH 1 /* DACVU */ 435f1c0a02fSMark Brown #define WM8903_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ 436f1c0a02fSMark Brown #define WM8903_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */ 437f1c0a02fSMark Brown #define WM8903_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */ 438f1c0a02fSMark Brown 439f1c0a02fSMark Brown /* 440f1c0a02fSMark Brown * R31 (0x1F) - DAC Digital Volume Right 441f1c0a02fSMark Brown */ 442f1c0a02fSMark Brown #define WM8903_DACVU 0x0100 /* DACVU */ 443f1c0a02fSMark Brown #define WM8903_DACVU_MASK 0x0100 /* DACVU */ 444f1c0a02fSMark Brown #define WM8903_DACVU_SHIFT 8 /* DACVU */ 445f1c0a02fSMark Brown #define WM8903_DACVU_WIDTH 1 /* DACVU */ 446f1c0a02fSMark Brown #define WM8903_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ 447f1c0a02fSMark Brown #define WM8903_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */ 448f1c0a02fSMark Brown #define WM8903_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */ 449f1c0a02fSMark Brown 450f1c0a02fSMark Brown /* 451f1c0a02fSMark Brown * R32 (0x20) - DAC Digital 0 452f1c0a02fSMark Brown */ 453f1c0a02fSMark Brown #define WM8903_ADCL_DAC_SVOL_MASK 0x0F00 /* ADCL_DAC_SVOL - [11:8] */ 454f1c0a02fSMark Brown #define WM8903_ADCL_DAC_SVOL_SHIFT 8 /* ADCL_DAC_SVOL - [11:8] */ 455f1c0a02fSMark Brown #define WM8903_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [11:8] */ 456f1c0a02fSMark Brown #define WM8903_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ 457f1c0a02fSMark Brown #define WM8903_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ 458f1c0a02fSMark Brown #define WM8903_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ 459f1c0a02fSMark Brown #define WM8903_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ 460f1c0a02fSMark Brown #define WM8903_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ 461f1c0a02fSMark Brown #define WM8903_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ 462f1c0a02fSMark Brown #define WM8903_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */ 463f1c0a02fSMark Brown #define WM8903_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */ 464f1c0a02fSMark Brown #define WM8903_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */ 465f1c0a02fSMark Brown 466f1c0a02fSMark Brown /* 467f1c0a02fSMark Brown * R33 (0x21) - DAC Digital 1 468f1c0a02fSMark Brown */ 469f1c0a02fSMark Brown #define WM8903_DAC_MONO 0x1000 /* DAC_MONO */ 470f1c0a02fSMark Brown #define WM8903_DAC_MONO_MASK 0x1000 /* DAC_MONO */ 471f1c0a02fSMark Brown #define WM8903_DAC_MONO_SHIFT 12 /* DAC_MONO */ 472f1c0a02fSMark Brown #define WM8903_DAC_MONO_WIDTH 1 /* DAC_MONO */ 473f1c0a02fSMark Brown #define WM8903_DAC_SB_FILT 0x0800 /* DAC_SB_FILT */ 474f1c0a02fSMark Brown #define WM8903_DAC_SB_FILT_MASK 0x0800 /* DAC_SB_FILT */ 475f1c0a02fSMark Brown #define WM8903_DAC_SB_FILT_SHIFT 11 /* DAC_SB_FILT */ 476f1c0a02fSMark Brown #define WM8903_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */ 477f1c0a02fSMark Brown #define WM8903_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */ 478f1c0a02fSMark Brown #define WM8903_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */ 479f1c0a02fSMark Brown #define WM8903_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */ 480f1c0a02fSMark Brown #define WM8903_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 481f1c0a02fSMark Brown #define WM8903_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */ 482f1c0a02fSMark Brown #define WM8903_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */ 483f1c0a02fSMark Brown #define WM8903_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */ 484f1c0a02fSMark Brown #define WM8903_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */ 485f1c0a02fSMark Brown #define WM8903_DAC_MUTE 0x0008 /* DAC_MUTE */ 486f1c0a02fSMark Brown #define WM8903_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ 487f1c0a02fSMark Brown #define WM8903_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ 488f1c0a02fSMark Brown #define WM8903_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ 489f1c0a02fSMark Brown #define WM8903_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 490f1c0a02fSMark Brown #define WM8903_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 491f1c0a02fSMark Brown #define WM8903_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 492f1c0a02fSMark Brown 493f1c0a02fSMark Brown /* 494f1c0a02fSMark Brown * R36 (0x24) - ADC Digital Volume Left 495f1c0a02fSMark Brown */ 496f1c0a02fSMark Brown #define WM8903_ADCVU 0x0100 /* ADCVU */ 497f1c0a02fSMark Brown #define WM8903_ADCVU_MASK 0x0100 /* ADCVU */ 498f1c0a02fSMark Brown #define WM8903_ADCVU_SHIFT 8 /* ADCVU */ 499f1c0a02fSMark Brown #define WM8903_ADCVU_WIDTH 1 /* ADCVU */ 500f1c0a02fSMark Brown #define WM8903_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ 501f1c0a02fSMark Brown #define WM8903_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */ 502f1c0a02fSMark Brown #define WM8903_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */ 503f1c0a02fSMark Brown 504f1c0a02fSMark Brown /* 505f1c0a02fSMark Brown * R37 (0x25) - ADC Digital Volume Right 506f1c0a02fSMark Brown */ 507f1c0a02fSMark Brown #define WM8903_ADCVU 0x0100 /* ADCVU */ 508f1c0a02fSMark Brown #define WM8903_ADCVU_MASK 0x0100 /* ADCVU */ 509f1c0a02fSMark Brown #define WM8903_ADCVU_SHIFT 8 /* ADCVU */ 510f1c0a02fSMark Brown #define WM8903_ADCVU_WIDTH 1 /* ADCVU */ 511f1c0a02fSMark Brown #define WM8903_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ 512f1c0a02fSMark Brown #define WM8903_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */ 513f1c0a02fSMark Brown #define WM8903_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */ 514f1c0a02fSMark Brown 515f1c0a02fSMark Brown /* 516f1c0a02fSMark Brown * R38 (0x26) - ADC Digital 0 517f1c0a02fSMark Brown */ 518f1c0a02fSMark Brown #define WM8903_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */ 519f1c0a02fSMark Brown #define WM8903_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */ 520f1c0a02fSMark Brown #define WM8903_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */ 521f1c0a02fSMark Brown #define WM8903_ADC_HPF_ENA 0x0010 /* ADC_HPF_ENA */ 522f1c0a02fSMark Brown #define WM8903_ADC_HPF_ENA_MASK 0x0010 /* ADC_HPF_ENA */ 523f1c0a02fSMark Brown #define WM8903_ADC_HPF_ENA_SHIFT 4 /* ADC_HPF_ENA */ 524f1c0a02fSMark Brown #define WM8903_ADC_HPF_ENA_WIDTH 1 /* ADC_HPF_ENA */ 525f1c0a02fSMark Brown #define WM8903_ADCL_DATINV 0x0002 /* ADCL_DATINV */ 526f1c0a02fSMark Brown #define WM8903_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */ 527f1c0a02fSMark Brown #define WM8903_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */ 528f1c0a02fSMark Brown #define WM8903_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */ 529f1c0a02fSMark Brown #define WM8903_ADCR_DATINV 0x0001 /* ADCR_DATINV */ 530f1c0a02fSMark Brown #define WM8903_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */ 531f1c0a02fSMark Brown #define WM8903_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */ 532f1c0a02fSMark Brown #define WM8903_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */ 533f1c0a02fSMark Brown 534f1c0a02fSMark Brown /* 535f1c0a02fSMark Brown * R39 (0x27) - Digital Microphone 0 536f1c0a02fSMark Brown */ 537f1c0a02fSMark Brown #define WM8903_DIGMIC_MODE_SEL 0x0100 /* DIGMIC_MODE_SEL */ 538f1c0a02fSMark Brown #define WM8903_DIGMIC_MODE_SEL_MASK 0x0100 /* DIGMIC_MODE_SEL */ 539f1c0a02fSMark Brown #define WM8903_DIGMIC_MODE_SEL_SHIFT 8 /* DIGMIC_MODE_SEL */ 540f1c0a02fSMark Brown #define WM8903_DIGMIC_MODE_SEL_WIDTH 1 /* DIGMIC_MODE_SEL */ 541f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_L_MASK 0x00C0 /* DIGMIC_CLK_SEL_L - [7:6] */ 542f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_L_SHIFT 6 /* DIGMIC_CLK_SEL_L - [7:6] */ 543f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_L_WIDTH 2 /* DIGMIC_CLK_SEL_L - [7:6] */ 544f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_R_MASK 0x0030 /* DIGMIC_CLK_SEL_R - [5:4] */ 545f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_R_SHIFT 4 /* DIGMIC_CLK_SEL_R - [5:4] */ 546f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_R_WIDTH 2 /* DIGMIC_CLK_SEL_R - [5:4] */ 547f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_RT_MASK 0x000C /* DIGMIC_CLK_SEL_RT - [3:2] */ 548f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_RT_SHIFT 2 /* DIGMIC_CLK_SEL_RT - [3:2] */ 549f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_RT_WIDTH 2 /* DIGMIC_CLK_SEL_RT - [3:2] */ 550f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_MASK 0x0003 /* DIGMIC_CLK_SEL - [1:0] */ 551f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_SHIFT 0 /* DIGMIC_CLK_SEL - [1:0] */ 552f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_WIDTH 2 /* DIGMIC_CLK_SEL - [1:0] */ 553f1c0a02fSMark Brown 554f1c0a02fSMark Brown /* 555f1c0a02fSMark Brown * R40 (0x28) - DRC 0 556f1c0a02fSMark Brown */ 557f1c0a02fSMark Brown #define WM8903_DRC_ENA 0x8000 /* DRC_ENA */ 558f1c0a02fSMark Brown #define WM8903_DRC_ENA_MASK 0x8000 /* DRC_ENA */ 559f1c0a02fSMark Brown #define WM8903_DRC_ENA_SHIFT 15 /* DRC_ENA */ 560f1c0a02fSMark Brown #define WM8903_DRC_ENA_WIDTH 1 /* DRC_ENA */ 561f1c0a02fSMark Brown #define WM8903_DRC_THRESH_HYST_MASK 0x1800 /* DRC_THRESH_HYST - [12:11] */ 562f1c0a02fSMark Brown #define WM8903_DRC_THRESH_HYST_SHIFT 11 /* DRC_THRESH_HYST - [12:11] */ 563f1c0a02fSMark Brown #define WM8903_DRC_THRESH_HYST_WIDTH 2 /* DRC_THRESH_HYST - [12:11] */ 564f1c0a02fSMark Brown #define WM8903_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */ 565f1c0a02fSMark Brown #define WM8903_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */ 566f1c0a02fSMark Brown #define WM8903_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */ 567f1c0a02fSMark Brown #define WM8903_DRC_FF_DELAY 0x0020 /* DRC_FF_DELAY */ 568f1c0a02fSMark Brown #define WM8903_DRC_FF_DELAY_MASK 0x0020 /* DRC_FF_DELAY */ 569f1c0a02fSMark Brown #define WM8903_DRC_FF_DELAY_SHIFT 5 /* DRC_FF_DELAY */ 570f1c0a02fSMark Brown #define WM8903_DRC_FF_DELAY_WIDTH 1 /* DRC_FF_DELAY */ 571f1c0a02fSMark Brown #define WM8903_DRC_SMOOTH_ENA 0x0008 /* DRC_SMOOTH_ENA */ 572f1c0a02fSMark Brown #define WM8903_DRC_SMOOTH_ENA_MASK 0x0008 /* DRC_SMOOTH_ENA */ 573f1c0a02fSMark Brown #define WM8903_DRC_SMOOTH_ENA_SHIFT 3 /* DRC_SMOOTH_ENA */ 574f1c0a02fSMark Brown #define WM8903_DRC_SMOOTH_ENA_WIDTH 1 /* DRC_SMOOTH_ENA */ 575f1c0a02fSMark Brown #define WM8903_DRC_QR_ENA 0x0004 /* DRC_QR_ENA */ 576f1c0a02fSMark Brown #define WM8903_DRC_QR_ENA_MASK 0x0004 /* DRC_QR_ENA */ 577f1c0a02fSMark Brown #define WM8903_DRC_QR_ENA_SHIFT 2 /* DRC_QR_ENA */ 578f1c0a02fSMark Brown #define WM8903_DRC_QR_ENA_WIDTH 1 /* DRC_QR_ENA */ 579f1c0a02fSMark Brown #define WM8903_DRC_ANTICLIP_ENA 0x0002 /* DRC_ANTICLIP_ENA */ 580f1c0a02fSMark Brown #define WM8903_DRC_ANTICLIP_ENA_MASK 0x0002 /* DRC_ANTICLIP_ENA */ 581f1c0a02fSMark Brown #define WM8903_DRC_ANTICLIP_ENA_SHIFT 1 /* DRC_ANTICLIP_ENA */ 582f1c0a02fSMark Brown #define WM8903_DRC_ANTICLIP_ENA_WIDTH 1 /* DRC_ANTICLIP_ENA */ 583f1c0a02fSMark Brown #define WM8903_DRC_HYST_ENA 0x0001 /* DRC_HYST_ENA */ 584f1c0a02fSMark Brown #define WM8903_DRC_HYST_ENA_MASK 0x0001 /* DRC_HYST_ENA */ 585f1c0a02fSMark Brown #define WM8903_DRC_HYST_ENA_SHIFT 0 /* DRC_HYST_ENA */ 586f1c0a02fSMark Brown #define WM8903_DRC_HYST_ENA_WIDTH 1 /* DRC_HYST_ENA */ 587f1c0a02fSMark Brown 588f1c0a02fSMark Brown /* 589f1c0a02fSMark Brown * R41 (0x29) - DRC 1 590f1c0a02fSMark Brown */ 591f1c0a02fSMark Brown #define WM8903_DRC_ATTACK_RATE_MASK 0xF000 /* DRC_ATTACK_RATE - [15:12] */ 592f1c0a02fSMark Brown #define WM8903_DRC_ATTACK_RATE_SHIFT 12 /* DRC_ATTACK_RATE - [15:12] */ 593f1c0a02fSMark Brown #define WM8903_DRC_ATTACK_RATE_WIDTH 4 /* DRC_ATTACK_RATE - [15:12] */ 594f1c0a02fSMark Brown #define WM8903_DRC_DECAY_RATE_MASK 0x0F00 /* DRC_DECAY_RATE - [11:8] */ 595f1c0a02fSMark Brown #define WM8903_DRC_DECAY_RATE_SHIFT 8 /* DRC_DECAY_RATE - [11:8] */ 596f1c0a02fSMark Brown #define WM8903_DRC_DECAY_RATE_WIDTH 4 /* DRC_DECAY_RATE - [11:8] */ 597f1c0a02fSMark Brown #define WM8903_DRC_THRESH_QR_MASK 0x00C0 /* DRC_THRESH_QR - [7:6] */ 598f1c0a02fSMark Brown #define WM8903_DRC_THRESH_QR_SHIFT 6 /* DRC_THRESH_QR - [7:6] */ 599f1c0a02fSMark Brown #define WM8903_DRC_THRESH_QR_WIDTH 2 /* DRC_THRESH_QR - [7:6] */ 600f1c0a02fSMark Brown #define WM8903_DRC_RATE_QR_MASK 0x0030 /* DRC_RATE_QR - [5:4] */ 601f1c0a02fSMark Brown #define WM8903_DRC_RATE_QR_SHIFT 4 /* DRC_RATE_QR - [5:4] */ 602f1c0a02fSMark Brown #define WM8903_DRC_RATE_QR_WIDTH 2 /* DRC_RATE_QR - [5:4] */ 603f1c0a02fSMark Brown #define WM8903_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */ 604f1c0a02fSMark Brown #define WM8903_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */ 605f1c0a02fSMark Brown #define WM8903_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */ 606f1c0a02fSMark Brown #define WM8903_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 607f1c0a02fSMark Brown #define WM8903_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 608f1c0a02fSMark Brown #define WM8903_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 609f1c0a02fSMark Brown 610f1c0a02fSMark Brown /* 611f1c0a02fSMark Brown * R42 (0x2A) - DRC 2 612f1c0a02fSMark Brown */ 613f1c0a02fSMark Brown #define WM8903_DRC_R0_SLOPE_COMP_MASK 0x0038 /* DRC_R0_SLOPE_COMP - [5:3] */ 614f1c0a02fSMark Brown #define WM8903_DRC_R0_SLOPE_COMP_SHIFT 3 /* DRC_R0_SLOPE_COMP - [5:3] */ 615f1c0a02fSMark Brown #define WM8903_DRC_R0_SLOPE_COMP_WIDTH 3 /* DRC_R0_SLOPE_COMP - [5:3] */ 616f1c0a02fSMark Brown #define WM8903_DRC_R1_SLOPE_COMP_MASK 0x0007 /* DRC_R1_SLOPE_COMP - [2:0] */ 617f1c0a02fSMark Brown #define WM8903_DRC_R1_SLOPE_COMP_SHIFT 0 /* DRC_R1_SLOPE_COMP - [2:0] */ 618f1c0a02fSMark Brown #define WM8903_DRC_R1_SLOPE_COMP_WIDTH 3 /* DRC_R1_SLOPE_COMP - [2:0] */ 619f1c0a02fSMark Brown 620f1c0a02fSMark Brown /* 621f1c0a02fSMark Brown * R43 (0x2B) - DRC 3 622f1c0a02fSMark Brown */ 623f1c0a02fSMark Brown #define WM8903_DRC_THRESH_COMP_MASK 0x07E0 /* DRC_THRESH_COMP - [10:5] */ 624f1c0a02fSMark Brown #define WM8903_DRC_THRESH_COMP_SHIFT 5 /* DRC_THRESH_COMP - [10:5] */ 625f1c0a02fSMark Brown #define WM8903_DRC_THRESH_COMP_WIDTH 6 /* DRC_THRESH_COMP - [10:5] */ 626f1c0a02fSMark Brown #define WM8903_DRC_AMP_COMP_MASK 0x001F /* DRC_AMP_COMP - [4:0] */ 627f1c0a02fSMark Brown #define WM8903_DRC_AMP_COMP_SHIFT 0 /* DRC_AMP_COMP - [4:0] */ 628f1c0a02fSMark Brown #define WM8903_DRC_AMP_COMP_WIDTH 5 /* DRC_AMP_COMP - [4:0] */ 629f1c0a02fSMark Brown 630f1c0a02fSMark Brown /* 631f1c0a02fSMark Brown * R44 (0x2C) - Analogue Left Input 0 632f1c0a02fSMark Brown */ 633f1c0a02fSMark Brown #define WM8903_LINMUTE 0x0080 /* LINMUTE */ 634f1c0a02fSMark Brown #define WM8903_LINMUTE_MASK 0x0080 /* LINMUTE */ 635f1c0a02fSMark Brown #define WM8903_LINMUTE_SHIFT 7 /* LINMUTE */ 636f1c0a02fSMark Brown #define WM8903_LINMUTE_WIDTH 1 /* LINMUTE */ 637f1c0a02fSMark Brown #define WM8903_LIN_VOL_MASK 0x001F /* LIN_VOL - [4:0] */ 638f1c0a02fSMark Brown #define WM8903_LIN_VOL_SHIFT 0 /* LIN_VOL - [4:0] */ 639f1c0a02fSMark Brown #define WM8903_LIN_VOL_WIDTH 5 /* LIN_VOL - [4:0] */ 640f1c0a02fSMark Brown 641f1c0a02fSMark Brown /* 642f1c0a02fSMark Brown * R45 (0x2D) - Analogue Right Input 0 643f1c0a02fSMark Brown */ 644f1c0a02fSMark Brown #define WM8903_RINMUTE 0x0080 /* RINMUTE */ 645f1c0a02fSMark Brown #define WM8903_RINMUTE_MASK 0x0080 /* RINMUTE */ 646f1c0a02fSMark Brown #define WM8903_RINMUTE_SHIFT 7 /* RINMUTE */ 647f1c0a02fSMark Brown #define WM8903_RINMUTE_WIDTH 1 /* RINMUTE */ 648f1c0a02fSMark Brown #define WM8903_RIN_VOL_MASK 0x001F /* RIN_VOL - [4:0] */ 649f1c0a02fSMark Brown #define WM8903_RIN_VOL_SHIFT 0 /* RIN_VOL - [4:0] */ 650f1c0a02fSMark Brown #define WM8903_RIN_VOL_WIDTH 5 /* RIN_VOL - [4:0] */ 651f1c0a02fSMark Brown 652f1c0a02fSMark Brown /* 653f1c0a02fSMark Brown * R46 (0x2E) - Analogue Left Input 1 654f1c0a02fSMark Brown */ 655f1c0a02fSMark Brown #define WM8903_INL_CM_ENA 0x0040 /* INL_CM_ENA */ 656f1c0a02fSMark Brown #define WM8903_INL_CM_ENA_MASK 0x0040 /* INL_CM_ENA */ 657f1c0a02fSMark Brown #define WM8903_INL_CM_ENA_SHIFT 6 /* INL_CM_ENA */ 658f1c0a02fSMark Brown #define WM8903_INL_CM_ENA_WIDTH 1 /* INL_CM_ENA */ 659f1c0a02fSMark Brown #define WM8903_L_IP_SEL_N_MASK 0x0030 /* L_IP_SEL_N - [5:4] */ 660f1c0a02fSMark Brown #define WM8903_L_IP_SEL_N_SHIFT 4 /* L_IP_SEL_N - [5:4] */ 661f1c0a02fSMark Brown #define WM8903_L_IP_SEL_N_WIDTH 2 /* L_IP_SEL_N - [5:4] */ 662f1c0a02fSMark Brown #define WM8903_L_IP_SEL_P_MASK 0x000C /* L_IP_SEL_P - [3:2] */ 663f1c0a02fSMark Brown #define WM8903_L_IP_SEL_P_SHIFT 2 /* L_IP_SEL_P - [3:2] */ 664f1c0a02fSMark Brown #define WM8903_L_IP_SEL_P_WIDTH 2 /* L_IP_SEL_P - [3:2] */ 665f1c0a02fSMark Brown #define WM8903_L_MODE_MASK 0x0003 /* L_MODE - [1:0] */ 666f1c0a02fSMark Brown #define WM8903_L_MODE_SHIFT 0 /* L_MODE - [1:0] */ 667f1c0a02fSMark Brown #define WM8903_L_MODE_WIDTH 2 /* L_MODE - [1:0] */ 668f1c0a02fSMark Brown 669f1c0a02fSMark Brown /* 670f1c0a02fSMark Brown * R47 (0x2F) - Analogue Right Input 1 671f1c0a02fSMark Brown */ 672f1c0a02fSMark Brown #define WM8903_INR_CM_ENA 0x0040 /* INR_CM_ENA */ 673f1c0a02fSMark Brown #define WM8903_INR_CM_ENA_MASK 0x0040 /* INR_CM_ENA */ 674f1c0a02fSMark Brown #define WM8903_INR_CM_ENA_SHIFT 6 /* INR_CM_ENA */ 675f1c0a02fSMark Brown #define WM8903_INR_CM_ENA_WIDTH 1 /* INR_CM_ENA */ 676f1c0a02fSMark Brown #define WM8903_R_IP_SEL_N_MASK 0x0030 /* R_IP_SEL_N - [5:4] */ 677f1c0a02fSMark Brown #define WM8903_R_IP_SEL_N_SHIFT 4 /* R_IP_SEL_N - [5:4] */ 678f1c0a02fSMark Brown #define WM8903_R_IP_SEL_N_WIDTH 2 /* R_IP_SEL_N - [5:4] */ 679f1c0a02fSMark Brown #define WM8903_R_IP_SEL_P_MASK 0x000C /* R_IP_SEL_P - [3:2] */ 680f1c0a02fSMark Brown #define WM8903_R_IP_SEL_P_SHIFT 2 /* R_IP_SEL_P - [3:2] */ 681f1c0a02fSMark Brown #define WM8903_R_IP_SEL_P_WIDTH 2 /* R_IP_SEL_P - [3:2] */ 682f1c0a02fSMark Brown #define WM8903_R_MODE_MASK 0x0003 /* R_MODE - [1:0] */ 683f1c0a02fSMark Brown #define WM8903_R_MODE_SHIFT 0 /* R_MODE - [1:0] */ 684f1c0a02fSMark Brown #define WM8903_R_MODE_WIDTH 2 /* R_MODE - [1:0] */ 685f1c0a02fSMark Brown 686f1c0a02fSMark Brown /* 687f1c0a02fSMark Brown * R50 (0x32) - Analogue Left Mix 0 688f1c0a02fSMark Brown */ 689f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTL 0x0008 /* DACL_TO_MIXOUTL */ 690f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTL_MASK 0x0008 /* DACL_TO_MIXOUTL */ 691f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTL_SHIFT 3 /* DACL_TO_MIXOUTL */ 692f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTL_WIDTH 1 /* DACL_TO_MIXOUTL */ 693f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTL 0x0004 /* DACR_TO_MIXOUTL */ 694f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTL_MASK 0x0004 /* DACR_TO_MIXOUTL */ 695f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTL_SHIFT 2 /* DACR_TO_MIXOUTL */ 696f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTL_WIDTH 1 /* DACR_TO_MIXOUTL */ 697f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTL 0x0002 /* BYPASSL_TO_MIXOUTL */ 698f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTL_MASK 0x0002 /* BYPASSL_TO_MIXOUTL */ 699f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTL_SHIFT 1 /* BYPASSL_TO_MIXOUTL */ 700f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTL_WIDTH 1 /* BYPASSL_TO_MIXOUTL */ 701f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTL 0x0001 /* BYPASSR_TO_MIXOUTL */ 702f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTL_MASK 0x0001 /* BYPASSR_TO_MIXOUTL */ 703f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTL_SHIFT 0 /* BYPASSR_TO_MIXOUTL */ 704f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTL_WIDTH 1 /* BYPASSR_TO_MIXOUTL */ 705f1c0a02fSMark Brown 706f1c0a02fSMark Brown /* 707f1c0a02fSMark Brown * R51 (0x33) - Analogue Right Mix 0 708f1c0a02fSMark Brown */ 709f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTR 0x0008 /* DACL_TO_MIXOUTR */ 710f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTR_MASK 0x0008 /* DACL_TO_MIXOUTR */ 711f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTR_SHIFT 3 /* DACL_TO_MIXOUTR */ 712f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTR_WIDTH 1 /* DACL_TO_MIXOUTR */ 713f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTR 0x0004 /* DACR_TO_MIXOUTR */ 714f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTR_MASK 0x0004 /* DACR_TO_MIXOUTR */ 715f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTR_SHIFT 2 /* DACR_TO_MIXOUTR */ 716f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTR_WIDTH 1 /* DACR_TO_MIXOUTR */ 717f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTR 0x0002 /* BYPASSL_TO_MIXOUTR */ 718f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTR_MASK 0x0002 /* BYPASSL_TO_MIXOUTR */ 719f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTR_SHIFT 1 /* BYPASSL_TO_MIXOUTR */ 720f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTR_WIDTH 1 /* BYPASSL_TO_MIXOUTR */ 721f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTR 0x0001 /* BYPASSR_TO_MIXOUTR */ 722f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTR_MASK 0x0001 /* BYPASSR_TO_MIXOUTR */ 723f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTR_SHIFT 0 /* BYPASSR_TO_MIXOUTR */ 724f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTR_WIDTH 1 /* BYPASSR_TO_MIXOUTR */ 725f1c0a02fSMark Brown 726f1c0a02fSMark Brown /* 727f1c0a02fSMark Brown * R52 (0x34) - Analogue Spk Mix Left 0 728f1c0a02fSMark Brown */ 729f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKL 0x0008 /* DACL_TO_MIXSPKL */ 730f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKL_MASK 0x0008 /* DACL_TO_MIXSPKL */ 731f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKL_SHIFT 3 /* DACL_TO_MIXSPKL */ 732f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKL_WIDTH 1 /* DACL_TO_MIXSPKL */ 733f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKL 0x0004 /* DACR_TO_MIXSPKL */ 734f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKL_MASK 0x0004 /* DACR_TO_MIXSPKL */ 735f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKL_SHIFT 2 /* DACR_TO_MIXSPKL */ 736f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKL_WIDTH 1 /* DACR_TO_MIXSPKL */ 737f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKL 0x0002 /* BYPASSL_TO_MIXSPKL */ 738f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKL_MASK 0x0002 /* BYPASSL_TO_MIXSPKL */ 739f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKL_SHIFT 1 /* BYPASSL_TO_MIXSPKL */ 740f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKL_WIDTH 1 /* BYPASSL_TO_MIXSPKL */ 741f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKL 0x0001 /* BYPASSR_TO_MIXSPKL */ 742f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKL_MASK 0x0001 /* BYPASSR_TO_MIXSPKL */ 743f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKL_SHIFT 0 /* BYPASSR_TO_MIXSPKL */ 744f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKL_WIDTH 1 /* BYPASSR_TO_MIXSPKL */ 745f1c0a02fSMark Brown 746f1c0a02fSMark Brown /* 747f1c0a02fSMark Brown * R53 (0x35) - Analogue Spk Mix Left 1 748f1c0a02fSMark Brown */ 749f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKL_VOL 0x0008 /* DACL_MIXSPKL_VOL */ 750f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKL_VOL_MASK 0x0008 /* DACL_MIXSPKL_VOL */ 751f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKL_VOL_SHIFT 3 /* DACL_MIXSPKL_VOL */ 752f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKL_VOL_WIDTH 1 /* DACL_MIXSPKL_VOL */ 753f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKL_VOL 0x0004 /* DACR_MIXSPKL_VOL */ 754f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKL_VOL_MASK 0x0004 /* DACR_MIXSPKL_VOL */ 755f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKL_VOL_SHIFT 2 /* DACR_MIXSPKL_VOL */ 756f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKL_VOL_WIDTH 1 /* DACR_MIXSPKL_VOL */ 757f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKL_VOL 0x0002 /* BYPASSL_MIXSPKL_VOL */ 758f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKL_VOL_MASK 0x0002 /* BYPASSL_MIXSPKL_VOL */ 759f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKL_VOL_SHIFT 1 /* BYPASSL_MIXSPKL_VOL */ 760f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKL_VOL_WIDTH 1 /* BYPASSL_MIXSPKL_VOL */ 761f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKL_VOL 0x0001 /* BYPASSR_MIXSPKL_VOL */ 762f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKL_VOL_MASK 0x0001 /* BYPASSR_MIXSPKL_VOL */ 763f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKL_VOL_SHIFT 0 /* BYPASSR_MIXSPKL_VOL */ 764f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKL_VOL_WIDTH 1 /* BYPASSR_MIXSPKL_VOL */ 765f1c0a02fSMark Brown 766f1c0a02fSMark Brown /* 767f1c0a02fSMark Brown * R54 (0x36) - Analogue Spk Mix Right 0 768f1c0a02fSMark Brown */ 769f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKR 0x0008 /* DACL_TO_MIXSPKR */ 770f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKR_MASK 0x0008 /* DACL_TO_MIXSPKR */ 771f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKR_SHIFT 3 /* DACL_TO_MIXSPKR */ 772f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKR_WIDTH 1 /* DACL_TO_MIXSPKR */ 773f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKR 0x0004 /* DACR_TO_MIXSPKR */ 774f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKR_MASK 0x0004 /* DACR_TO_MIXSPKR */ 775f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKR_SHIFT 2 /* DACR_TO_MIXSPKR */ 776f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKR_WIDTH 1 /* DACR_TO_MIXSPKR */ 777f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKR 0x0002 /* BYPASSL_TO_MIXSPKR */ 778f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKR_MASK 0x0002 /* BYPASSL_TO_MIXSPKR */ 779f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKR_SHIFT 1 /* BYPASSL_TO_MIXSPKR */ 780f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKR_WIDTH 1 /* BYPASSL_TO_MIXSPKR */ 781f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKR 0x0001 /* BYPASSR_TO_MIXSPKR */ 782f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKR_MASK 0x0001 /* BYPASSR_TO_MIXSPKR */ 783f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKR_SHIFT 0 /* BYPASSR_TO_MIXSPKR */ 784f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKR_WIDTH 1 /* BYPASSR_TO_MIXSPKR */ 785f1c0a02fSMark Brown 786f1c0a02fSMark Brown /* 787f1c0a02fSMark Brown * R55 (0x37) - Analogue Spk Mix Right 1 788f1c0a02fSMark Brown */ 789f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKR_VOL 0x0008 /* DACL_MIXSPKR_VOL */ 790f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKR_VOL_MASK 0x0008 /* DACL_MIXSPKR_VOL */ 791f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKR_VOL_SHIFT 3 /* DACL_MIXSPKR_VOL */ 792f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKR_VOL_WIDTH 1 /* DACL_MIXSPKR_VOL */ 793f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKR_VOL 0x0004 /* DACR_MIXSPKR_VOL */ 794f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKR_VOL_MASK 0x0004 /* DACR_MIXSPKR_VOL */ 795f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKR_VOL_SHIFT 2 /* DACR_MIXSPKR_VOL */ 796f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKR_VOL_WIDTH 1 /* DACR_MIXSPKR_VOL */ 797f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKR_VOL 0x0002 /* BYPASSL_MIXSPKR_VOL */ 798f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKR_VOL_MASK 0x0002 /* BYPASSL_MIXSPKR_VOL */ 799f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKR_VOL_SHIFT 1 /* BYPASSL_MIXSPKR_VOL */ 800f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKR_VOL_WIDTH 1 /* BYPASSL_MIXSPKR_VOL */ 801f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKR_VOL 0x0001 /* BYPASSR_MIXSPKR_VOL */ 802f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKR_VOL_MASK 0x0001 /* BYPASSR_MIXSPKR_VOL */ 803f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKR_VOL_SHIFT 0 /* BYPASSR_MIXSPKR_VOL */ 804f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKR_VOL_WIDTH 1 /* BYPASSR_MIXSPKR_VOL */ 805f1c0a02fSMark Brown 806f1c0a02fSMark Brown /* 807f1c0a02fSMark Brown * R57 (0x39) - Analogue OUT1 Left 808f1c0a02fSMark Brown */ 809f1c0a02fSMark Brown #define WM8903_HPL_MUTE 0x0100 /* HPL_MUTE */ 810f1c0a02fSMark Brown #define WM8903_HPL_MUTE_MASK 0x0100 /* HPL_MUTE */ 811f1c0a02fSMark Brown #define WM8903_HPL_MUTE_SHIFT 8 /* HPL_MUTE */ 812f1c0a02fSMark Brown #define WM8903_HPL_MUTE_WIDTH 1 /* HPL_MUTE */ 813f1c0a02fSMark Brown #define WM8903_HPOUTVU 0x0080 /* HPOUTVU */ 814f1c0a02fSMark Brown #define WM8903_HPOUTVU_MASK 0x0080 /* HPOUTVU */ 815f1c0a02fSMark Brown #define WM8903_HPOUTVU_SHIFT 7 /* HPOUTVU */ 816f1c0a02fSMark Brown #define WM8903_HPOUTVU_WIDTH 1 /* HPOUTVU */ 817f1c0a02fSMark Brown #define WM8903_HPOUTLZC 0x0040 /* HPOUTLZC */ 818f1c0a02fSMark Brown #define WM8903_HPOUTLZC_MASK 0x0040 /* HPOUTLZC */ 819f1c0a02fSMark Brown #define WM8903_HPOUTLZC_SHIFT 6 /* HPOUTLZC */ 820f1c0a02fSMark Brown #define WM8903_HPOUTLZC_WIDTH 1 /* HPOUTLZC */ 821f1c0a02fSMark Brown #define WM8903_HPOUTL_VOL_MASK 0x003F /* HPOUTL_VOL - [5:0] */ 822f1c0a02fSMark Brown #define WM8903_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [5:0] */ 823f1c0a02fSMark Brown #define WM8903_HPOUTL_VOL_WIDTH 6 /* HPOUTL_VOL - [5:0] */ 824f1c0a02fSMark Brown 825f1c0a02fSMark Brown /* 826f1c0a02fSMark Brown * R58 (0x3A) - Analogue OUT1 Right 827f1c0a02fSMark Brown */ 828f1c0a02fSMark Brown #define WM8903_HPR_MUTE 0x0100 /* HPR_MUTE */ 829f1c0a02fSMark Brown #define WM8903_HPR_MUTE_MASK 0x0100 /* HPR_MUTE */ 830f1c0a02fSMark Brown #define WM8903_HPR_MUTE_SHIFT 8 /* HPR_MUTE */ 831f1c0a02fSMark Brown #define WM8903_HPR_MUTE_WIDTH 1 /* HPR_MUTE */ 832f1c0a02fSMark Brown #define WM8903_HPOUTVU 0x0080 /* HPOUTVU */ 833f1c0a02fSMark Brown #define WM8903_HPOUTVU_MASK 0x0080 /* HPOUTVU */ 834f1c0a02fSMark Brown #define WM8903_HPOUTVU_SHIFT 7 /* HPOUTVU */ 835f1c0a02fSMark Brown #define WM8903_HPOUTVU_WIDTH 1 /* HPOUTVU */ 836f1c0a02fSMark Brown #define WM8903_HPOUTRZC 0x0040 /* HPOUTRZC */ 837f1c0a02fSMark Brown #define WM8903_HPOUTRZC_MASK 0x0040 /* HPOUTRZC */ 838f1c0a02fSMark Brown #define WM8903_HPOUTRZC_SHIFT 6 /* HPOUTRZC */ 839f1c0a02fSMark Brown #define WM8903_HPOUTRZC_WIDTH 1 /* HPOUTRZC */ 840f1c0a02fSMark Brown #define WM8903_HPOUTR_VOL_MASK 0x003F /* HPOUTR_VOL - [5:0] */ 841f1c0a02fSMark Brown #define WM8903_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [5:0] */ 842f1c0a02fSMark Brown #define WM8903_HPOUTR_VOL_WIDTH 6 /* HPOUTR_VOL - [5:0] */ 843f1c0a02fSMark Brown 844f1c0a02fSMark Brown /* 845f1c0a02fSMark Brown * R59 (0x3B) - Analogue OUT2 Left 846f1c0a02fSMark Brown */ 847f1c0a02fSMark Brown #define WM8903_LINEOUTL_MUTE 0x0100 /* LINEOUTL_MUTE */ 848f1c0a02fSMark Brown #define WM8903_LINEOUTL_MUTE_MASK 0x0100 /* LINEOUTL_MUTE */ 849f1c0a02fSMark Brown #define WM8903_LINEOUTL_MUTE_SHIFT 8 /* LINEOUTL_MUTE */ 850f1c0a02fSMark Brown #define WM8903_LINEOUTL_MUTE_WIDTH 1 /* LINEOUTL_MUTE */ 851f1c0a02fSMark Brown #define WM8903_LINEOUTVU 0x0080 /* LINEOUTVU */ 852f1c0a02fSMark Brown #define WM8903_LINEOUTVU_MASK 0x0080 /* LINEOUTVU */ 853f1c0a02fSMark Brown #define WM8903_LINEOUTVU_SHIFT 7 /* LINEOUTVU */ 854f1c0a02fSMark Brown #define WM8903_LINEOUTVU_WIDTH 1 /* LINEOUTVU */ 855f1c0a02fSMark Brown #define WM8903_LINEOUTLZC 0x0040 /* LINEOUTLZC */ 856f1c0a02fSMark Brown #define WM8903_LINEOUTLZC_MASK 0x0040 /* LINEOUTLZC */ 857f1c0a02fSMark Brown #define WM8903_LINEOUTLZC_SHIFT 6 /* LINEOUTLZC */ 858f1c0a02fSMark Brown #define WM8903_LINEOUTLZC_WIDTH 1 /* LINEOUTLZC */ 859f1c0a02fSMark Brown #define WM8903_LINEOUTL_VOL_MASK 0x003F /* LINEOUTL_VOL - [5:0] */ 860f1c0a02fSMark Brown #define WM8903_LINEOUTL_VOL_SHIFT 0 /* LINEOUTL_VOL - [5:0] */ 861f1c0a02fSMark Brown #define WM8903_LINEOUTL_VOL_WIDTH 6 /* LINEOUTL_VOL - [5:0] */ 862f1c0a02fSMark Brown 863f1c0a02fSMark Brown /* 864f1c0a02fSMark Brown * R60 (0x3C) - Analogue OUT2 Right 865f1c0a02fSMark Brown */ 866f1c0a02fSMark Brown #define WM8903_LINEOUTR_MUTE 0x0100 /* LINEOUTR_MUTE */ 867f1c0a02fSMark Brown #define WM8903_LINEOUTR_MUTE_MASK 0x0100 /* LINEOUTR_MUTE */ 868f1c0a02fSMark Brown #define WM8903_LINEOUTR_MUTE_SHIFT 8 /* LINEOUTR_MUTE */ 869f1c0a02fSMark Brown #define WM8903_LINEOUTR_MUTE_WIDTH 1 /* LINEOUTR_MUTE */ 870f1c0a02fSMark Brown #define WM8903_LINEOUTVU 0x0080 /* LINEOUTVU */ 871f1c0a02fSMark Brown #define WM8903_LINEOUTVU_MASK 0x0080 /* LINEOUTVU */ 872f1c0a02fSMark Brown #define WM8903_LINEOUTVU_SHIFT 7 /* LINEOUTVU */ 873f1c0a02fSMark Brown #define WM8903_LINEOUTVU_WIDTH 1 /* LINEOUTVU */ 874f1c0a02fSMark Brown #define WM8903_LINEOUTRZC 0x0040 /* LINEOUTRZC */ 875f1c0a02fSMark Brown #define WM8903_LINEOUTRZC_MASK 0x0040 /* LINEOUTRZC */ 876f1c0a02fSMark Brown #define WM8903_LINEOUTRZC_SHIFT 6 /* LINEOUTRZC */ 877f1c0a02fSMark Brown #define WM8903_LINEOUTRZC_WIDTH 1 /* LINEOUTRZC */ 878f1c0a02fSMark Brown #define WM8903_LINEOUTR_VOL_MASK 0x003F /* LINEOUTR_VOL - [5:0] */ 879f1c0a02fSMark Brown #define WM8903_LINEOUTR_VOL_SHIFT 0 /* LINEOUTR_VOL - [5:0] */ 880f1c0a02fSMark Brown #define WM8903_LINEOUTR_VOL_WIDTH 6 /* LINEOUTR_VOL - [5:0] */ 881f1c0a02fSMark Brown 882f1c0a02fSMark Brown /* 883f1c0a02fSMark Brown * R62 (0x3E) - Analogue OUT3 Left 884f1c0a02fSMark Brown */ 885f1c0a02fSMark Brown #define WM8903_SPKL_MUTE 0x0100 /* SPKL_MUTE */ 886f1c0a02fSMark Brown #define WM8903_SPKL_MUTE_MASK 0x0100 /* SPKL_MUTE */ 887f1c0a02fSMark Brown #define WM8903_SPKL_MUTE_SHIFT 8 /* SPKL_MUTE */ 888f1c0a02fSMark Brown #define WM8903_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */ 889f1c0a02fSMark Brown #define WM8903_SPKVU 0x0080 /* SPKVU */ 890f1c0a02fSMark Brown #define WM8903_SPKVU_MASK 0x0080 /* SPKVU */ 891f1c0a02fSMark Brown #define WM8903_SPKVU_SHIFT 7 /* SPKVU */ 892f1c0a02fSMark Brown #define WM8903_SPKVU_WIDTH 1 /* SPKVU */ 893f1c0a02fSMark Brown #define WM8903_SPKLZC 0x0040 /* SPKLZC */ 894f1c0a02fSMark Brown #define WM8903_SPKLZC_MASK 0x0040 /* SPKLZC */ 895f1c0a02fSMark Brown #define WM8903_SPKLZC_SHIFT 6 /* SPKLZC */ 896f1c0a02fSMark Brown #define WM8903_SPKLZC_WIDTH 1 /* SPKLZC */ 897f1c0a02fSMark Brown #define WM8903_SPKL_VOL_MASK 0x003F /* SPKL_VOL - [5:0] */ 898f1c0a02fSMark Brown #define WM8903_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [5:0] */ 899f1c0a02fSMark Brown #define WM8903_SPKL_VOL_WIDTH 6 /* SPKL_VOL - [5:0] */ 900f1c0a02fSMark Brown 901f1c0a02fSMark Brown /* 902f1c0a02fSMark Brown * R63 (0x3F) - Analogue OUT3 Right 903f1c0a02fSMark Brown */ 904f1c0a02fSMark Brown #define WM8903_SPKR_MUTE 0x0100 /* SPKR_MUTE */ 905f1c0a02fSMark Brown #define WM8903_SPKR_MUTE_MASK 0x0100 /* SPKR_MUTE */ 906f1c0a02fSMark Brown #define WM8903_SPKR_MUTE_SHIFT 8 /* SPKR_MUTE */ 907f1c0a02fSMark Brown #define WM8903_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */ 908f1c0a02fSMark Brown #define WM8903_SPKVU 0x0080 /* SPKVU */ 909f1c0a02fSMark Brown #define WM8903_SPKVU_MASK 0x0080 /* SPKVU */ 910f1c0a02fSMark Brown #define WM8903_SPKVU_SHIFT 7 /* SPKVU */ 911f1c0a02fSMark Brown #define WM8903_SPKVU_WIDTH 1 /* SPKVU */ 912f1c0a02fSMark Brown #define WM8903_SPKRZC 0x0040 /* SPKRZC */ 913f1c0a02fSMark Brown #define WM8903_SPKRZC_MASK 0x0040 /* SPKRZC */ 914f1c0a02fSMark Brown #define WM8903_SPKRZC_SHIFT 6 /* SPKRZC */ 915f1c0a02fSMark Brown #define WM8903_SPKRZC_WIDTH 1 /* SPKRZC */ 916f1c0a02fSMark Brown #define WM8903_SPKR_VOL_MASK 0x003F /* SPKR_VOL - [5:0] */ 917f1c0a02fSMark Brown #define WM8903_SPKR_VOL_SHIFT 0 /* SPKR_VOL - [5:0] */ 918f1c0a02fSMark Brown #define WM8903_SPKR_VOL_WIDTH 6 /* SPKR_VOL - [5:0] */ 919f1c0a02fSMark Brown 920f1c0a02fSMark Brown /* 921f1c0a02fSMark Brown * R65 (0x41) - Analogue SPK Output Control 0 922f1c0a02fSMark Brown */ 923f1c0a02fSMark Brown #define WM8903_SPK_DISCHARGE 0x0002 /* SPK_DISCHARGE */ 924f1c0a02fSMark Brown #define WM8903_SPK_DISCHARGE_MASK 0x0002 /* SPK_DISCHARGE */ 925f1c0a02fSMark Brown #define WM8903_SPK_DISCHARGE_SHIFT 1 /* SPK_DISCHARGE */ 926f1c0a02fSMark Brown #define WM8903_SPK_DISCHARGE_WIDTH 1 /* SPK_DISCHARGE */ 927f1c0a02fSMark Brown #define WM8903_VROI 0x0001 /* VROI */ 928f1c0a02fSMark Brown #define WM8903_VROI_MASK 0x0001 /* VROI */ 929f1c0a02fSMark Brown #define WM8903_VROI_SHIFT 0 /* VROI */ 930f1c0a02fSMark Brown #define WM8903_VROI_WIDTH 1 /* VROI */ 931f1c0a02fSMark Brown 932f1c0a02fSMark Brown /* 933f1c0a02fSMark Brown * R67 (0x43) - DC Servo 0 934f1c0a02fSMark Brown */ 935f1c0a02fSMark Brown #define WM8903_DCS_MASTER_ENA 0x0010 /* DCS_MASTER_ENA */ 936f1c0a02fSMark Brown #define WM8903_DCS_MASTER_ENA_MASK 0x0010 /* DCS_MASTER_ENA */ 937f1c0a02fSMark Brown #define WM8903_DCS_MASTER_ENA_SHIFT 4 /* DCS_MASTER_ENA */ 938f1c0a02fSMark Brown #define WM8903_DCS_MASTER_ENA_WIDTH 1 /* DCS_MASTER_ENA */ 939f1c0a02fSMark Brown #define WM8903_DCS_ENA_MASK 0x000F /* DCS_ENA - [3:0] */ 940f1c0a02fSMark Brown #define WM8903_DCS_ENA_SHIFT 0 /* DCS_ENA - [3:0] */ 941f1c0a02fSMark Brown #define WM8903_DCS_ENA_WIDTH 4 /* DCS_ENA - [3:0] */ 942f1c0a02fSMark Brown 943f1c0a02fSMark Brown /* 944f1c0a02fSMark Brown * R69 (0x45) - DC Servo 2 945f1c0a02fSMark Brown */ 946f1c0a02fSMark Brown #define WM8903_DCS_MODE_MASK 0x0003 /* DCS_MODE - [1:0] */ 947f1c0a02fSMark Brown #define WM8903_DCS_MODE_SHIFT 0 /* DCS_MODE - [1:0] */ 948f1c0a02fSMark Brown #define WM8903_DCS_MODE_WIDTH 2 /* DCS_MODE - [1:0] */ 949f1c0a02fSMark Brown 950f1c0a02fSMark Brown /* 951f1c0a02fSMark Brown * R90 (0x5A) - Analogue HP 0 952f1c0a02fSMark Brown */ 953f1c0a02fSMark Brown #define WM8903_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ 954f1c0a02fSMark Brown #define WM8903_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ 955f1c0a02fSMark Brown #define WM8903_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ 956f1c0a02fSMark Brown #define WM8903_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ 957f1c0a02fSMark Brown #define WM8903_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ 958f1c0a02fSMark Brown #define WM8903_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ 959f1c0a02fSMark Brown #define WM8903_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ 960f1c0a02fSMark Brown #define WM8903_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ 961f1c0a02fSMark Brown #define WM8903_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ 962f1c0a02fSMark Brown #define WM8903_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ 963f1c0a02fSMark Brown #define WM8903_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ 964f1c0a02fSMark Brown #define WM8903_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ 965f1c0a02fSMark Brown #define WM8903_HPL_ENA 0x0010 /* HPL_ENA */ 966f1c0a02fSMark Brown #define WM8903_HPL_ENA_MASK 0x0010 /* HPL_ENA */ 967f1c0a02fSMark Brown #define WM8903_HPL_ENA_SHIFT 4 /* HPL_ENA */ 968f1c0a02fSMark Brown #define WM8903_HPL_ENA_WIDTH 1 /* HPL_ENA */ 969f1c0a02fSMark Brown #define WM8903_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ 970f1c0a02fSMark Brown #define WM8903_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ 971f1c0a02fSMark Brown #define WM8903_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ 972f1c0a02fSMark Brown #define WM8903_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ 973f1c0a02fSMark Brown #define WM8903_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ 974f1c0a02fSMark Brown #define WM8903_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ 975f1c0a02fSMark Brown #define WM8903_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ 976f1c0a02fSMark Brown #define WM8903_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ 977f1c0a02fSMark Brown #define WM8903_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */ 978f1c0a02fSMark Brown #define WM8903_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ 979f1c0a02fSMark Brown #define WM8903_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ 980f1c0a02fSMark Brown #define WM8903_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ 981f1c0a02fSMark Brown #define WM8903_HPR_ENA 0x0001 /* HPR_ENA */ 982f1c0a02fSMark Brown #define WM8903_HPR_ENA_MASK 0x0001 /* HPR_ENA */ 983f1c0a02fSMark Brown #define WM8903_HPR_ENA_SHIFT 0 /* HPR_ENA */ 984f1c0a02fSMark Brown #define WM8903_HPR_ENA_WIDTH 1 /* HPR_ENA */ 985f1c0a02fSMark Brown 986f1c0a02fSMark Brown /* 987f1c0a02fSMark Brown * R94 (0x5E) - Analogue Lineout 0 988f1c0a02fSMark Brown */ 989f1c0a02fSMark Brown #define WM8903_LINEOUTL_RMV_SHORT 0x0080 /* LINEOUTL_RMV_SHORT */ 990f1c0a02fSMark Brown #define WM8903_LINEOUTL_RMV_SHORT_MASK 0x0080 /* LINEOUTL_RMV_SHORT */ 991f1c0a02fSMark Brown #define WM8903_LINEOUTL_RMV_SHORT_SHIFT 7 /* LINEOUTL_RMV_SHORT */ 992f1c0a02fSMark Brown #define WM8903_LINEOUTL_RMV_SHORT_WIDTH 1 /* LINEOUTL_RMV_SHORT */ 993f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_OUTP 0x0040 /* LINEOUTL_ENA_OUTP */ 994f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_OUTP_MASK 0x0040 /* LINEOUTL_ENA_OUTP */ 995f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_OUTP_SHIFT 6 /* LINEOUTL_ENA_OUTP */ 996f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_OUTP_WIDTH 1 /* LINEOUTL_ENA_OUTP */ 997f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_DLY 0x0020 /* LINEOUTL_ENA_DLY */ 998f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_DLY_MASK 0x0020 /* LINEOUTL_ENA_DLY */ 999f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_DLY_SHIFT 5 /* LINEOUTL_ENA_DLY */ 1000f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_DLY_WIDTH 1 /* LINEOUTL_ENA_DLY */ 1001f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA 0x0010 /* LINEOUTL_ENA */ 1002f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_MASK 0x0010 /* LINEOUTL_ENA */ 1003f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_SHIFT 4 /* LINEOUTL_ENA */ 1004f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_WIDTH 1 /* LINEOUTL_ENA */ 1005f1c0a02fSMark Brown #define WM8903_LINEOUTR_RMV_SHORT 0x0008 /* LINEOUTR_RMV_SHORT */ 1006f1c0a02fSMark Brown #define WM8903_LINEOUTR_RMV_SHORT_MASK 0x0008 /* LINEOUTR_RMV_SHORT */ 1007f1c0a02fSMark Brown #define WM8903_LINEOUTR_RMV_SHORT_SHIFT 3 /* LINEOUTR_RMV_SHORT */ 1008f1c0a02fSMark Brown #define WM8903_LINEOUTR_RMV_SHORT_WIDTH 1 /* LINEOUTR_RMV_SHORT */ 1009f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_OUTP 0x0004 /* LINEOUTR_ENA_OUTP */ 1010f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_OUTP_MASK 0x0004 /* LINEOUTR_ENA_OUTP */ 1011f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_OUTP_SHIFT 2 /* LINEOUTR_ENA_OUTP */ 1012f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_OUTP_WIDTH 1 /* LINEOUTR_ENA_OUTP */ 1013f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_DLY 0x0002 /* LINEOUTR_ENA_DLY */ 1014f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_DLY_MASK 0x0002 /* LINEOUTR_ENA_DLY */ 1015f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_DLY_SHIFT 1 /* LINEOUTR_ENA_DLY */ 1016f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_DLY_WIDTH 1 /* LINEOUTR_ENA_DLY */ 1017f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */ 1018f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */ 1019f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_SHIFT 0 /* LINEOUTR_ENA */ 1020f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_WIDTH 1 /* LINEOUTR_ENA */ 1021f1c0a02fSMark Brown 1022f1c0a02fSMark Brown /* 1023f1c0a02fSMark Brown * R98 (0x62) - Charge Pump 0 1024f1c0a02fSMark Brown */ 1025f1c0a02fSMark Brown #define WM8903_CP_ENA 0x0001 /* CP_ENA */ 1026f1c0a02fSMark Brown #define WM8903_CP_ENA_MASK 0x0001 /* CP_ENA */ 1027f1c0a02fSMark Brown #define WM8903_CP_ENA_SHIFT 0 /* CP_ENA */ 1028f1c0a02fSMark Brown #define WM8903_CP_ENA_WIDTH 1 /* CP_ENA */ 1029f1c0a02fSMark Brown 1030f1c0a02fSMark Brown /* 1031f1c0a02fSMark Brown * R104 (0x68) - Class W 0 1032f1c0a02fSMark Brown */ 1033f1c0a02fSMark Brown #define WM8903_CP_DYN_FREQ 0x0002 /* CP_DYN_FREQ */ 1034f1c0a02fSMark Brown #define WM8903_CP_DYN_FREQ_MASK 0x0002 /* CP_DYN_FREQ */ 1035f1c0a02fSMark Brown #define WM8903_CP_DYN_FREQ_SHIFT 1 /* CP_DYN_FREQ */ 1036f1c0a02fSMark Brown #define WM8903_CP_DYN_FREQ_WIDTH 1 /* CP_DYN_FREQ */ 1037f1c0a02fSMark Brown #define WM8903_CP_DYN_V 0x0001 /* CP_DYN_V */ 1038f1c0a02fSMark Brown #define WM8903_CP_DYN_V_MASK 0x0001 /* CP_DYN_V */ 1039f1c0a02fSMark Brown #define WM8903_CP_DYN_V_SHIFT 0 /* CP_DYN_V */ 1040f1c0a02fSMark Brown #define WM8903_CP_DYN_V_WIDTH 1 /* CP_DYN_V */ 1041f1c0a02fSMark Brown 1042f1c0a02fSMark Brown /* 1043f1c0a02fSMark Brown * R108 (0x6C) - Write Sequencer 0 1044f1c0a02fSMark Brown */ 1045f1c0a02fSMark Brown #define WM8903_WSEQ_ENA 0x0100 /* WSEQ_ENA */ 1046f1c0a02fSMark Brown #define WM8903_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */ 1047f1c0a02fSMark Brown #define WM8903_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */ 1048f1c0a02fSMark Brown #define WM8903_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1049f1c0a02fSMark Brown #define WM8903_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ 1050f1c0a02fSMark Brown #define WM8903_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ 1051f1c0a02fSMark Brown #define WM8903_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ 1052f1c0a02fSMark Brown 1053f1c0a02fSMark Brown /* 1054f1c0a02fSMark Brown * R109 (0x6D) - Write Sequencer 1 1055f1c0a02fSMark Brown */ 1056f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */ 1057f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */ 1058f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */ 1059f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */ 1060f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */ 1061f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */ 1062f1c0a02fSMark Brown #define WM8903_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ 1063f1c0a02fSMark Brown #define WM8903_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ 1064f1c0a02fSMark Brown #define WM8903_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ 1065f1c0a02fSMark Brown 1066f1c0a02fSMark Brown /* 1067f1c0a02fSMark Brown * R110 (0x6E) - Write Sequencer 2 1068f1c0a02fSMark Brown */ 1069f1c0a02fSMark Brown #define WM8903_WSEQ_EOS 0x4000 /* WSEQ_EOS */ 1070f1c0a02fSMark Brown #define WM8903_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */ 1071f1c0a02fSMark Brown #define WM8903_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */ 1072f1c0a02fSMark Brown #define WM8903_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ 1073f1c0a02fSMark Brown #define WM8903_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */ 1074f1c0a02fSMark Brown #define WM8903_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */ 1075f1c0a02fSMark Brown #define WM8903_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */ 1076f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ 1077f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ 1078f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ 1079f1c0a02fSMark Brown 1080f1c0a02fSMark Brown /* 1081f1c0a02fSMark Brown * R111 (0x6F) - Write Sequencer 3 1082f1c0a02fSMark Brown */ 1083f1c0a02fSMark Brown #define WM8903_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1084f1c0a02fSMark Brown #define WM8903_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1085f1c0a02fSMark Brown #define WM8903_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1086f1c0a02fSMark Brown #define WM8903_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1087f1c0a02fSMark Brown #define WM8903_WSEQ_START 0x0100 /* WSEQ_START */ 1088f1c0a02fSMark Brown #define WM8903_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1089f1c0a02fSMark Brown #define WM8903_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1090f1c0a02fSMark Brown #define WM8903_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1091f1c0a02fSMark Brown #define WM8903_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ 1092f1c0a02fSMark Brown #define WM8903_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ 1093f1c0a02fSMark Brown #define WM8903_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ 1094f1c0a02fSMark Brown 1095f1c0a02fSMark Brown /* 1096f1c0a02fSMark Brown * R112 (0x70) - Write Sequencer 4 1097f1c0a02fSMark Brown */ 1098f1c0a02fSMark Brown #define WM8903_WSEQ_CURRENT_INDEX_MASK 0x03F0 /* WSEQ_CURRENT_INDEX - [9:4] */ 1099f1c0a02fSMark Brown #define WM8903_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [9:4] */ 1100f1c0a02fSMark Brown #define WM8903_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [9:4] */ 1101f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 1102f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 1103f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 1104f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1105f1c0a02fSMark Brown 1106f1c0a02fSMark Brown /* 1107f1c0a02fSMark Brown * R114 (0x72) - Control Interface 1108f1c0a02fSMark Brown */ 1109f1c0a02fSMark Brown #define WM8903_MASK_WRITE_ENA 0x0001 /* MASK_WRITE_ENA */ 1110f1c0a02fSMark Brown #define WM8903_MASK_WRITE_ENA_MASK 0x0001 /* MASK_WRITE_ENA */ 1111f1c0a02fSMark Brown #define WM8903_MASK_WRITE_ENA_SHIFT 0 /* MASK_WRITE_ENA */ 1112f1c0a02fSMark Brown #define WM8903_MASK_WRITE_ENA_WIDTH 1 /* MASK_WRITE_ENA */ 1113f1c0a02fSMark Brown 1114f1c0a02fSMark Brown /* 1115f1c0a02fSMark Brown * R121 (0x79) - Interrupt Status 1 1116f1c0a02fSMark Brown */ 1117f1c0a02fSMark Brown #define WM8903_MICSHRT_EINT 0x8000 /* MICSHRT_EINT */ 1118f1c0a02fSMark Brown #define WM8903_MICSHRT_EINT_MASK 0x8000 /* MICSHRT_EINT */ 1119f1c0a02fSMark Brown #define WM8903_MICSHRT_EINT_SHIFT 15 /* MICSHRT_EINT */ 1120f1c0a02fSMark Brown #define WM8903_MICSHRT_EINT_WIDTH 1 /* MICSHRT_EINT */ 1121f1c0a02fSMark Brown #define WM8903_MICDET_EINT 0x4000 /* MICDET_EINT */ 1122f1c0a02fSMark Brown #define WM8903_MICDET_EINT_MASK 0x4000 /* MICDET_EINT */ 1123f1c0a02fSMark Brown #define WM8903_MICDET_EINT_SHIFT 14 /* MICDET_EINT */ 1124f1c0a02fSMark Brown #define WM8903_MICDET_EINT_WIDTH 1 /* MICDET_EINT */ 1125f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_EINT 0x2000 /* WSEQ_BUSY_EINT */ 1126f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_EINT_MASK 0x2000 /* WSEQ_BUSY_EINT */ 1127f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_EINT_SHIFT 13 /* WSEQ_BUSY_EINT */ 1128f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */ 1129f1c0a02fSMark Brown #define WM8903_GP5_EINT 0x0010 /* GP5_EINT */ 1130f1c0a02fSMark Brown #define WM8903_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 1131f1c0a02fSMark Brown #define WM8903_GP5_EINT_SHIFT 4 /* GP5_EINT */ 1132f1c0a02fSMark Brown #define WM8903_GP5_EINT_WIDTH 1 /* GP5_EINT */ 1133f1c0a02fSMark Brown #define WM8903_GP4_EINT 0x0008 /* GP4_EINT */ 1134f1c0a02fSMark Brown #define WM8903_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 1135f1c0a02fSMark Brown #define WM8903_GP4_EINT_SHIFT 3 /* GP4_EINT */ 1136f1c0a02fSMark Brown #define WM8903_GP4_EINT_WIDTH 1 /* GP4_EINT */ 1137f1c0a02fSMark Brown #define WM8903_GP3_EINT 0x0004 /* GP3_EINT */ 1138f1c0a02fSMark Brown #define WM8903_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 1139f1c0a02fSMark Brown #define WM8903_GP3_EINT_SHIFT 2 /* GP3_EINT */ 1140f1c0a02fSMark Brown #define WM8903_GP3_EINT_WIDTH 1 /* GP3_EINT */ 1141f1c0a02fSMark Brown #define WM8903_GP2_EINT 0x0002 /* GP2_EINT */ 1142f1c0a02fSMark Brown #define WM8903_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 1143f1c0a02fSMark Brown #define WM8903_GP2_EINT_SHIFT 1 /* GP2_EINT */ 1144f1c0a02fSMark Brown #define WM8903_GP2_EINT_WIDTH 1 /* GP2_EINT */ 1145f1c0a02fSMark Brown #define WM8903_GP1_EINT 0x0001 /* GP1_EINT */ 1146f1c0a02fSMark Brown #define WM8903_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 1147f1c0a02fSMark Brown #define WM8903_GP1_EINT_SHIFT 0 /* GP1_EINT */ 1148f1c0a02fSMark Brown #define WM8903_GP1_EINT_WIDTH 1 /* GP1_EINT */ 1149f1c0a02fSMark Brown 1150f1c0a02fSMark Brown /* 1151f1c0a02fSMark Brown * R122 (0x7A) - Interrupt Status 1 Mask 1152f1c0a02fSMark Brown */ 1153f1c0a02fSMark Brown #define WM8903_IM_MICSHRT_EINT 0x8000 /* IM_MICSHRT_EINT */ 1154f1c0a02fSMark Brown #define WM8903_IM_MICSHRT_EINT_MASK 0x8000 /* IM_MICSHRT_EINT */ 1155f1c0a02fSMark Brown #define WM8903_IM_MICSHRT_EINT_SHIFT 15 /* IM_MICSHRT_EINT */ 1156f1c0a02fSMark Brown #define WM8903_IM_MICSHRT_EINT_WIDTH 1 /* IM_MICSHRT_EINT */ 1157f1c0a02fSMark Brown #define WM8903_IM_MICDET_EINT 0x4000 /* IM_MICDET_EINT */ 1158f1c0a02fSMark Brown #define WM8903_IM_MICDET_EINT_MASK 0x4000 /* IM_MICDET_EINT */ 1159f1c0a02fSMark Brown #define WM8903_IM_MICDET_EINT_SHIFT 14 /* IM_MICDET_EINT */ 1160f1c0a02fSMark Brown #define WM8903_IM_MICDET_EINT_WIDTH 1 /* IM_MICDET_EINT */ 1161f1c0a02fSMark Brown #define WM8903_IM_WSEQ_BUSY_EINT 0x2000 /* IM_WSEQ_BUSY_EINT */ 1162f1c0a02fSMark Brown #define WM8903_IM_WSEQ_BUSY_EINT_MASK 0x2000 /* IM_WSEQ_BUSY_EINT */ 1163f1c0a02fSMark Brown #define WM8903_IM_WSEQ_BUSY_EINT_SHIFT 13 /* IM_WSEQ_BUSY_EINT */ 1164f1c0a02fSMark Brown #define WM8903_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */ 1165f1c0a02fSMark Brown #define WM8903_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 1166f1c0a02fSMark Brown #define WM8903_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 1167f1c0a02fSMark Brown #define WM8903_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 1168f1c0a02fSMark Brown #define WM8903_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 1169f1c0a02fSMark Brown #define WM8903_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 1170f1c0a02fSMark Brown #define WM8903_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 1171f1c0a02fSMark Brown #define WM8903_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 1172f1c0a02fSMark Brown #define WM8903_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 1173f1c0a02fSMark Brown #define WM8903_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 1174f1c0a02fSMark Brown #define WM8903_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 1175f1c0a02fSMark Brown #define WM8903_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 1176f1c0a02fSMark Brown #define WM8903_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 1177f1c0a02fSMark Brown #define WM8903_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 1178f1c0a02fSMark Brown #define WM8903_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 1179f1c0a02fSMark Brown #define WM8903_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 1180f1c0a02fSMark Brown #define WM8903_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 1181f1c0a02fSMark Brown #define WM8903_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 1182f1c0a02fSMark Brown #define WM8903_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 1183f1c0a02fSMark Brown #define WM8903_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 1184f1c0a02fSMark Brown #define WM8903_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 1185f1c0a02fSMark Brown 1186f1c0a02fSMark Brown /* 1187f1c0a02fSMark Brown * R123 (0x7B) - Interrupt Polarity 1 1188f1c0a02fSMark Brown */ 1189f1c0a02fSMark Brown #define WM8903_MICSHRT_INV 0x8000 /* MICSHRT_INV */ 1190f1c0a02fSMark Brown #define WM8903_MICSHRT_INV_MASK 0x8000 /* MICSHRT_INV */ 1191f1c0a02fSMark Brown #define WM8903_MICSHRT_INV_SHIFT 15 /* MICSHRT_INV */ 1192f1c0a02fSMark Brown #define WM8903_MICSHRT_INV_WIDTH 1 /* MICSHRT_INV */ 1193f1c0a02fSMark Brown #define WM8903_MICDET_INV 0x4000 /* MICDET_INV */ 1194f1c0a02fSMark Brown #define WM8903_MICDET_INV_MASK 0x4000 /* MICDET_INV */ 1195f1c0a02fSMark Brown #define WM8903_MICDET_INV_SHIFT 14 /* MICDET_INV */ 1196f1c0a02fSMark Brown #define WM8903_MICDET_INV_WIDTH 1 /* MICDET_INV */ 1197f1c0a02fSMark Brown 1198f1c0a02fSMark Brown /* 1199f1c0a02fSMark Brown * R126 (0x7E) - Interrupt Control 1200f1c0a02fSMark Brown */ 1201f1c0a02fSMark Brown #define WM8903_IRQ_POL 0x0001 /* IRQ_POL */ 1202f1c0a02fSMark Brown #define WM8903_IRQ_POL_MASK 0x0001 /* IRQ_POL */ 1203f1c0a02fSMark Brown #define WM8903_IRQ_POL_SHIFT 0 /* IRQ_POL */ 1204f1c0a02fSMark Brown #define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */ 1205f1c0a02fSMark Brown 1206f1c0a02fSMark Brown /* 1207f1c0a02fSMark Brown * R164 (0xA4) - Clock Rate Test 4 1208f1c0a02fSMark Brown */ 1209f1c0a02fSMark Brown #define WM8903_ADC_DIG_MIC 0x0200 /* ADC_DIG_MIC */ 1210f1c0a02fSMark Brown #define WM8903_ADC_DIG_MIC_MASK 0x0200 /* ADC_DIG_MIC */ 1211f1c0a02fSMark Brown #define WM8903_ADC_DIG_MIC_SHIFT 9 /* ADC_DIG_MIC */ 1212f1c0a02fSMark Brown #define WM8903_ADC_DIG_MIC_WIDTH 1 /* ADC_DIG_MIC */ 1213f1c0a02fSMark Brown 1214f1c0a02fSMark Brown /* 1215f1c0a02fSMark Brown * R172 (0xAC) - Analogue Output Bias 0 1216f1c0a02fSMark Brown */ 1217f1c0a02fSMark Brown #define WM8903_PGA_BIAS_MASK 0x0070 /* PGA_BIAS - [6:4] */ 1218f1c0a02fSMark Brown #define WM8903_PGA_BIAS_SHIFT 4 /* PGA_BIAS - [6:4] */ 1219f1c0a02fSMark Brown #define WM8903_PGA_BIAS_WIDTH 3 /* PGA_BIAS - [6:4] */ 1220f1c0a02fSMark Brown 1221f1c0a02fSMark Brown #endif 1222