1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2a91eb199SMark Brown /* 3a91eb199SMark Brown * wm8904.h -- WM8904 ASoC driver 4a91eb199SMark Brown * 5a91eb199SMark Brown * Copyright 2009 Wolfson Microelectronics, plc 6a91eb199SMark Brown * 7a91eb199SMark Brown * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8a91eb199SMark Brown */ 9a91eb199SMark Brown 10a91eb199SMark Brown #ifndef _WM8904_H 11a91eb199SMark Brown #define _WM8904_H 12a91eb199SMark Brown 1313409d27SMichael Walle #define WM8904_CLK_AUTO 0 14a91eb199SMark Brown #define WM8904_CLK_MCLK 1 15a91eb199SMark Brown #define WM8904_CLK_FLL 2 16a91eb199SMark Brown 17a91eb199SMark Brown #define WM8904_FLL_MCLK 1 18a91eb199SMark Brown #define WM8904_FLL_BCLK 2 19a91eb199SMark Brown #define WM8904_FLL_LRCLK 3 20a91eb199SMark Brown #define WM8904_FLL_FREE_RUNNING 4 21a91eb199SMark Brown 22a91eb199SMark Brown /* 23a91eb199SMark Brown * Register values. 24a91eb199SMark Brown */ 25a91eb199SMark Brown #define WM8904_SW_RESET_AND_ID 0x00 26a91eb199SMark Brown #define WM8904_REVISION 0x01 27a91eb199SMark Brown #define WM8904_BIAS_CONTROL_0 0x04 28a91eb199SMark Brown #define WM8904_VMID_CONTROL_0 0x05 29a91eb199SMark Brown #define WM8904_MIC_BIAS_CONTROL_0 0x06 30a91eb199SMark Brown #define WM8904_MIC_BIAS_CONTROL_1 0x07 31a91eb199SMark Brown #define WM8904_ANALOGUE_DAC_0 0x08 32a91eb199SMark Brown #define WM8904_MIC_FILTER_CONTROL 0x09 33a91eb199SMark Brown #define WM8904_ANALOGUE_ADC_0 0x0A 34a91eb199SMark Brown #define WM8904_POWER_MANAGEMENT_0 0x0C 35a91eb199SMark Brown #define WM8904_POWER_MANAGEMENT_2 0x0E 36a91eb199SMark Brown #define WM8904_POWER_MANAGEMENT_3 0x0F 37a91eb199SMark Brown #define WM8904_POWER_MANAGEMENT_6 0x12 38a91eb199SMark Brown #define WM8904_CLOCK_RATES_0 0x14 39a91eb199SMark Brown #define WM8904_CLOCK_RATES_1 0x15 40a91eb199SMark Brown #define WM8904_CLOCK_RATES_2 0x16 41a91eb199SMark Brown #define WM8904_AUDIO_INTERFACE_0 0x18 42a91eb199SMark Brown #define WM8904_AUDIO_INTERFACE_1 0x19 43a91eb199SMark Brown #define WM8904_AUDIO_INTERFACE_2 0x1A 44a91eb199SMark Brown #define WM8904_AUDIO_INTERFACE_3 0x1B 45a91eb199SMark Brown #define WM8904_DAC_DIGITAL_VOLUME_LEFT 0x1E 46a91eb199SMark Brown #define WM8904_DAC_DIGITAL_VOLUME_RIGHT 0x1F 47a91eb199SMark Brown #define WM8904_DAC_DIGITAL_0 0x20 48a91eb199SMark Brown #define WM8904_DAC_DIGITAL_1 0x21 49a91eb199SMark Brown #define WM8904_ADC_DIGITAL_VOLUME_LEFT 0x24 50a91eb199SMark Brown #define WM8904_ADC_DIGITAL_VOLUME_RIGHT 0x25 51a91eb199SMark Brown #define WM8904_ADC_DIGITAL_0 0x26 52a91eb199SMark Brown #define WM8904_DIGITAL_MICROPHONE_0 0x27 53a91eb199SMark Brown #define WM8904_DRC_0 0x28 54a91eb199SMark Brown #define WM8904_DRC_1 0x29 55a91eb199SMark Brown #define WM8904_DRC_2 0x2A 56a91eb199SMark Brown #define WM8904_DRC_3 0x2B 57a91eb199SMark Brown #define WM8904_ANALOGUE_LEFT_INPUT_0 0x2C 58a91eb199SMark Brown #define WM8904_ANALOGUE_RIGHT_INPUT_0 0x2D 59a91eb199SMark Brown #define WM8904_ANALOGUE_LEFT_INPUT_1 0x2E 60a91eb199SMark Brown #define WM8904_ANALOGUE_RIGHT_INPUT_1 0x2F 61a91eb199SMark Brown #define WM8904_ANALOGUE_OUT1_LEFT 0x39 62a91eb199SMark Brown #define WM8904_ANALOGUE_OUT1_RIGHT 0x3A 63a91eb199SMark Brown #define WM8904_ANALOGUE_OUT2_LEFT 0x3B 64a91eb199SMark Brown #define WM8904_ANALOGUE_OUT2_RIGHT 0x3C 65a91eb199SMark Brown #define WM8904_ANALOGUE_OUT12_ZC 0x3D 66a91eb199SMark Brown #define WM8904_DC_SERVO_0 0x43 67a91eb199SMark Brown #define WM8904_DC_SERVO_1 0x44 68a91eb199SMark Brown #define WM8904_DC_SERVO_2 0x45 69a91eb199SMark Brown #define WM8904_DC_SERVO_4 0x47 70a91eb199SMark Brown #define WM8904_DC_SERVO_5 0x48 71a91eb199SMark Brown #define WM8904_DC_SERVO_6 0x49 72a91eb199SMark Brown #define WM8904_DC_SERVO_7 0x4A 73a91eb199SMark Brown #define WM8904_DC_SERVO_8 0x4B 74a91eb199SMark Brown #define WM8904_DC_SERVO_9 0x4C 75a91eb199SMark Brown #define WM8904_DC_SERVO_READBACK_0 0x4D 76a91eb199SMark Brown #define WM8904_ANALOGUE_HP_0 0x5A 77a91eb199SMark Brown #define WM8904_ANALOGUE_LINEOUT_0 0x5E 78a91eb199SMark Brown #define WM8904_CHARGE_PUMP_0 0x62 79a91eb199SMark Brown #define WM8904_CLASS_W_0 0x68 80a91eb199SMark Brown #define WM8904_WRITE_SEQUENCER_0 0x6C 81a91eb199SMark Brown #define WM8904_WRITE_SEQUENCER_1 0x6D 82a91eb199SMark Brown #define WM8904_WRITE_SEQUENCER_2 0x6E 83a91eb199SMark Brown #define WM8904_WRITE_SEQUENCER_3 0x6F 84a91eb199SMark Brown #define WM8904_WRITE_SEQUENCER_4 0x70 85a91eb199SMark Brown #define WM8904_FLL_CONTROL_1 0x74 86a91eb199SMark Brown #define WM8904_FLL_CONTROL_2 0x75 87a91eb199SMark Brown #define WM8904_FLL_CONTROL_3 0x76 88a91eb199SMark Brown #define WM8904_FLL_CONTROL_4 0x77 89a91eb199SMark Brown #define WM8904_FLL_CONTROL_5 0x78 90a91eb199SMark Brown #define WM8904_GPIO_CONTROL_1 0x79 91a91eb199SMark Brown #define WM8904_GPIO_CONTROL_2 0x7A 92a91eb199SMark Brown #define WM8904_GPIO_CONTROL_3 0x7B 93a91eb199SMark Brown #define WM8904_GPIO_CONTROL_4 0x7C 94a91eb199SMark Brown #define WM8904_DIGITAL_PULLS 0x7E 95a91eb199SMark Brown #define WM8904_INTERRUPT_STATUS 0x7F 96a91eb199SMark Brown #define WM8904_INTERRUPT_STATUS_MASK 0x80 97a91eb199SMark Brown #define WM8904_INTERRUPT_POLARITY 0x81 98a91eb199SMark Brown #define WM8904_INTERRUPT_DEBOUNCE 0x82 99a91eb199SMark Brown #define WM8904_EQ1 0x86 100a91eb199SMark Brown #define WM8904_EQ2 0x87 101a91eb199SMark Brown #define WM8904_EQ3 0x88 102a91eb199SMark Brown #define WM8904_EQ4 0x89 103a91eb199SMark Brown #define WM8904_EQ5 0x8A 104a91eb199SMark Brown #define WM8904_EQ6 0x8B 105a91eb199SMark Brown #define WM8904_EQ7 0x8C 106a91eb199SMark Brown #define WM8904_EQ8 0x8D 107a91eb199SMark Brown #define WM8904_EQ9 0x8E 108a91eb199SMark Brown #define WM8904_EQ10 0x8F 109a91eb199SMark Brown #define WM8904_EQ11 0x90 110a91eb199SMark Brown #define WM8904_EQ12 0x91 111a91eb199SMark Brown #define WM8904_EQ13 0x92 112a91eb199SMark Brown #define WM8904_EQ14 0x93 113a91eb199SMark Brown #define WM8904_EQ15 0x94 114a91eb199SMark Brown #define WM8904_EQ16 0x95 115a91eb199SMark Brown #define WM8904_EQ17 0x96 116a91eb199SMark Brown #define WM8904_EQ18 0x97 117a91eb199SMark Brown #define WM8904_EQ19 0x98 118a91eb199SMark Brown #define WM8904_EQ20 0x99 119a91eb199SMark Brown #define WM8904_EQ21 0x9A 120a91eb199SMark Brown #define WM8904_EQ22 0x9B 121a91eb199SMark Brown #define WM8904_EQ23 0x9C 122a91eb199SMark Brown #define WM8904_EQ24 0x9D 123a91eb199SMark Brown #define WM8904_CONTROL_INTERFACE_TEST_1 0xA1 1249b85fc90SMark Brown #define WM8904_ADC_TEST_0 0xC6 125a91eb199SMark Brown #define WM8904_ANALOGUE_OUTPUT_BIAS_0 0xCC 126a91eb199SMark Brown #define WM8904_FLL_NCO_TEST_0 0xF7 127a91eb199SMark Brown #define WM8904_FLL_NCO_TEST_1 0xF8 128a91eb199SMark Brown 129a91eb199SMark Brown #define WM8904_REGISTER_COUNT 101 130a91eb199SMark Brown #define WM8904_MAX_REGISTER 0xF8 131a91eb199SMark Brown 132a91eb199SMark Brown /* 133a91eb199SMark Brown * Field Definitions. 134a91eb199SMark Brown */ 135a91eb199SMark Brown 136a91eb199SMark Brown /* 137a91eb199SMark Brown * R0 (0x00) - SW Reset and ID 138a91eb199SMark Brown */ 139a91eb199SMark Brown #define WM8904_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 140a91eb199SMark Brown #define WM8904_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 141a91eb199SMark Brown #define WM8904_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 142a91eb199SMark Brown 143a91eb199SMark Brown /* 144a91eb199SMark Brown * R1 (0x01) - Revision 145a91eb199SMark Brown */ 146a91eb199SMark Brown #define WM8904_REVISION_MASK 0x000F /* REVISION - [3:0] */ 147a91eb199SMark Brown #define WM8904_REVISION_SHIFT 0 /* REVISION - [3:0] */ 148a91eb199SMark Brown #define WM8904_REVISION_WIDTH 16 /* REVISION - [3:0] */ 149a91eb199SMark Brown 150a91eb199SMark Brown /* 151a91eb199SMark Brown * R4 (0x04) - Bias Control 0 152a91eb199SMark Brown */ 153a91eb199SMark Brown #define WM8904_POBCTRL 0x0010 /* POBCTRL */ 154a91eb199SMark Brown #define WM8904_POBCTRL_MASK 0x0010 /* POBCTRL */ 155a91eb199SMark Brown #define WM8904_POBCTRL_SHIFT 4 /* POBCTRL */ 156a91eb199SMark Brown #define WM8904_POBCTRL_WIDTH 1 /* POBCTRL */ 157a91eb199SMark Brown #define WM8904_ISEL_MASK 0x000C /* ISEL - [3:2] */ 158a91eb199SMark Brown #define WM8904_ISEL_SHIFT 2 /* ISEL - [3:2] */ 159a91eb199SMark Brown #define WM8904_ISEL_WIDTH 2 /* ISEL - [3:2] */ 160a91eb199SMark Brown #define WM8904_STARTUP_BIAS_ENA 0x0002 /* STARTUP_BIAS_ENA */ 161a91eb199SMark Brown #define WM8904_STARTUP_BIAS_ENA_MASK 0x0002 /* STARTUP_BIAS_ENA */ 162a91eb199SMark Brown #define WM8904_STARTUP_BIAS_ENA_SHIFT 1 /* STARTUP_BIAS_ENA */ 163a91eb199SMark Brown #define WM8904_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 164a91eb199SMark Brown #define WM8904_BIAS_ENA 0x0001 /* BIAS_ENA */ 165a91eb199SMark Brown #define WM8904_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ 166a91eb199SMark Brown #define WM8904_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ 167a91eb199SMark Brown #define WM8904_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 168a91eb199SMark Brown 169a91eb199SMark Brown /* 170a91eb199SMark Brown * R5 (0x05) - VMID Control 0 171a91eb199SMark Brown */ 172a91eb199SMark Brown #define WM8904_VMID_BUF_ENA 0x0040 /* VMID_BUF_ENA */ 173a91eb199SMark Brown #define WM8904_VMID_BUF_ENA_MASK 0x0040 /* VMID_BUF_ENA */ 174a91eb199SMark Brown #define WM8904_VMID_BUF_ENA_SHIFT 6 /* VMID_BUF_ENA */ 175a91eb199SMark Brown #define WM8904_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 176a91eb199SMark Brown #define WM8904_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */ 177a91eb199SMark Brown #define WM8904_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */ 178a91eb199SMark Brown #define WM8904_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */ 179a91eb199SMark Brown #define WM8904_VMID_ENA 0x0001 /* VMID_ENA */ 180a91eb199SMark Brown #define WM8904_VMID_ENA_MASK 0x0001 /* VMID_ENA */ 181a91eb199SMark Brown #define WM8904_VMID_ENA_SHIFT 0 /* VMID_ENA */ 182a91eb199SMark Brown #define WM8904_VMID_ENA_WIDTH 1 /* VMID_ENA */ 183a91eb199SMark Brown 184a91eb199SMark Brown /* 185a91eb199SMark Brown * R8 (0x08) - Analogue DAC 0 186a91eb199SMark Brown */ 187a91eb199SMark Brown #define WM8904_DAC_BIAS_SEL_MASK 0x0018 /* DAC_BIAS_SEL - [4:3] */ 188a91eb199SMark Brown #define WM8904_DAC_BIAS_SEL_SHIFT 3 /* DAC_BIAS_SEL - [4:3] */ 189a91eb199SMark Brown #define WM8904_DAC_BIAS_SEL_WIDTH 2 /* DAC_BIAS_SEL - [4:3] */ 190a91eb199SMark Brown #define WM8904_DAC_VMID_BIAS_SEL_MASK 0x0006 /* DAC_VMID_BIAS_SEL - [2:1] */ 191a91eb199SMark Brown #define WM8904_DAC_VMID_BIAS_SEL_SHIFT 1 /* DAC_VMID_BIAS_SEL - [2:1] */ 192a91eb199SMark Brown #define WM8904_DAC_VMID_BIAS_SEL_WIDTH 2 /* DAC_VMID_BIAS_SEL - [2:1] */ 193a91eb199SMark Brown 194a91eb199SMark Brown /* 195a91eb199SMark Brown * R9 (0x09) - mic Filter Control 196a91eb199SMark Brown */ 197a91eb199SMark Brown #define WM8904_MIC_DET_SET_THRESHOLD_MASK 0xF000 /* MIC_DET_SET_THRESHOLD - [15:12] */ 198a91eb199SMark Brown #define WM8904_MIC_DET_SET_THRESHOLD_SHIFT 12 /* MIC_DET_SET_THRESHOLD - [15:12] */ 199a91eb199SMark Brown #define WM8904_MIC_DET_SET_THRESHOLD_WIDTH 4 /* MIC_DET_SET_THRESHOLD - [15:12] */ 200a91eb199SMark Brown #define WM8904_MIC_DET_RESET_THRESHOLD_MASK 0x0F00 /* MIC_DET_RESET_THRESHOLD - [11:8] */ 201a91eb199SMark Brown #define WM8904_MIC_DET_RESET_THRESHOLD_SHIFT 8 /* MIC_DET_RESET_THRESHOLD - [11:8] */ 202a91eb199SMark Brown #define WM8904_MIC_DET_RESET_THRESHOLD_WIDTH 4 /* MIC_DET_RESET_THRESHOLD - [11:8] */ 203a91eb199SMark Brown #define WM8904_MIC_SHORT_SET_THRESHOLD_MASK 0x00F0 /* MIC_SHORT_SET_THRESHOLD - [7:4] */ 204a91eb199SMark Brown #define WM8904_MIC_SHORT_SET_THRESHOLD_SHIFT 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */ 205a91eb199SMark Brown #define WM8904_MIC_SHORT_SET_THRESHOLD_WIDTH 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */ 206a91eb199SMark Brown #define WM8904_MIC_SHORT_RESET_THRESHOLD_MASK 0x000F /* MIC_SHORT_RESET_THRESHOLD - [3:0] */ 207a91eb199SMark Brown #define WM8904_MIC_SHORT_RESET_THRESHOLD_SHIFT 0 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */ 208a91eb199SMark Brown #define WM8904_MIC_SHORT_RESET_THRESHOLD_WIDTH 4 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */ 209a91eb199SMark Brown 210a91eb199SMark Brown /* 211a91eb199SMark Brown * R10 (0x0A) - Analogue ADC 0 212a91eb199SMark Brown */ 213a91eb199SMark Brown #define WM8904_ADC_OSR128 0x0001 /* ADC_OSR128 */ 214a91eb199SMark Brown #define WM8904_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */ 215a91eb199SMark Brown #define WM8904_ADC_OSR128_SHIFT 0 /* ADC_OSR128 */ 216a91eb199SMark Brown #define WM8904_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 217a91eb199SMark Brown 218a91eb199SMark Brown /* 219a91eb199SMark Brown * R12 (0x0C) - Power Management 0 220a91eb199SMark Brown */ 221a91eb199SMark Brown #define WM8904_INL_ENA 0x0002 /* INL_ENA */ 222a91eb199SMark Brown #define WM8904_INL_ENA_MASK 0x0002 /* INL_ENA */ 223a91eb199SMark Brown #define WM8904_INL_ENA_SHIFT 1 /* INL_ENA */ 224a91eb199SMark Brown #define WM8904_INL_ENA_WIDTH 1 /* INL_ENA */ 225a91eb199SMark Brown #define WM8904_INR_ENA 0x0001 /* INR_ENA */ 226a91eb199SMark Brown #define WM8904_INR_ENA_MASK 0x0001 /* INR_ENA */ 227a91eb199SMark Brown #define WM8904_INR_ENA_SHIFT 0 /* INR_ENA */ 228a91eb199SMark Brown #define WM8904_INR_ENA_WIDTH 1 /* INR_ENA */ 229a91eb199SMark Brown 230a91eb199SMark Brown /* 231a91eb199SMark Brown * R14 (0x0E) - Power Management 2 232a91eb199SMark Brown */ 233a91eb199SMark Brown #define WM8904_HPL_PGA_ENA 0x0002 /* HPL_PGA_ENA */ 234a91eb199SMark Brown #define WM8904_HPL_PGA_ENA_MASK 0x0002 /* HPL_PGA_ENA */ 235a91eb199SMark Brown #define WM8904_HPL_PGA_ENA_SHIFT 1 /* HPL_PGA_ENA */ 236a91eb199SMark Brown #define WM8904_HPL_PGA_ENA_WIDTH 1 /* HPL_PGA_ENA */ 237a91eb199SMark Brown #define WM8904_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */ 238a91eb199SMark Brown #define WM8904_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */ 239a91eb199SMark Brown #define WM8904_HPR_PGA_ENA_SHIFT 0 /* HPR_PGA_ENA */ 240a91eb199SMark Brown #define WM8904_HPR_PGA_ENA_WIDTH 1 /* HPR_PGA_ENA */ 241a91eb199SMark Brown 242a91eb199SMark Brown /* 243a91eb199SMark Brown * R15 (0x0F) - Power Management 3 244a91eb199SMark Brown */ 245a91eb199SMark Brown #define WM8904_LINEOUTL_PGA_ENA 0x0002 /* LINEOUTL_PGA_ENA */ 246a91eb199SMark Brown #define WM8904_LINEOUTL_PGA_ENA_MASK 0x0002 /* LINEOUTL_PGA_ENA */ 247a91eb199SMark Brown #define WM8904_LINEOUTL_PGA_ENA_SHIFT 1 /* LINEOUTL_PGA_ENA */ 248a91eb199SMark Brown #define WM8904_LINEOUTL_PGA_ENA_WIDTH 1 /* LINEOUTL_PGA_ENA */ 249a91eb199SMark Brown #define WM8904_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */ 250a91eb199SMark Brown #define WM8904_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */ 251a91eb199SMark Brown #define WM8904_LINEOUTR_PGA_ENA_SHIFT 0 /* LINEOUTR_PGA_ENA */ 252a91eb199SMark Brown #define WM8904_LINEOUTR_PGA_ENA_WIDTH 1 /* LINEOUTR_PGA_ENA */ 253a91eb199SMark Brown 254a91eb199SMark Brown /* 255a91eb199SMark Brown * R18 (0x12) - Power Management 6 256a91eb199SMark Brown */ 257a91eb199SMark Brown #define WM8904_DACL_ENA 0x0008 /* DACL_ENA */ 258a91eb199SMark Brown #define WM8904_DACL_ENA_MASK 0x0008 /* DACL_ENA */ 259a91eb199SMark Brown #define WM8904_DACL_ENA_SHIFT 3 /* DACL_ENA */ 260a91eb199SMark Brown #define WM8904_DACL_ENA_WIDTH 1 /* DACL_ENA */ 261a91eb199SMark Brown #define WM8904_DACR_ENA 0x0004 /* DACR_ENA */ 262a91eb199SMark Brown #define WM8904_DACR_ENA_MASK 0x0004 /* DACR_ENA */ 263a91eb199SMark Brown #define WM8904_DACR_ENA_SHIFT 2 /* DACR_ENA */ 264a91eb199SMark Brown #define WM8904_DACR_ENA_WIDTH 1 /* DACR_ENA */ 265a91eb199SMark Brown #define WM8904_ADCL_ENA 0x0002 /* ADCL_ENA */ 266a91eb199SMark Brown #define WM8904_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 267a91eb199SMark Brown #define WM8904_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 268a91eb199SMark Brown #define WM8904_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 269a91eb199SMark Brown #define WM8904_ADCR_ENA 0x0001 /* ADCR_ENA */ 270a91eb199SMark Brown #define WM8904_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 271a91eb199SMark Brown #define WM8904_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 272a91eb199SMark Brown #define WM8904_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 273a91eb199SMark Brown 274a91eb199SMark Brown /* 275a91eb199SMark Brown * R20 (0x14) - Clock Rates 0 276a91eb199SMark Brown */ 277a91eb199SMark Brown #define WM8904_TOCLK_RATE_DIV16 0x4000 /* TOCLK_RATE_DIV16 */ 278a91eb199SMark Brown #define WM8904_TOCLK_RATE_DIV16_MASK 0x4000 /* TOCLK_RATE_DIV16 */ 279a91eb199SMark Brown #define WM8904_TOCLK_RATE_DIV16_SHIFT 14 /* TOCLK_RATE_DIV16 */ 280a91eb199SMark Brown #define WM8904_TOCLK_RATE_DIV16_WIDTH 1 /* TOCLK_RATE_DIV16 */ 281a91eb199SMark Brown #define WM8904_TOCLK_RATE_X4 0x2000 /* TOCLK_RATE_X4 */ 282a91eb199SMark Brown #define WM8904_TOCLK_RATE_X4_MASK 0x2000 /* TOCLK_RATE_X4 */ 283a91eb199SMark Brown #define WM8904_TOCLK_RATE_X4_SHIFT 13 /* TOCLK_RATE_X4 */ 284a91eb199SMark Brown #define WM8904_TOCLK_RATE_X4_WIDTH 1 /* TOCLK_RATE_X4 */ 285a91eb199SMark Brown #define WM8904_SR_MODE 0x1000 /* SR_MODE */ 286a91eb199SMark Brown #define WM8904_SR_MODE_MASK 0x1000 /* SR_MODE */ 287a91eb199SMark Brown #define WM8904_SR_MODE_SHIFT 12 /* SR_MODE */ 288a91eb199SMark Brown #define WM8904_SR_MODE_WIDTH 1 /* SR_MODE */ 289a91eb199SMark Brown #define WM8904_MCLK_DIV 0x0001 /* MCLK_DIV */ 290a91eb199SMark Brown #define WM8904_MCLK_DIV_MASK 0x0001 /* MCLK_DIV */ 291a91eb199SMark Brown #define WM8904_MCLK_DIV_SHIFT 0 /* MCLK_DIV */ 292a91eb199SMark Brown #define WM8904_MCLK_DIV_WIDTH 1 /* MCLK_DIV */ 293a91eb199SMark Brown 294a91eb199SMark Brown /* 295a91eb199SMark Brown * R21 (0x15) - Clock Rates 1 296a91eb199SMark Brown */ 297a91eb199SMark Brown #define WM8904_CLK_SYS_RATE_MASK 0x3C00 /* CLK_SYS_RATE - [13:10] */ 298a91eb199SMark Brown #define WM8904_CLK_SYS_RATE_SHIFT 10 /* CLK_SYS_RATE - [13:10] */ 299a91eb199SMark Brown #define WM8904_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [13:10] */ 300a91eb199SMark Brown #define WM8904_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */ 301a91eb199SMark Brown #define WM8904_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */ 302a91eb199SMark Brown #define WM8904_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */ 303a91eb199SMark Brown 304a91eb199SMark Brown /* 305a91eb199SMark Brown * R22 (0x16) - Clock Rates 2 306a91eb199SMark Brown */ 307a91eb199SMark Brown #define WM8904_MCLK_INV 0x8000 /* MCLK_INV */ 308a91eb199SMark Brown #define WM8904_MCLK_INV_MASK 0x8000 /* MCLK_INV */ 309a91eb199SMark Brown #define WM8904_MCLK_INV_SHIFT 15 /* MCLK_INV */ 310a91eb199SMark Brown #define WM8904_MCLK_INV_WIDTH 1 /* MCLK_INV */ 311a91eb199SMark Brown #define WM8904_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */ 312a91eb199SMark Brown #define WM8904_SYSCLK_SRC_MASK 0x4000 /* SYSCLK_SRC */ 313a91eb199SMark Brown #define WM8904_SYSCLK_SRC_SHIFT 14 /* SYSCLK_SRC */ 314a91eb199SMark Brown #define WM8904_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ 315a91eb199SMark Brown #define WM8904_TOCLK_RATE 0x1000 /* TOCLK_RATE */ 316a91eb199SMark Brown #define WM8904_TOCLK_RATE_MASK 0x1000 /* TOCLK_RATE */ 317a91eb199SMark Brown #define WM8904_TOCLK_RATE_SHIFT 12 /* TOCLK_RATE */ 318a91eb199SMark Brown #define WM8904_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */ 319a91eb199SMark Brown #define WM8904_OPCLK_ENA 0x0008 /* OPCLK_ENA */ 320a91eb199SMark Brown #define WM8904_OPCLK_ENA_MASK 0x0008 /* OPCLK_ENA */ 321a91eb199SMark Brown #define WM8904_OPCLK_ENA_SHIFT 3 /* OPCLK_ENA */ 322a91eb199SMark Brown #define WM8904_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 323a91eb199SMark Brown #define WM8904_CLK_SYS_ENA 0x0004 /* CLK_SYS_ENA */ 324a91eb199SMark Brown #define WM8904_CLK_SYS_ENA_MASK 0x0004 /* CLK_SYS_ENA */ 325a91eb199SMark Brown #define WM8904_CLK_SYS_ENA_SHIFT 2 /* CLK_SYS_ENA */ 326a91eb199SMark Brown #define WM8904_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ 327a91eb199SMark Brown #define WM8904_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */ 328a91eb199SMark Brown #define WM8904_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */ 329a91eb199SMark Brown #define WM8904_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */ 330a91eb199SMark Brown #define WM8904_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ 331a91eb199SMark Brown #define WM8904_TOCLK_ENA 0x0001 /* TOCLK_ENA */ 332a91eb199SMark Brown #define WM8904_TOCLK_ENA_MASK 0x0001 /* TOCLK_ENA */ 333a91eb199SMark Brown #define WM8904_TOCLK_ENA_SHIFT 0 /* TOCLK_ENA */ 334a91eb199SMark Brown #define WM8904_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 335a91eb199SMark Brown 336a91eb199SMark Brown /* 337a91eb199SMark Brown * R24 (0x18) - Audio Interface 0 338a91eb199SMark Brown */ 339a91eb199SMark Brown #define WM8904_DACL_DATINV 0x1000 /* DACL_DATINV */ 340a91eb199SMark Brown #define WM8904_DACL_DATINV_MASK 0x1000 /* DACL_DATINV */ 341a91eb199SMark Brown #define WM8904_DACL_DATINV_SHIFT 12 /* DACL_DATINV */ 342a91eb199SMark Brown #define WM8904_DACL_DATINV_WIDTH 1 /* DACL_DATINV */ 343a91eb199SMark Brown #define WM8904_DACR_DATINV 0x0800 /* DACR_DATINV */ 344a91eb199SMark Brown #define WM8904_DACR_DATINV_MASK 0x0800 /* DACR_DATINV */ 345a91eb199SMark Brown #define WM8904_DACR_DATINV_SHIFT 11 /* DACR_DATINV */ 346a91eb199SMark Brown #define WM8904_DACR_DATINV_WIDTH 1 /* DACR_DATINV */ 347a91eb199SMark Brown #define WM8904_DAC_BOOST_MASK 0x0600 /* DAC_BOOST - [10:9] */ 348a91eb199SMark Brown #define WM8904_DAC_BOOST_SHIFT 9 /* DAC_BOOST - [10:9] */ 349a91eb199SMark Brown #define WM8904_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [10:9] */ 350a91eb199SMark Brown #define WM8904_LOOPBACK 0x0100 /* LOOPBACK */ 351a91eb199SMark Brown #define WM8904_LOOPBACK_MASK 0x0100 /* LOOPBACK */ 352a91eb199SMark Brown #define WM8904_LOOPBACK_SHIFT 8 /* LOOPBACK */ 353a91eb199SMark Brown #define WM8904_LOOPBACK_WIDTH 1 /* LOOPBACK */ 354a91eb199SMark Brown #define WM8904_AIFADCL_SRC 0x0080 /* AIFADCL_SRC */ 355a91eb199SMark Brown #define WM8904_AIFADCL_SRC_MASK 0x0080 /* AIFADCL_SRC */ 356a91eb199SMark Brown #define WM8904_AIFADCL_SRC_SHIFT 7 /* AIFADCL_SRC */ 357a91eb199SMark Brown #define WM8904_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */ 358a91eb199SMark Brown #define WM8904_AIFADCR_SRC 0x0040 /* AIFADCR_SRC */ 359a91eb199SMark Brown #define WM8904_AIFADCR_SRC_MASK 0x0040 /* AIFADCR_SRC */ 360a91eb199SMark Brown #define WM8904_AIFADCR_SRC_SHIFT 6 /* AIFADCR_SRC */ 361a91eb199SMark Brown #define WM8904_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */ 362a91eb199SMark Brown #define WM8904_AIFDACL_SRC 0x0020 /* AIFDACL_SRC */ 363a91eb199SMark Brown #define WM8904_AIFDACL_SRC_MASK 0x0020 /* AIFDACL_SRC */ 364a91eb199SMark Brown #define WM8904_AIFDACL_SRC_SHIFT 5 /* AIFDACL_SRC */ 365a91eb199SMark Brown #define WM8904_AIFDACL_SRC_WIDTH 1 /* AIFDACL_SRC */ 366a91eb199SMark Brown #define WM8904_AIFDACR_SRC 0x0010 /* AIFDACR_SRC */ 367a91eb199SMark Brown #define WM8904_AIFDACR_SRC_MASK 0x0010 /* AIFDACR_SRC */ 368a91eb199SMark Brown #define WM8904_AIFDACR_SRC_SHIFT 4 /* AIFDACR_SRC */ 369a91eb199SMark Brown #define WM8904_AIFDACR_SRC_WIDTH 1 /* AIFDACR_SRC */ 370a91eb199SMark Brown #define WM8904_ADC_COMP 0x0008 /* ADC_COMP */ 371a91eb199SMark Brown #define WM8904_ADC_COMP_MASK 0x0008 /* ADC_COMP */ 372a91eb199SMark Brown #define WM8904_ADC_COMP_SHIFT 3 /* ADC_COMP */ 373a91eb199SMark Brown #define WM8904_ADC_COMP_WIDTH 1 /* ADC_COMP */ 374a91eb199SMark Brown #define WM8904_ADC_COMPMODE 0x0004 /* ADC_COMPMODE */ 375a91eb199SMark Brown #define WM8904_ADC_COMPMODE_MASK 0x0004 /* ADC_COMPMODE */ 376a91eb199SMark Brown #define WM8904_ADC_COMPMODE_SHIFT 2 /* ADC_COMPMODE */ 377a91eb199SMark Brown #define WM8904_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */ 378a91eb199SMark Brown #define WM8904_DAC_COMP 0x0002 /* DAC_COMP */ 379a91eb199SMark Brown #define WM8904_DAC_COMP_MASK 0x0002 /* DAC_COMP */ 380a91eb199SMark Brown #define WM8904_DAC_COMP_SHIFT 1 /* DAC_COMP */ 381a91eb199SMark Brown #define WM8904_DAC_COMP_WIDTH 1 /* DAC_COMP */ 382a91eb199SMark Brown #define WM8904_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */ 383a91eb199SMark Brown #define WM8904_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */ 384a91eb199SMark Brown #define WM8904_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */ 385a91eb199SMark Brown #define WM8904_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ 386a91eb199SMark Brown 387a91eb199SMark Brown /* 388a91eb199SMark Brown * R25 (0x19) - Audio Interface 1 389a91eb199SMark Brown */ 390a91eb199SMark Brown #define WM8904_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ 391a91eb199SMark Brown #define WM8904_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */ 392a91eb199SMark Brown #define WM8904_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */ 393a91eb199SMark Brown #define WM8904_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */ 394a91eb199SMark Brown #define WM8904_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ 395a91eb199SMark Brown #define WM8904_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */ 396a91eb199SMark Brown #define WM8904_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */ 397a91eb199SMark Brown #define WM8904_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */ 398a91eb199SMark Brown #define WM8904_AIFADC_TDM 0x0800 /* AIFADC_TDM */ 399a91eb199SMark Brown #define WM8904_AIFADC_TDM_MASK 0x0800 /* AIFADC_TDM */ 400a91eb199SMark Brown #define WM8904_AIFADC_TDM_SHIFT 11 /* AIFADC_TDM */ 401a91eb199SMark Brown #define WM8904_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */ 402a91eb199SMark Brown #define WM8904_AIFADC_TDM_CHAN 0x0400 /* AIFADC_TDM_CHAN */ 403a91eb199SMark Brown #define WM8904_AIFADC_TDM_CHAN_MASK 0x0400 /* AIFADC_TDM_CHAN */ 404a91eb199SMark Brown #define WM8904_AIFADC_TDM_CHAN_SHIFT 10 /* AIFADC_TDM_CHAN */ 405a91eb199SMark Brown #define WM8904_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */ 406a91eb199SMark Brown #define WM8904_AIF_TRIS 0x0100 /* AIF_TRIS */ 407a91eb199SMark Brown #define WM8904_AIF_TRIS_MASK 0x0100 /* AIF_TRIS */ 408a91eb199SMark Brown #define WM8904_AIF_TRIS_SHIFT 8 /* AIF_TRIS */ 409a91eb199SMark Brown #define WM8904_AIF_TRIS_WIDTH 1 /* AIF_TRIS */ 410a91eb199SMark Brown #define WM8904_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */ 411a91eb199SMark Brown #define WM8904_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */ 412a91eb199SMark Brown #define WM8904_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */ 413a91eb199SMark Brown #define WM8904_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */ 414a91eb199SMark Brown #define WM8904_BCLK_DIR 0x0040 /* BCLK_DIR */ 415a91eb199SMark Brown #define WM8904_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */ 416a91eb199SMark Brown #define WM8904_BCLK_DIR_SHIFT 6 /* BCLK_DIR */ 417a91eb199SMark Brown #define WM8904_BCLK_DIR_WIDTH 1 /* BCLK_DIR */ 418a91eb199SMark Brown #define WM8904_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */ 419a91eb199SMark Brown #define WM8904_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */ 420a91eb199SMark Brown #define WM8904_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */ 421a91eb199SMark Brown #define WM8904_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */ 422a91eb199SMark Brown #define WM8904_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */ 423a91eb199SMark Brown #define WM8904_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */ 424a91eb199SMark Brown #define WM8904_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */ 425a91eb199SMark Brown #define WM8904_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */ 426a91eb199SMark Brown #define WM8904_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */ 427a91eb199SMark Brown #define WM8904_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */ 428a91eb199SMark Brown 429a91eb199SMark Brown /* 430a91eb199SMark Brown * R26 (0x1A) - Audio Interface 2 431a91eb199SMark Brown */ 432a91eb199SMark Brown #define WM8904_OPCLK_DIV_MASK 0x0F00 /* OPCLK_DIV - [11:8] */ 433a91eb199SMark Brown #define WM8904_OPCLK_DIV_SHIFT 8 /* OPCLK_DIV - [11:8] */ 434a91eb199SMark Brown #define WM8904_OPCLK_DIV_WIDTH 4 /* OPCLK_DIV - [11:8] */ 435a91eb199SMark Brown #define WM8904_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */ 436a91eb199SMark Brown #define WM8904_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */ 437a91eb199SMark Brown #define WM8904_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */ 438a91eb199SMark Brown 439a91eb199SMark Brown /* 440a91eb199SMark Brown * R27 (0x1B) - Audio Interface 3 441a91eb199SMark Brown */ 442a91eb199SMark Brown #define WM8904_LRCLK_DIR 0x0800 /* LRCLK_DIR */ 443a91eb199SMark Brown #define WM8904_LRCLK_DIR_MASK 0x0800 /* LRCLK_DIR */ 444a91eb199SMark Brown #define WM8904_LRCLK_DIR_SHIFT 11 /* LRCLK_DIR */ 445a91eb199SMark Brown #define WM8904_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */ 446a91eb199SMark Brown #define WM8904_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */ 447a91eb199SMark Brown #define WM8904_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */ 448a91eb199SMark Brown #define WM8904_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */ 449a91eb199SMark Brown 450a91eb199SMark Brown /* 451a91eb199SMark Brown * R30 (0x1E) - DAC Digital Volume Left 452a91eb199SMark Brown */ 453a91eb199SMark Brown #define WM8904_DAC_VU 0x0100 /* DAC_VU */ 454a91eb199SMark Brown #define WM8904_DAC_VU_MASK 0x0100 /* DAC_VU */ 455a91eb199SMark Brown #define WM8904_DAC_VU_SHIFT 8 /* DAC_VU */ 456a91eb199SMark Brown #define WM8904_DAC_VU_WIDTH 1 /* DAC_VU */ 457a91eb199SMark Brown #define WM8904_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ 458a91eb199SMark Brown #define WM8904_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */ 459a91eb199SMark Brown #define WM8904_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */ 460a91eb199SMark Brown 461a91eb199SMark Brown /* 462a91eb199SMark Brown * R31 (0x1F) - DAC Digital Volume Right 463a91eb199SMark Brown */ 464a91eb199SMark Brown #define WM8904_DAC_VU 0x0100 /* DAC_VU */ 465a91eb199SMark Brown #define WM8904_DAC_VU_MASK 0x0100 /* DAC_VU */ 466a91eb199SMark Brown #define WM8904_DAC_VU_SHIFT 8 /* DAC_VU */ 467a91eb199SMark Brown #define WM8904_DAC_VU_WIDTH 1 /* DAC_VU */ 468a91eb199SMark Brown #define WM8904_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ 469a91eb199SMark Brown #define WM8904_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */ 470a91eb199SMark Brown #define WM8904_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */ 471a91eb199SMark Brown 472a91eb199SMark Brown /* 473a91eb199SMark Brown * R32 (0x20) - DAC Digital 0 474a91eb199SMark Brown */ 475a91eb199SMark Brown #define WM8904_ADCL_DAC_SVOL_MASK 0x0F00 /* ADCL_DAC_SVOL - [11:8] */ 476a91eb199SMark Brown #define WM8904_ADCL_DAC_SVOL_SHIFT 8 /* ADCL_DAC_SVOL - [11:8] */ 477a91eb199SMark Brown #define WM8904_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [11:8] */ 478a91eb199SMark Brown #define WM8904_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ 479a91eb199SMark Brown #define WM8904_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ 480a91eb199SMark Brown #define WM8904_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ 481a91eb199SMark Brown #define WM8904_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ 482a91eb199SMark Brown #define WM8904_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ 483a91eb199SMark Brown #define WM8904_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ 484a91eb199SMark Brown #define WM8904_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */ 485a91eb199SMark Brown #define WM8904_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */ 486a91eb199SMark Brown #define WM8904_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */ 487a91eb199SMark Brown 488a91eb199SMark Brown /* 489a91eb199SMark Brown * R33 (0x21) - DAC Digital 1 490a91eb199SMark Brown */ 491a91eb199SMark Brown #define WM8904_DAC_MONO 0x1000 /* DAC_MONO */ 492a91eb199SMark Brown #define WM8904_DAC_MONO_MASK 0x1000 /* DAC_MONO */ 493a91eb199SMark Brown #define WM8904_DAC_MONO_SHIFT 12 /* DAC_MONO */ 494a91eb199SMark Brown #define WM8904_DAC_MONO_WIDTH 1 /* DAC_MONO */ 495a91eb199SMark Brown #define WM8904_DAC_SB_FILT 0x0800 /* DAC_SB_FILT */ 496a91eb199SMark Brown #define WM8904_DAC_SB_FILT_MASK 0x0800 /* DAC_SB_FILT */ 497a91eb199SMark Brown #define WM8904_DAC_SB_FILT_SHIFT 11 /* DAC_SB_FILT */ 498a91eb199SMark Brown #define WM8904_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */ 499a91eb199SMark Brown #define WM8904_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */ 500a91eb199SMark Brown #define WM8904_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */ 501a91eb199SMark Brown #define WM8904_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */ 502a91eb199SMark Brown #define WM8904_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 503a91eb199SMark Brown #define WM8904_DAC_UNMUTE_RAMP 0x0200 /* DAC_UNMUTE_RAMP */ 504a91eb199SMark Brown #define WM8904_DAC_UNMUTE_RAMP_MASK 0x0200 /* DAC_UNMUTE_RAMP */ 505a91eb199SMark Brown #define WM8904_DAC_UNMUTE_RAMP_SHIFT 9 /* DAC_UNMUTE_RAMP */ 506a91eb199SMark Brown #define WM8904_DAC_UNMUTE_RAMP_WIDTH 1 /* DAC_UNMUTE_RAMP */ 507a91eb199SMark Brown #define WM8904_DAC_OSR128 0x0040 /* DAC_OSR128 */ 508a91eb199SMark Brown #define WM8904_DAC_OSR128_MASK 0x0040 /* DAC_OSR128 */ 509a91eb199SMark Brown #define WM8904_DAC_OSR128_SHIFT 6 /* DAC_OSR128 */ 510a91eb199SMark Brown #define WM8904_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 511a91eb199SMark Brown #define WM8904_DAC_MUTE 0x0008 /* DAC_MUTE */ 512a91eb199SMark Brown #define WM8904_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ 513a91eb199SMark Brown #define WM8904_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ 514a91eb199SMark Brown #define WM8904_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ 515a91eb199SMark Brown #define WM8904_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 516a91eb199SMark Brown #define WM8904_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 517a91eb199SMark Brown #define WM8904_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 518a91eb199SMark Brown 519a91eb199SMark Brown /* 520a91eb199SMark Brown * R36 (0x24) - ADC Digital Volume Left 521a91eb199SMark Brown */ 522a91eb199SMark Brown #define WM8904_ADC_VU 0x0100 /* ADC_VU */ 523a91eb199SMark Brown #define WM8904_ADC_VU_MASK 0x0100 /* ADC_VU */ 524a91eb199SMark Brown #define WM8904_ADC_VU_SHIFT 8 /* ADC_VU */ 525a91eb199SMark Brown #define WM8904_ADC_VU_WIDTH 1 /* ADC_VU */ 526a91eb199SMark Brown #define WM8904_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ 527a91eb199SMark Brown #define WM8904_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */ 528a91eb199SMark Brown #define WM8904_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */ 529a91eb199SMark Brown 530a91eb199SMark Brown /* 531a91eb199SMark Brown * R37 (0x25) - ADC Digital Volume Right 532a91eb199SMark Brown */ 533a91eb199SMark Brown #define WM8904_ADC_VU 0x0100 /* ADC_VU */ 534a91eb199SMark Brown #define WM8904_ADC_VU_MASK 0x0100 /* ADC_VU */ 535a91eb199SMark Brown #define WM8904_ADC_VU_SHIFT 8 /* ADC_VU */ 536a91eb199SMark Brown #define WM8904_ADC_VU_WIDTH 1 /* ADC_VU */ 537a91eb199SMark Brown #define WM8904_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ 538a91eb199SMark Brown #define WM8904_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */ 539a91eb199SMark Brown #define WM8904_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */ 540a91eb199SMark Brown 541a91eb199SMark Brown /* 542a91eb199SMark Brown * R38 (0x26) - ADC Digital 0 543a91eb199SMark Brown */ 544a91eb199SMark Brown #define WM8904_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */ 545a91eb199SMark Brown #define WM8904_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */ 546a91eb199SMark Brown #define WM8904_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */ 547a91eb199SMark Brown #define WM8904_ADC_HPF 0x0010 /* ADC_HPF */ 548a91eb199SMark Brown #define WM8904_ADC_HPF_MASK 0x0010 /* ADC_HPF */ 549a91eb199SMark Brown #define WM8904_ADC_HPF_SHIFT 4 /* ADC_HPF */ 550a91eb199SMark Brown #define WM8904_ADC_HPF_WIDTH 1 /* ADC_HPF */ 551a91eb199SMark Brown #define WM8904_ADCL_DATINV 0x0002 /* ADCL_DATINV */ 552a91eb199SMark Brown #define WM8904_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */ 553a91eb199SMark Brown #define WM8904_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */ 554a91eb199SMark Brown #define WM8904_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */ 555a91eb199SMark Brown #define WM8904_ADCR_DATINV 0x0001 /* ADCR_DATINV */ 556a91eb199SMark Brown #define WM8904_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */ 557a91eb199SMark Brown #define WM8904_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */ 558a91eb199SMark Brown #define WM8904_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */ 559a91eb199SMark Brown 560a91eb199SMark Brown /* 561a91eb199SMark Brown * R39 (0x27) - Digital Microphone 0 562a91eb199SMark Brown */ 563a91eb199SMark Brown #define WM8904_DMIC_ENA 0x1000 /* DMIC_ENA */ 564a91eb199SMark Brown #define WM8904_DMIC_ENA_MASK 0x1000 /* DMIC_ENA */ 565a91eb199SMark Brown #define WM8904_DMIC_ENA_SHIFT 12 /* DMIC_ENA */ 566a91eb199SMark Brown #define WM8904_DMIC_ENA_WIDTH 1 /* DMIC_ENA */ 567a91eb199SMark Brown #define WM8904_DMIC_SRC 0x0800 /* DMIC_SRC */ 568a91eb199SMark Brown #define WM8904_DMIC_SRC_MASK 0x0800 /* DMIC_SRC */ 569a91eb199SMark Brown #define WM8904_DMIC_SRC_SHIFT 11 /* DMIC_SRC */ 570a91eb199SMark Brown #define WM8904_DMIC_SRC_WIDTH 1 /* DMIC_SRC */ 571a91eb199SMark Brown 572a91eb199SMark Brown /* 573a91eb199SMark Brown * R40 (0x28) - DRC 0 574a91eb199SMark Brown */ 575a91eb199SMark Brown #define WM8904_DRC_ENA 0x8000 /* DRC_ENA */ 576a91eb199SMark Brown #define WM8904_DRC_ENA_MASK 0x8000 /* DRC_ENA */ 577a91eb199SMark Brown #define WM8904_DRC_ENA_SHIFT 15 /* DRC_ENA */ 578a91eb199SMark Brown #define WM8904_DRC_ENA_WIDTH 1 /* DRC_ENA */ 579a91eb199SMark Brown #define WM8904_DRC_DAC_PATH 0x4000 /* DRC_DAC_PATH */ 580a91eb199SMark Brown #define WM8904_DRC_DAC_PATH_MASK 0x4000 /* DRC_DAC_PATH */ 581a91eb199SMark Brown #define WM8904_DRC_DAC_PATH_SHIFT 14 /* DRC_DAC_PATH */ 582a91eb199SMark Brown #define WM8904_DRC_DAC_PATH_WIDTH 1 /* DRC_DAC_PATH */ 583a91eb199SMark Brown #define WM8904_DRC_GS_HYST_LVL_MASK 0x1800 /* DRC_GS_HYST_LVL - [12:11] */ 584a91eb199SMark Brown #define WM8904_DRC_GS_HYST_LVL_SHIFT 11 /* DRC_GS_HYST_LVL - [12:11] */ 585a91eb199SMark Brown #define WM8904_DRC_GS_HYST_LVL_WIDTH 2 /* DRC_GS_HYST_LVL - [12:11] */ 586a91eb199SMark Brown #define WM8904_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */ 587a91eb199SMark Brown #define WM8904_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */ 588a91eb199SMark Brown #define WM8904_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */ 589a91eb199SMark Brown #define WM8904_DRC_FF_DELAY 0x0020 /* DRC_FF_DELAY */ 590a91eb199SMark Brown #define WM8904_DRC_FF_DELAY_MASK 0x0020 /* DRC_FF_DELAY */ 591a91eb199SMark Brown #define WM8904_DRC_FF_DELAY_SHIFT 5 /* DRC_FF_DELAY */ 592a91eb199SMark Brown #define WM8904_DRC_FF_DELAY_WIDTH 1 /* DRC_FF_DELAY */ 593a91eb199SMark Brown #define WM8904_DRC_GS_ENA 0x0008 /* DRC_GS_ENA */ 594a91eb199SMark Brown #define WM8904_DRC_GS_ENA_MASK 0x0008 /* DRC_GS_ENA */ 595a91eb199SMark Brown #define WM8904_DRC_GS_ENA_SHIFT 3 /* DRC_GS_ENA */ 596a91eb199SMark Brown #define WM8904_DRC_GS_ENA_WIDTH 1 /* DRC_GS_ENA */ 597a91eb199SMark Brown #define WM8904_DRC_QR 0x0004 /* DRC_QR */ 598a91eb199SMark Brown #define WM8904_DRC_QR_MASK 0x0004 /* DRC_QR */ 599a91eb199SMark Brown #define WM8904_DRC_QR_SHIFT 2 /* DRC_QR */ 600a91eb199SMark Brown #define WM8904_DRC_QR_WIDTH 1 /* DRC_QR */ 601a91eb199SMark Brown #define WM8904_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */ 602a91eb199SMark Brown #define WM8904_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */ 603a91eb199SMark Brown #define WM8904_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */ 604a91eb199SMark Brown #define WM8904_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ 605a91eb199SMark Brown #define WM8904_DRC_GS_HYST 0x0001 /* DRC_GS_HYST */ 606a91eb199SMark Brown #define WM8904_DRC_GS_HYST_MASK 0x0001 /* DRC_GS_HYST */ 607a91eb199SMark Brown #define WM8904_DRC_GS_HYST_SHIFT 0 /* DRC_GS_HYST */ 608a91eb199SMark Brown #define WM8904_DRC_GS_HYST_WIDTH 1 /* DRC_GS_HYST */ 609a91eb199SMark Brown 610a91eb199SMark Brown /* 611a91eb199SMark Brown * R41 (0x29) - DRC 1 612a91eb199SMark Brown */ 613a91eb199SMark Brown #define WM8904_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */ 614a91eb199SMark Brown #define WM8904_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */ 615a91eb199SMark Brown #define WM8904_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */ 616a91eb199SMark Brown #define WM8904_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */ 617a91eb199SMark Brown #define WM8904_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */ 618a91eb199SMark Brown #define WM8904_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */ 619a91eb199SMark Brown #define WM8904_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */ 620a91eb199SMark Brown #define WM8904_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */ 621a91eb199SMark Brown #define WM8904_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */ 622a91eb199SMark Brown #define WM8904_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */ 623a91eb199SMark Brown #define WM8904_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */ 624a91eb199SMark Brown #define WM8904_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */ 625a91eb199SMark Brown #define WM8904_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */ 626a91eb199SMark Brown #define WM8904_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */ 627a91eb199SMark Brown #define WM8904_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */ 628a91eb199SMark Brown #define WM8904_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 629a91eb199SMark Brown #define WM8904_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 630a91eb199SMark Brown #define WM8904_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 631a91eb199SMark Brown 632a91eb199SMark Brown /* 633a91eb199SMark Brown * R42 (0x2A) - DRC 2 634a91eb199SMark Brown */ 635a91eb199SMark Brown #define WM8904_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ 636a91eb199SMark Brown #define WM8904_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ 637a91eb199SMark Brown #define WM8904_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ 638a91eb199SMark Brown #define WM8904_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ 639a91eb199SMark Brown #define WM8904_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ 640a91eb199SMark Brown #define WM8904_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ 641a91eb199SMark Brown 642a91eb199SMark Brown /* 643a91eb199SMark Brown * R43 (0x2B) - DRC 3 644a91eb199SMark Brown */ 645a91eb199SMark Brown #define WM8904_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ 646a91eb199SMark Brown #define WM8904_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ 647a91eb199SMark Brown #define WM8904_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ 648a91eb199SMark Brown #define WM8904_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ 649a91eb199SMark Brown #define WM8904_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ 650a91eb199SMark Brown #define WM8904_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ 651a91eb199SMark Brown 652a91eb199SMark Brown /* 653a91eb199SMark Brown * R44 (0x2C) - Analogue Left Input 0 654a91eb199SMark Brown */ 655a91eb199SMark Brown #define WM8904_LINMUTE 0x0080 /* LINMUTE */ 656a91eb199SMark Brown #define WM8904_LINMUTE_MASK 0x0080 /* LINMUTE */ 657a91eb199SMark Brown #define WM8904_LINMUTE_SHIFT 7 /* LINMUTE */ 658a91eb199SMark Brown #define WM8904_LINMUTE_WIDTH 1 /* LINMUTE */ 659a91eb199SMark Brown #define WM8904_LIN_VOL_MASK 0x001F /* LIN_VOL - [4:0] */ 660a91eb199SMark Brown #define WM8904_LIN_VOL_SHIFT 0 /* LIN_VOL - [4:0] */ 661a91eb199SMark Brown #define WM8904_LIN_VOL_WIDTH 5 /* LIN_VOL - [4:0] */ 662a91eb199SMark Brown 663a91eb199SMark Brown /* 664a91eb199SMark Brown * R45 (0x2D) - Analogue Right Input 0 665a91eb199SMark Brown */ 666a91eb199SMark Brown #define WM8904_RINMUTE 0x0080 /* RINMUTE */ 667a91eb199SMark Brown #define WM8904_RINMUTE_MASK 0x0080 /* RINMUTE */ 668a91eb199SMark Brown #define WM8904_RINMUTE_SHIFT 7 /* RINMUTE */ 669a91eb199SMark Brown #define WM8904_RINMUTE_WIDTH 1 /* RINMUTE */ 670a91eb199SMark Brown #define WM8904_RIN_VOL_MASK 0x001F /* RIN_VOL - [4:0] */ 671a91eb199SMark Brown #define WM8904_RIN_VOL_SHIFT 0 /* RIN_VOL - [4:0] */ 672a91eb199SMark Brown #define WM8904_RIN_VOL_WIDTH 5 /* RIN_VOL - [4:0] */ 673a91eb199SMark Brown 674a91eb199SMark Brown /* 675a91eb199SMark Brown * R46 (0x2E) - Analogue Left Input 1 676a91eb199SMark Brown */ 677a91eb199SMark Brown #define WM8904_INL_CM_ENA 0x0040 /* INL_CM_ENA */ 678a91eb199SMark Brown #define WM8904_INL_CM_ENA_MASK 0x0040 /* INL_CM_ENA */ 679a91eb199SMark Brown #define WM8904_INL_CM_ENA_SHIFT 6 /* INL_CM_ENA */ 680a91eb199SMark Brown #define WM8904_INL_CM_ENA_WIDTH 1 /* INL_CM_ENA */ 681a91eb199SMark Brown #define WM8904_L_IP_SEL_N_MASK 0x0030 /* L_IP_SEL_N - [5:4] */ 682a91eb199SMark Brown #define WM8904_L_IP_SEL_N_SHIFT 4 /* L_IP_SEL_N - [5:4] */ 683a91eb199SMark Brown #define WM8904_L_IP_SEL_N_WIDTH 2 /* L_IP_SEL_N - [5:4] */ 684a91eb199SMark Brown #define WM8904_L_IP_SEL_P_MASK 0x000C /* L_IP_SEL_P - [3:2] */ 685a91eb199SMark Brown #define WM8904_L_IP_SEL_P_SHIFT 2 /* L_IP_SEL_P - [3:2] */ 686a91eb199SMark Brown #define WM8904_L_IP_SEL_P_WIDTH 2 /* L_IP_SEL_P - [3:2] */ 687a91eb199SMark Brown #define WM8904_L_MODE_MASK 0x0003 /* L_MODE - [1:0] */ 688a91eb199SMark Brown #define WM8904_L_MODE_SHIFT 0 /* L_MODE - [1:0] */ 689a91eb199SMark Brown #define WM8904_L_MODE_WIDTH 2 /* L_MODE - [1:0] */ 690a91eb199SMark Brown 691a91eb199SMark Brown /* 692a91eb199SMark Brown * R47 (0x2F) - Analogue Right Input 1 693a91eb199SMark Brown */ 694a91eb199SMark Brown #define WM8904_INR_CM_ENA 0x0040 /* INR_CM_ENA */ 695a91eb199SMark Brown #define WM8904_INR_CM_ENA_MASK 0x0040 /* INR_CM_ENA */ 696a91eb199SMark Brown #define WM8904_INR_CM_ENA_SHIFT 6 /* INR_CM_ENA */ 697a91eb199SMark Brown #define WM8904_INR_CM_ENA_WIDTH 1 /* INR_CM_ENA */ 698a91eb199SMark Brown #define WM8904_R_IP_SEL_N_MASK 0x0030 /* R_IP_SEL_N - [5:4] */ 699a91eb199SMark Brown #define WM8904_R_IP_SEL_N_SHIFT 4 /* R_IP_SEL_N - [5:4] */ 700a91eb199SMark Brown #define WM8904_R_IP_SEL_N_WIDTH 2 /* R_IP_SEL_N - [5:4] */ 701a91eb199SMark Brown #define WM8904_R_IP_SEL_P_MASK 0x000C /* R_IP_SEL_P - [3:2] */ 702a91eb199SMark Brown #define WM8904_R_IP_SEL_P_SHIFT 2 /* R_IP_SEL_P - [3:2] */ 703a91eb199SMark Brown #define WM8904_R_IP_SEL_P_WIDTH 2 /* R_IP_SEL_P - [3:2] */ 704a91eb199SMark Brown #define WM8904_R_MODE_MASK 0x0003 /* R_MODE - [1:0] */ 705a91eb199SMark Brown #define WM8904_R_MODE_SHIFT 0 /* R_MODE - [1:0] */ 706a91eb199SMark Brown #define WM8904_R_MODE_WIDTH 2 /* R_MODE - [1:0] */ 707a91eb199SMark Brown 708a91eb199SMark Brown /* 709a91eb199SMark Brown * R57 (0x39) - Analogue OUT1 Left 710a91eb199SMark Brown */ 711a91eb199SMark Brown #define WM8904_HPOUTL_MUTE 0x0100 /* HPOUTL_MUTE */ 712a91eb199SMark Brown #define WM8904_HPOUTL_MUTE_MASK 0x0100 /* HPOUTL_MUTE */ 713a91eb199SMark Brown #define WM8904_HPOUTL_MUTE_SHIFT 8 /* HPOUTL_MUTE */ 714a91eb199SMark Brown #define WM8904_HPOUTL_MUTE_WIDTH 1 /* HPOUTL_MUTE */ 715a91eb199SMark Brown #define WM8904_HPOUT_VU 0x0080 /* HPOUT_VU */ 716a91eb199SMark Brown #define WM8904_HPOUT_VU_MASK 0x0080 /* HPOUT_VU */ 717a91eb199SMark Brown #define WM8904_HPOUT_VU_SHIFT 7 /* HPOUT_VU */ 718a91eb199SMark Brown #define WM8904_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ 719a91eb199SMark Brown #define WM8904_HPOUTLZC 0x0040 /* HPOUTLZC */ 720a91eb199SMark Brown #define WM8904_HPOUTLZC_MASK 0x0040 /* HPOUTLZC */ 721a91eb199SMark Brown #define WM8904_HPOUTLZC_SHIFT 6 /* HPOUTLZC */ 722a91eb199SMark Brown #define WM8904_HPOUTLZC_WIDTH 1 /* HPOUTLZC */ 723a91eb199SMark Brown #define WM8904_HPOUTL_VOL_MASK 0x003F /* HPOUTL_VOL - [5:0] */ 724a91eb199SMark Brown #define WM8904_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [5:0] */ 725a91eb199SMark Brown #define WM8904_HPOUTL_VOL_WIDTH 6 /* HPOUTL_VOL - [5:0] */ 726a91eb199SMark Brown 727a91eb199SMark Brown /* 728a91eb199SMark Brown * R58 (0x3A) - Analogue OUT1 Right 729a91eb199SMark Brown */ 730a91eb199SMark Brown #define WM8904_HPOUTR_MUTE 0x0100 /* HPOUTR_MUTE */ 731a91eb199SMark Brown #define WM8904_HPOUTR_MUTE_MASK 0x0100 /* HPOUTR_MUTE */ 732a91eb199SMark Brown #define WM8904_HPOUTR_MUTE_SHIFT 8 /* HPOUTR_MUTE */ 733a91eb199SMark Brown #define WM8904_HPOUTR_MUTE_WIDTH 1 /* HPOUTR_MUTE */ 734a91eb199SMark Brown #define WM8904_HPOUT_VU 0x0080 /* HPOUT_VU */ 735a91eb199SMark Brown #define WM8904_HPOUT_VU_MASK 0x0080 /* HPOUT_VU */ 736a91eb199SMark Brown #define WM8904_HPOUT_VU_SHIFT 7 /* HPOUT_VU */ 737a91eb199SMark Brown #define WM8904_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ 738a91eb199SMark Brown #define WM8904_HPOUTRZC 0x0040 /* HPOUTRZC */ 739a91eb199SMark Brown #define WM8904_HPOUTRZC_MASK 0x0040 /* HPOUTRZC */ 740a91eb199SMark Brown #define WM8904_HPOUTRZC_SHIFT 6 /* HPOUTRZC */ 741a91eb199SMark Brown #define WM8904_HPOUTRZC_WIDTH 1 /* HPOUTRZC */ 742a91eb199SMark Brown #define WM8904_HPOUTR_VOL_MASK 0x003F /* HPOUTR_VOL - [5:0] */ 743a91eb199SMark Brown #define WM8904_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [5:0] */ 744a91eb199SMark Brown #define WM8904_HPOUTR_VOL_WIDTH 6 /* HPOUTR_VOL - [5:0] */ 745a91eb199SMark Brown 746a91eb199SMark Brown /* 747a91eb199SMark Brown * R59 (0x3B) - Analogue OUT2 Left 748a91eb199SMark Brown */ 749a91eb199SMark Brown #define WM8904_LINEOUTL_MUTE 0x0100 /* LINEOUTL_MUTE */ 750a91eb199SMark Brown #define WM8904_LINEOUTL_MUTE_MASK 0x0100 /* LINEOUTL_MUTE */ 751a91eb199SMark Brown #define WM8904_LINEOUTL_MUTE_SHIFT 8 /* LINEOUTL_MUTE */ 752a91eb199SMark Brown #define WM8904_LINEOUTL_MUTE_WIDTH 1 /* LINEOUTL_MUTE */ 753a91eb199SMark Brown #define WM8904_LINEOUT_VU 0x0080 /* LINEOUT_VU */ 754a91eb199SMark Brown #define WM8904_LINEOUT_VU_MASK 0x0080 /* LINEOUT_VU */ 755a91eb199SMark Brown #define WM8904_LINEOUT_VU_SHIFT 7 /* LINEOUT_VU */ 756a91eb199SMark Brown #define WM8904_LINEOUT_VU_WIDTH 1 /* LINEOUT_VU */ 757a91eb199SMark Brown #define WM8904_LINEOUTLZC 0x0040 /* LINEOUTLZC */ 758a91eb199SMark Brown #define WM8904_LINEOUTLZC_MASK 0x0040 /* LINEOUTLZC */ 759a91eb199SMark Brown #define WM8904_LINEOUTLZC_SHIFT 6 /* LINEOUTLZC */ 760a91eb199SMark Brown #define WM8904_LINEOUTLZC_WIDTH 1 /* LINEOUTLZC */ 761a91eb199SMark Brown #define WM8904_LINEOUTL_VOL_MASK 0x003F /* LINEOUTL_VOL - [5:0] */ 762a91eb199SMark Brown #define WM8904_LINEOUTL_VOL_SHIFT 0 /* LINEOUTL_VOL - [5:0] */ 763a91eb199SMark Brown #define WM8904_LINEOUTL_VOL_WIDTH 6 /* LINEOUTL_VOL - [5:0] */ 764a91eb199SMark Brown 765a91eb199SMark Brown /* 766a91eb199SMark Brown * R60 (0x3C) - Analogue OUT2 Right 767a91eb199SMark Brown */ 768a91eb199SMark Brown #define WM8904_LINEOUTR_MUTE 0x0100 /* LINEOUTR_MUTE */ 769a91eb199SMark Brown #define WM8904_LINEOUTR_MUTE_MASK 0x0100 /* LINEOUTR_MUTE */ 770a91eb199SMark Brown #define WM8904_LINEOUTR_MUTE_SHIFT 8 /* LINEOUTR_MUTE */ 771a91eb199SMark Brown #define WM8904_LINEOUTR_MUTE_WIDTH 1 /* LINEOUTR_MUTE */ 772a91eb199SMark Brown #define WM8904_LINEOUT_VU 0x0080 /* LINEOUT_VU */ 773a91eb199SMark Brown #define WM8904_LINEOUT_VU_MASK 0x0080 /* LINEOUT_VU */ 774a91eb199SMark Brown #define WM8904_LINEOUT_VU_SHIFT 7 /* LINEOUT_VU */ 775a91eb199SMark Brown #define WM8904_LINEOUT_VU_WIDTH 1 /* LINEOUT_VU */ 776a91eb199SMark Brown #define WM8904_LINEOUTRZC 0x0040 /* LINEOUTRZC */ 777a91eb199SMark Brown #define WM8904_LINEOUTRZC_MASK 0x0040 /* LINEOUTRZC */ 778a91eb199SMark Brown #define WM8904_LINEOUTRZC_SHIFT 6 /* LINEOUTRZC */ 779a91eb199SMark Brown #define WM8904_LINEOUTRZC_WIDTH 1 /* LINEOUTRZC */ 780a91eb199SMark Brown #define WM8904_LINEOUTR_VOL_MASK 0x003F /* LINEOUTR_VOL - [5:0] */ 781a91eb199SMark Brown #define WM8904_LINEOUTR_VOL_SHIFT 0 /* LINEOUTR_VOL - [5:0] */ 782a91eb199SMark Brown #define WM8904_LINEOUTR_VOL_WIDTH 6 /* LINEOUTR_VOL - [5:0] */ 783a91eb199SMark Brown 784a91eb199SMark Brown /* 785a91eb199SMark Brown * R61 (0x3D) - Analogue OUT12 ZC 786a91eb199SMark Brown */ 787a91eb199SMark Brown #define WM8904_HPL_BYP_ENA 0x0008 /* HPL_BYP_ENA */ 788a91eb199SMark Brown #define WM8904_HPL_BYP_ENA_MASK 0x0008 /* HPL_BYP_ENA */ 789a91eb199SMark Brown #define WM8904_HPL_BYP_ENA_SHIFT 3 /* HPL_BYP_ENA */ 790a91eb199SMark Brown #define WM8904_HPL_BYP_ENA_WIDTH 1 /* HPL_BYP_ENA */ 791a91eb199SMark Brown #define WM8904_HPR_BYP_ENA 0x0004 /* HPR_BYP_ENA */ 792a91eb199SMark Brown #define WM8904_HPR_BYP_ENA_MASK 0x0004 /* HPR_BYP_ENA */ 793a91eb199SMark Brown #define WM8904_HPR_BYP_ENA_SHIFT 2 /* HPR_BYP_ENA */ 794a91eb199SMark Brown #define WM8904_HPR_BYP_ENA_WIDTH 1 /* HPR_BYP_ENA */ 795a91eb199SMark Brown #define WM8904_LINEOUTL_BYP_ENA 0x0002 /* LINEOUTL_BYP_ENA */ 796a91eb199SMark Brown #define WM8904_LINEOUTL_BYP_ENA_MASK 0x0002 /* LINEOUTL_BYP_ENA */ 797a91eb199SMark Brown #define WM8904_LINEOUTL_BYP_ENA_SHIFT 1 /* LINEOUTL_BYP_ENA */ 798a91eb199SMark Brown #define WM8904_LINEOUTL_BYP_ENA_WIDTH 1 /* LINEOUTL_BYP_ENA */ 799a91eb199SMark Brown #define WM8904_LINEOUTR_BYP_ENA 0x0001 /* LINEOUTR_BYP_ENA */ 800a91eb199SMark Brown #define WM8904_LINEOUTR_BYP_ENA_MASK 0x0001 /* LINEOUTR_BYP_ENA */ 801a91eb199SMark Brown #define WM8904_LINEOUTR_BYP_ENA_SHIFT 0 /* LINEOUTR_BYP_ENA */ 802a91eb199SMark Brown #define WM8904_LINEOUTR_BYP_ENA_WIDTH 1 /* LINEOUTR_BYP_ENA */ 803a91eb199SMark Brown 804a91eb199SMark Brown /* 805a91eb199SMark Brown * R67 (0x43) - DC Servo 0 806a91eb199SMark Brown */ 807a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ 808a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ 809a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ 810a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ 811a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ 812a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ 813a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ 814a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ 815a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 816a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 817a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 818a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 819a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 820a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 821a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 822a91eb199SMark Brown #define WM8904_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 823a91eb199SMark Brown 824a91eb199SMark Brown /* 825a91eb199SMark Brown * R68 (0x44) - DC Servo 1 826a91eb199SMark Brown */ 827a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ 828a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ 829a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ 830a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ 831a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ 832a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ 833a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ 834a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ 835a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 836a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 837a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 838a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 839a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 840a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 841a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 842a91eb199SMark Brown #define WM8904_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 843a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ 844a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ 845a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ 846a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ 847a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ 848a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ 849a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ 850a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ 851a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 852a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 853a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 854a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 855a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 856a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 857a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 858a91eb199SMark Brown #define WM8904_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 859a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ 860a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ 861a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ 862a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ 863a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ 864a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ 865a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ 866a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ 867a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 868a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 869a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 870a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 871a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 872a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 873a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 874a91eb199SMark Brown #define WM8904_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 875a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ 876a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ 877a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ 878a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ 879a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ 880a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ 881a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ 882a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ 883a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ 884a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ 885a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ 886a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 887a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ 888a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ 889a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ 890a91eb199SMark Brown #define WM8904_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 891a91eb199SMark Brown 892a91eb199SMark Brown /* 893a91eb199SMark Brown * R69 (0x45) - DC Servo 2 894a91eb199SMark Brown */ 895a91eb199SMark Brown #define WM8904_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ 896a91eb199SMark Brown #define WM8904_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ 897a91eb199SMark Brown #define WM8904_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ 898a91eb199SMark Brown #define WM8904_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 899a91eb199SMark Brown #define WM8904_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 900a91eb199SMark Brown #define WM8904_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 901a91eb199SMark Brown 902a91eb199SMark Brown /* 903a91eb199SMark Brown * R71 (0x47) - DC Servo 4 904a91eb199SMark Brown */ 905a91eb199SMark Brown #define WM8904_DCS_SERIES_NO_23_MASK 0x007F /* DCS_SERIES_NO_23 - [6:0] */ 906a91eb199SMark Brown #define WM8904_DCS_SERIES_NO_23_SHIFT 0 /* DCS_SERIES_NO_23 - [6:0] */ 907a91eb199SMark Brown #define WM8904_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [6:0] */ 908a91eb199SMark Brown 909a91eb199SMark Brown /* 910a91eb199SMark Brown * R72 (0x48) - DC Servo 5 911a91eb199SMark Brown */ 912a91eb199SMark Brown #define WM8904_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ 913a91eb199SMark Brown #define WM8904_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ 914a91eb199SMark Brown #define WM8904_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ 915a91eb199SMark Brown 916a91eb199SMark Brown /* 917a91eb199SMark Brown * R73 (0x49) - DC Servo 6 918a91eb199SMark Brown */ 919a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_3_MASK 0x00FF /* DCS_DAC_WR_VAL_3 - [7:0] */ 920a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_3_SHIFT 0 /* DCS_DAC_WR_VAL_3 - [7:0] */ 921a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [7:0] */ 922a91eb199SMark Brown 923a91eb199SMark Brown /* 924a91eb199SMark Brown * R74 (0x4A) - DC Servo 7 925a91eb199SMark Brown */ 926a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ 927a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ 928a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ 929a91eb199SMark Brown 930a91eb199SMark Brown /* 931a91eb199SMark Brown * R75 (0x4B) - DC Servo 8 932a91eb199SMark Brown */ 933a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_1_MASK 0x00FF /* DCS_DAC_WR_VAL_1 - [7:0] */ 934a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_1_SHIFT 0 /* DCS_DAC_WR_VAL_1 - [7:0] */ 935a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [7:0] */ 936a91eb199SMark Brown 937a91eb199SMark Brown /* 938a91eb199SMark Brown * R76 (0x4C) - DC Servo 9 939a91eb199SMark Brown */ 940a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 941a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 942a91eb199SMark Brown #define WM8904_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 943a91eb199SMark Brown 944a91eb199SMark Brown /* 945a91eb199SMark Brown * R77 (0x4D) - DC Servo Readback 0 946a91eb199SMark Brown */ 947a91eb199SMark Brown #define WM8904_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ 948a91eb199SMark Brown #define WM8904_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ 949a91eb199SMark Brown #define WM8904_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ 950a91eb199SMark Brown #define WM8904_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ 951a91eb199SMark Brown #define WM8904_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 952a91eb199SMark Brown #define WM8904_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 953a91eb199SMark Brown #define WM8904_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ 954a91eb199SMark Brown #define WM8904_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ 955a91eb199SMark Brown #define WM8904_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ 956a91eb199SMark Brown 957a91eb199SMark Brown /* 958a91eb199SMark Brown * R90 (0x5A) - Analogue HP 0 959a91eb199SMark Brown */ 960a91eb199SMark Brown #define WM8904_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ 961a91eb199SMark Brown #define WM8904_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ 962a91eb199SMark Brown #define WM8904_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ 963a91eb199SMark Brown #define WM8904_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ 964a91eb199SMark Brown #define WM8904_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ 965a91eb199SMark Brown #define WM8904_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ 966a91eb199SMark Brown #define WM8904_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ 967a91eb199SMark Brown #define WM8904_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ 968a91eb199SMark Brown #define WM8904_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ 969a91eb199SMark Brown #define WM8904_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ 970a91eb199SMark Brown #define WM8904_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ 971a91eb199SMark Brown #define WM8904_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ 972a91eb199SMark Brown #define WM8904_HPL_ENA 0x0010 /* HPL_ENA */ 973a91eb199SMark Brown #define WM8904_HPL_ENA_MASK 0x0010 /* HPL_ENA */ 974a91eb199SMark Brown #define WM8904_HPL_ENA_SHIFT 4 /* HPL_ENA */ 975a91eb199SMark Brown #define WM8904_HPL_ENA_WIDTH 1 /* HPL_ENA */ 976a91eb199SMark Brown #define WM8904_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ 977a91eb199SMark Brown #define WM8904_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ 978a91eb199SMark Brown #define WM8904_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ 979a91eb199SMark Brown #define WM8904_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ 980a91eb199SMark Brown #define WM8904_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ 981a91eb199SMark Brown #define WM8904_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ 982a91eb199SMark Brown #define WM8904_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ 983a91eb199SMark Brown #define WM8904_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ 984a91eb199SMark Brown #define WM8904_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */ 985a91eb199SMark Brown #define WM8904_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ 986a91eb199SMark Brown #define WM8904_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ 987a91eb199SMark Brown #define WM8904_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ 988a91eb199SMark Brown #define WM8904_HPR_ENA 0x0001 /* HPR_ENA */ 989a91eb199SMark Brown #define WM8904_HPR_ENA_MASK 0x0001 /* HPR_ENA */ 990a91eb199SMark Brown #define WM8904_HPR_ENA_SHIFT 0 /* HPR_ENA */ 991a91eb199SMark Brown #define WM8904_HPR_ENA_WIDTH 1 /* HPR_ENA */ 992a91eb199SMark Brown 993a91eb199SMark Brown /* 994a91eb199SMark Brown * R94 (0x5E) - Analogue Lineout 0 995a91eb199SMark Brown */ 996a91eb199SMark Brown #define WM8904_LINEOUTL_RMV_SHORT 0x0080 /* LINEOUTL_RMV_SHORT */ 997a91eb199SMark Brown #define WM8904_LINEOUTL_RMV_SHORT_MASK 0x0080 /* LINEOUTL_RMV_SHORT */ 998a91eb199SMark Brown #define WM8904_LINEOUTL_RMV_SHORT_SHIFT 7 /* LINEOUTL_RMV_SHORT */ 999a91eb199SMark Brown #define WM8904_LINEOUTL_RMV_SHORT_WIDTH 1 /* LINEOUTL_RMV_SHORT */ 1000a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_OUTP 0x0040 /* LINEOUTL_ENA_OUTP */ 1001a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_OUTP_MASK 0x0040 /* LINEOUTL_ENA_OUTP */ 1002a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_OUTP_SHIFT 6 /* LINEOUTL_ENA_OUTP */ 1003a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_OUTP_WIDTH 1 /* LINEOUTL_ENA_OUTP */ 1004a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_DLY 0x0020 /* LINEOUTL_ENA_DLY */ 1005a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_DLY_MASK 0x0020 /* LINEOUTL_ENA_DLY */ 1006a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_DLY_SHIFT 5 /* LINEOUTL_ENA_DLY */ 1007a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_DLY_WIDTH 1 /* LINEOUTL_ENA_DLY */ 1008a91eb199SMark Brown #define WM8904_LINEOUTL_ENA 0x0010 /* LINEOUTL_ENA */ 1009a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_MASK 0x0010 /* LINEOUTL_ENA */ 1010a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_SHIFT 4 /* LINEOUTL_ENA */ 1011a91eb199SMark Brown #define WM8904_LINEOUTL_ENA_WIDTH 1 /* LINEOUTL_ENA */ 1012a91eb199SMark Brown #define WM8904_LINEOUTR_RMV_SHORT 0x0008 /* LINEOUTR_RMV_SHORT */ 1013a91eb199SMark Brown #define WM8904_LINEOUTR_RMV_SHORT_MASK 0x0008 /* LINEOUTR_RMV_SHORT */ 1014a91eb199SMark Brown #define WM8904_LINEOUTR_RMV_SHORT_SHIFT 3 /* LINEOUTR_RMV_SHORT */ 1015a91eb199SMark Brown #define WM8904_LINEOUTR_RMV_SHORT_WIDTH 1 /* LINEOUTR_RMV_SHORT */ 1016a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_OUTP 0x0004 /* LINEOUTR_ENA_OUTP */ 1017a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_OUTP_MASK 0x0004 /* LINEOUTR_ENA_OUTP */ 1018a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_OUTP_SHIFT 2 /* LINEOUTR_ENA_OUTP */ 1019a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_OUTP_WIDTH 1 /* LINEOUTR_ENA_OUTP */ 1020a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_DLY 0x0002 /* LINEOUTR_ENA_DLY */ 1021a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_DLY_MASK 0x0002 /* LINEOUTR_ENA_DLY */ 1022a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_DLY_SHIFT 1 /* LINEOUTR_ENA_DLY */ 1023a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_DLY_WIDTH 1 /* LINEOUTR_ENA_DLY */ 1024a91eb199SMark Brown #define WM8904_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */ 1025a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */ 1026a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_SHIFT 0 /* LINEOUTR_ENA */ 1027a91eb199SMark Brown #define WM8904_LINEOUTR_ENA_WIDTH 1 /* LINEOUTR_ENA */ 1028a91eb199SMark Brown 1029a91eb199SMark Brown /* 1030a91eb199SMark Brown * R98 (0x62) - Charge Pump 0 1031a91eb199SMark Brown */ 1032a91eb199SMark Brown #define WM8904_CP_ENA 0x0001 /* CP_ENA */ 1033a91eb199SMark Brown #define WM8904_CP_ENA_MASK 0x0001 /* CP_ENA */ 1034a91eb199SMark Brown #define WM8904_CP_ENA_SHIFT 0 /* CP_ENA */ 1035a91eb199SMark Brown #define WM8904_CP_ENA_WIDTH 1 /* CP_ENA */ 1036a91eb199SMark Brown 1037a91eb199SMark Brown /* 1038a91eb199SMark Brown * R104 (0x68) - Class W 0 1039a91eb199SMark Brown */ 1040a91eb199SMark Brown #define WM8904_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ 1041a91eb199SMark Brown #define WM8904_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ 1042a91eb199SMark Brown #define WM8904_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ 1043a91eb199SMark Brown #define WM8904_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ 1044a91eb199SMark Brown 1045a91eb199SMark Brown /* 1046a91eb199SMark Brown * R108 (0x6C) - Write Sequencer 0 1047a91eb199SMark Brown */ 1048a91eb199SMark Brown #define WM8904_WSEQ_ENA 0x0100 /* WSEQ_ENA */ 1049a91eb199SMark Brown #define WM8904_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */ 1050a91eb199SMark Brown #define WM8904_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */ 1051a91eb199SMark Brown #define WM8904_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1052a91eb199SMark Brown #define WM8904_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ 1053a91eb199SMark Brown #define WM8904_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ 1054a91eb199SMark Brown #define WM8904_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ 1055a91eb199SMark Brown 1056a91eb199SMark Brown /* 1057a91eb199SMark Brown * R109 (0x6D) - Write Sequencer 1 1058a91eb199SMark Brown */ 1059a91eb199SMark Brown #define WM8904_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */ 1060a91eb199SMark Brown #define WM8904_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */ 1061a91eb199SMark Brown #define WM8904_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */ 1062a91eb199SMark Brown #define WM8904_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */ 1063a91eb199SMark Brown #define WM8904_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */ 1064a91eb199SMark Brown #define WM8904_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */ 1065a91eb199SMark Brown #define WM8904_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ 1066a91eb199SMark Brown #define WM8904_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ 1067a91eb199SMark Brown #define WM8904_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ 1068a91eb199SMark Brown 1069a91eb199SMark Brown /* 1070a91eb199SMark Brown * R110 (0x6E) - Write Sequencer 2 1071a91eb199SMark Brown */ 1072a91eb199SMark Brown #define WM8904_WSEQ_EOS 0x4000 /* WSEQ_EOS */ 1073a91eb199SMark Brown #define WM8904_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */ 1074a91eb199SMark Brown #define WM8904_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */ 1075a91eb199SMark Brown #define WM8904_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ 1076a91eb199SMark Brown #define WM8904_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */ 1077a91eb199SMark Brown #define WM8904_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */ 1078a91eb199SMark Brown #define WM8904_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */ 1079a91eb199SMark Brown #define WM8904_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ 1080a91eb199SMark Brown #define WM8904_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ 1081a91eb199SMark Brown #define WM8904_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ 1082a91eb199SMark Brown 1083a91eb199SMark Brown /* 1084a91eb199SMark Brown * R111 (0x6F) - Write Sequencer 3 1085a91eb199SMark Brown */ 1086a91eb199SMark Brown #define WM8904_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1087a91eb199SMark Brown #define WM8904_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1088a91eb199SMark Brown #define WM8904_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1089a91eb199SMark Brown #define WM8904_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1090a91eb199SMark Brown #define WM8904_WSEQ_START 0x0100 /* WSEQ_START */ 1091a91eb199SMark Brown #define WM8904_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1092a91eb199SMark Brown #define WM8904_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1093a91eb199SMark Brown #define WM8904_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1094a91eb199SMark Brown #define WM8904_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ 1095a91eb199SMark Brown #define WM8904_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ 1096a91eb199SMark Brown #define WM8904_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ 1097a91eb199SMark Brown 1098a91eb199SMark Brown /* 1099a91eb199SMark Brown * R112 (0x70) - Write Sequencer 4 1100a91eb199SMark Brown */ 1101a91eb199SMark Brown #define WM8904_WSEQ_CURRENT_INDEX_MASK 0x03F0 /* WSEQ_CURRENT_INDEX - [9:4] */ 1102a91eb199SMark Brown #define WM8904_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [9:4] */ 1103a91eb199SMark Brown #define WM8904_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [9:4] */ 1104a91eb199SMark Brown #define WM8904_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 1105a91eb199SMark Brown #define WM8904_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 1106a91eb199SMark Brown #define WM8904_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 1107a91eb199SMark Brown #define WM8904_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1108a91eb199SMark Brown 1109a91eb199SMark Brown /* 1110a91eb199SMark Brown * R116 (0x74) - FLL Control 1 1111a91eb199SMark Brown */ 1112a91eb199SMark Brown #define WM8904_FLL_FRACN_ENA 0x0004 /* FLL_FRACN_ENA */ 1113a91eb199SMark Brown #define WM8904_FLL_FRACN_ENA_MASK 0x0004 /* FLL_FRACN_ENA */ 1114a91eb199SMark Brown #define WM8904_FLL_FRACN_ENA_SHIFT 2 /* FLL_FRACN_ENA */ 1115a91eb199SMark Brown #define WM8904_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */ 1116a91eb199SMark Brown #define WM8904_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ 1117a91eb199SMark Brown #define WM8904_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ 1118a91eb199SMark Brown #define WM8904_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ 1119a91eb199SMark Brown #define WM8904_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ 1120a91eb199SMark Brown #define WM8904_FLL_ENA 0x0001 /* FLL_ENA */ 1121a91eb199SMark Brown #define WM8904_FLL_ENA_MASK 0x0001 /* FLL_ENA */ 1122a91eb199SMark Brown #define WM8904_FLL_ENA_SHIFT 0 /* FLL_ENA */ 1123a91eb199SMark Brown #define WM8904_FLL_ENA_WIDTH 1 /* FLL_ENA */ 1124a91eb199SMark Brown 1125a91eb199SMark Brown /* 1126a91eb199SMark Brown * R117 (0x75) - FLL Control 2 1127a91eb199SMark Brown */ 1128a91eb199SMark Brown #define WM8904_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ 1129a91eb199SMark Brown #define WM8904_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ 1130a91eb199SMark Brown #define WM8904_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ 1131a91eb199SMark Brown #define WM8904_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */ 1132a91eb199SMark Brown #define WM8904_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */ 1133a91eb199SMark Brown #define WM8904_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */ 1134a91eb199SMark Brown #define WM8904_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ 1135a91eb199SMark Brown #define WM8904_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ 1136a91eb199SMark Brown #define WM8904_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ 1137a91eb199SMark Brown 1138a91eb199SMark Brown /* 1139a91eb199SMark Brown * R118 (0x76) - FLL Control 3 1140a91eb199SMark Brown */ 1141a91eb199SMark Brown #define WM8904_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */ 1142a91eb199SMark Brown #define WM8904_FLL_K_SHIFT 0 /* FLL_K - [15:0] */ 1143a91eb199SMark Brown #define WM8904_FLL_K_WIDTH 16 /* FLL_K - [15:0] */ 1144a91eb199SMark Brown 1145a91eb199SMark Brown /* 1146a91eb199SMark Brown * R119 (0x77) - FLL Control 4 1147a91eb199SMark Brown */ 1148a91eb199SMark Brown #define WM8904_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ 1149a91eb199SMark Brown #define WM8904_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ 1150a91eb199SMark Brown #define WM8904_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ 1151a91eb199SMark Brown #define WM8904_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */ 1152a91eb199SMark Brown #define WM8904_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */ 1153a91eb199SMark Brown #define WM8904_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */ 1154a91eb199SMark Brown 1155a91eb199SMark Brown /* 1156a91eb199SMark Brown * R120 (0x78) - FLL Control 5 1157a91eb199SMark Brown */ 1158a91eb199SMark Brown #define WM8904_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */ 1159a91eb199SMark Brown #define WM8904_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */ 1160a91eb199SMark Brown #define WM8904_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */ 1161a91eb199SMark Brown #define WM8904_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */ 1162a91eb199SMark Brown #define WM8904_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */ 1163a91eb199SMark Brown #define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */ 1164a91eb199SMark Brown 1165a91eb199SMark Brown /* 1166a91eb199SMark Brown * R126 (0x7E) - Digital Pulls 1167a91eb199SMark Brown */ 1168a91eb199SMark Brown #define WM8904_MCLK_PU 0x0080 /* MCLK_PU */ 1169a91eb199SMark Brown #define WM8904_MCLK_PU_MASK 0x0080 /* MCLK_PU */ 1170a91eb199SMark Brown #define WM8904_MCLK_PU_SHIFT 7 /* MCLK_PU */ 1171a91eb199SMark Brown #define WM8904_MCLK_PU_WIDTH 1 /* MCLK_PU */ 1172a91eb199SMark Brown #define WM8904_MCLK_PD 0x0040 /* MCLK_PD */ 1173a91eb199SMark Brown #define WM8904_MCLK_PD_MASK 0x0040 /* MCLK_PD */ 1174a91eb199SMark Brown #define WM8904_MCLK_PD_SHIFT 6 /* MCLK_PD */ 1175a91eb199SMark Brown #define WM8904_MCLK_PD_WIDTH 1 /* MCLK_PD */ 1176a91eb199SMark Brown #define WM8904_DACDAT_PU 0x0020 /* DACDAT_PU */ 1177a91eb199SMark Brown #define WM8904_DACDAT_PU_MASK 0x0020 /* DACDAT_PU */ 1178a91eb199SMark Brown #define WM8904_DACDAT_PU_SHIFT 5 /* DACDAT_PU */ 1179a91eb199SMark Brown #define WM8904_DACDAT_PU_WIDTH 1 /* DACDAT_PU */ 1180a91eb199SMark Brown #define WM8904_DACDAT_PD 0x0010 /* DACDAT_PD */ 1181a91eb199SMark Brown #define WM8904_DACDAT_PD_MASK 0x0010 /* DACDAT_PD */ 1182a91eb199SMark Brown #define WM8904_DACDAT_PD_SHIFT 4 /* DACDAT_PD */ 1183a91eb199SMark Brown #define WM8904_DACDAT_PD_WIDTH 1 /* DACDAT_PD */ 1184a91eb199SMark Brown #define WM8904_LRCLK_PU 0x0008 /* LRCLK_PU */ 1185a91eb199SMark Brown #define WM8904_LRCLK_PU_MASK 0x0008 /* LRCLK_PU */ 1186a91eb199SMark Brown #define WM8904_LRCLK_PU_SHIFT 3 /* LRCLK_PU */ 1187a91eb199SMark Brown #define WM8904_LRCLK_PU_WIDTH 1 /* LRCLK_PU */ 1188a91eb199SMark Brown #define WM8904_LRCLK_PD 0x0004 /* LRCLK_PD */ 1189a91eb199SMark Brown #define WM8904_LRCLK_PD_MASK 0x0004 /* LRCLK_PD */ 1190a91eb199SMark Brown #define WM8904_LRCLK_PD_SHIFT 2 /* LRCLK_PD */ 1191a91eb199SMark Brown #define WM8904_LRCLK_PD_WIDTH 1 /* LRCLK_PD */ 1192a91eb199SMark Brown #define WM8904_BCLK_PU 0x0002 /* BCLK_PU */ 1193a91eb199SMark Brown #define WM8904_BCLK_PU_MASK 0x0002 /* BCLK_PU */ 1194a91eb199SMark Brown #define WM8904_BCLK_PU_SHIFT 1 /* BCLK_PU */ 1195a91eb199SMark Brown #define WM8904_BCLK_PU_WIDTH 1 /* BCLK_PU */ 1196a91eb199SMark Brown #define WM8904_BCLK_PD 0x0001 /* BCLK_PD */ 1197a91eb199SMark Brown #define WM8904_BCLK_PD_MASK 0x0001 /* BCLK_PD */ 1198a91eb199SMark Brown #define WM8904_BCLK_PD_SHIFT 0 /* BCLK_PD */ 1199a91eb199SMark Brown #define WM8904_BCLK_PD_WIDTH 1 /* BCLK_PD */ 1200a91eb199SMark Brown 1201a91eb199SMark Brown /* 1202a91eb199SMark Brown * R127 (0x7F) - Interrupt Status 1203a91eb199SMark Brown */ 1204a91eb199SMark Brown #define WM8904_IRQ 0x0400 /* IRQ */ 1205a91eb199SMark Brown #define WM8904_IRQ_MASK 0x0400 /* IRQ */ 1206a91eb199SMark Brown #define WM8904_IRQ_SHIFT 10 /* IRQ */ 1207a91eb199SMark Brown #define WM8904_IRQ_WIDTH 1 /* IRQ */ 1208a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT 0x0200 /* GPIO_BCLK_EINT */ 1209a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_MASK 0x0200 /* GPIO_BCLK_EINT */ 1210a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_SHIFT 9 /* GPIO_BCLK_EINT */ 1211a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_WIDTH 1 /* GPIO_BCLK_EINT */ 1212a91eb199SMark Brown #define WM8904_WSEQ_EINT 0x0100 /* WSEQ_EINT */ 1213a91eb199SMark Brown #define WM8904_WSEQ_EINT_MASK 0x0100 /* WSEQ_EINT */ 1214a91eb199SMark Brown #define WM8904_WSEQ_EINT_SHIFT 8 /* WSEQ_EINT */ 1215a91eb199SMark Brown #define WM8904_WSEQ_EINT_WIDTH 1 /* WSEQ_EINT */ 1216a91eb199SMark Brown #define WM8904_GPIO3_EINT 0x0080 /* GPIO3_EINT */ 1217a91eb199SMark Brown #define WM8904_GPIO3_EINT_MASK 0x0080 /* GPIO3_EINT */ 1218a91eb199SMark Brown #define WM8904_GPIO3_EINT_SHIFT 7 /* GPIO3_EINT */ 1219a91eb199SMark Brown #define WM8904_GPIO3_EINT_WIDTH 1 /* GPIO3_EINT */ 1220a91eb199SMark Brown #define WM8904_GPIO2_EINT 0x0040 /* GPIO2_EINT */ 1221a91eb199SMark Brown #define WM8904_GPIO2_EINT_MASK 0x0040 /* GPIO2_EINT */ 1222a91eb199SMark Brown #define WM8904_GPIO2_EINT_SHIFT 6 /* GPIO2_EINT */ 1223a91eb199SMark Brown #define WM8904_GPIO2_EINT_WIDTH 1 /* GPIO2_EINT */ 1224a91eb199SMark Brown #define WM8904_GPIO1_EINT 0x0020 /* GPIO1_EINT */ 1225a91eb199SMark Brown #define WM8904_GPIO1_EINT_MASK 0x0020 /* GPIO1_EINT */ 1226a91eb199SMark Brown #define WM8904_GPIO1_EINT_SHIFT 5 /* GPIO1_EINT */ 1227a91eb199SMark Brown #define WM8904_GPIO1_EINT_WIDTH 1 /* GPIO1_EINT */ 1228a91eb199SMark Brown #define WM8904_GPI8_EINT 0x0010 /* GPI8_EINT */ 1229a91eb199SMark Brown #define WM8904_GPI8_EINT_MASK 0x0010 /* GPI8_EINT */ 1230a91eb199SMark Brown #define WM8904_GPI8_EINT_SHIFT 4 /* GPI8_EINT */ 1231a91eb199SMark Brown #define WM8904_GPI8_EINT_WIDTH 1 /* GPI8_EINT */ 1232a91eb199SMark Brown #define WM8904_GPI7_EINT 0x0008 /* GPI7_EINT */ 1233a91eb199SMark Brown #define WM8904_GPI7_EINT_MASK 0x0008 /* GPI7_EINT */ 1234a91eb199SMark Brown #define WM8904_GPI7_EINT_SHIFT 3 /* GPI7_EINT */ 1235a91eb199SMark Brown #define WM8904_GPI7_EINT_WIDTH 1 /* GPI7_EINT */ 1236a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */ 1237a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */ 1238a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */ 1239a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ 1240a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT 0x0002 /* MIC_SHRT_EINT */ 1241a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_MASK 0x0002 /* MIC_SHRT_EINT */ 1242a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_SHIFT 1 /* MIC_SHRT_EINT */ 1243a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_WIDTH 1 /* MIC_SHRT_EINT */ 1244a91eb199SMark Brown #define WM8904_MIC_DET_EINT 0x0001 /* MIC_DET_EINT */ 1245a91eb199SMark Brown #define WM8904_MIC_DET_EINT_MASK 0x0001 /* MIC_DET_EINT */ 1246a91eb199SMark Brown #define WM8904_MIC_DET_EINT_SHIFT 0 /* MIC_DET_EINT */ 1247a91eb199SMark Brown #define WM8904_MIC_DET_EINT_WIDTH 1 /* MIC_DET_EINT */ 1248a91eb199SMark Brown 1249a91eb199SMark Brown /* 1250a91eb199SMark Brown * R128 (0x80) - Interrupt Status Mask 1251a91eb199SMark Brown */ 1252a91eb199SMark Brown #define WM8904_IM_GPIO_BCLK_EINT 0x0200 /* IM_GPIO_BCLK_EINT */ 1253a91eb199SMark Brown #define WM8904_IM_GPIO_BCLK_EINT_MASK 0x0200 /* IM_GPIO_BCLK_EINT */ 1254a91eb199SMark Brown #define WM8904_IM_GPIO_BCLK_EINT_SHIFT 9 /* IM_GPIO_BCLK_EINT */ 1255a91eb199SMark Brown #define WM8904_IM_GPIO_BCLK_EINT_WIDTH 1 /* IM_GPIO_BCLK_EINT */ 1256a91eb199SMark Brown #define WM8904_IM_WSEQ_EINT 0x0100 /* IM_WSEQ_EINT */ 1257a91eb199SMark Brown #define WM8904_IM_WSEQ_EINT_MASK 0x0100 /* IM_WSEQ_EINT */ 1258a91eb199SMark Brown #define WM8904_IM_WSEQ_EINT_SHIFT 8 /* IM_WSEQ_EINT */ 1259a91eb199SMark Brown #define WM8904_IM_WSEQ_EINT_WIDTH 1 /* IM_WSEQ_EINT */ 1260a91eb199SMark Brown #define WM8904_IM_GPIO3_EINT 0x0080 /* IM_GPIO3_EINT */ 1261a91eb199SMark Brown #define WM8904_IM_GPIO3_EINT_MASK 0x0080 /* IM_GPIO3_EINT */ 1262a91eb199SMark Brown #define WM8904_IM_GPIO3_EINT_SHIFT 7 /* IM_GPIO3_EINT */ 1263a91eb199SMark Brown #define WM8904_IM_GPIO3_EINT_WIDTH 1 /* IM_GPIO3_EINT */ 1264a91eb199SMark Brown #define WM8904_IM_GPIO2_EINT 0x0040 /* IM_GPIO2_EINT */ 1265a91eb199SMark Brown #define WM8904_IM_GPIO2_EINT_MASK 0x0040 /* IM_GPIO2_EINT */ 1266a91eb199SMark Brown #define WM8904_IM_GPIO2_EINT_SHIFT 6 /* IM_GPIO2_EINT */ 1267a91eb199SMark Brown #define WM8904_IM_GPIO2_EINT_WIDTH 1 /* IM_GPIO2_EINT */ 1268a91eb199SMark Brown #define WM8904_IM_GPIO1_EINT 0x0020 /* IM_GPIO1_EINT */ 1269a91eb199SMark Brown #define WM8904_IM_GPIO1_EINT_MASK 0x0020 /* IM_GPIO1_EINT */ 1270a91eb199SMark Brown #define WM8904_IM_GPIO1_EINT_SHIFT 5 /* IM_GPIO1_EINT */ 1271a91eb199SMark Brown #define WM8904_IM_GPIO1_EINT_WIDTH 1 /* IM_GPIO1_EINT */ 1272a91eb199SMark Brown #define WM8904_IM_GPI8_EINT 0x0010 /* IM_GPI8_EINT */ 1273a91eb199SMark Brown #define WM8904_IM_GPI8_EINT_MASK 0x0010 /* IM_GPI8_EINT */ 1274a91eb199SMark Brown #define WM8904_IM_GPI8_EINT_SHIFT 4 /* IM_GPI8_EINT */ 1275a91eb199SMark Brown #define WM8904_IM_GPI8_EINT_WIDTH 1 /* IM_GPI8_EINT */ 1276a91eb199SMark Brown #define WM8904_IM_GPI7_EINT 0x0008 /* IM_GPI7_EINT */ 1277a91eb199SMark Brown #define WM8904_IM_GPI7_EINT_MASK 0x0008 /* IM_GPI7_EINT */ 1278a91eb199SMark Brown #define WM8904_IM_GPI7_EINT_SHIFT 3 /* IM_GPI7_EINT */ 1279a91eb199SMark Brown #define WM8904_IM_GPI7_EINT_WIDTH 1 /* IM_GPI7_EINT */ 1280a91eb199SMark Brown #define WM8904_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */ 1281a91eb199SMark Brown #define WM8904_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */ 1282a91eb199SMark Brown #define WM8904_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */ 1283a91eb199SMark Brown #define WM8904_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ 1284a91eb199SMark Brown #define WM8904_IM_MIC_SHRT_EINT 0x0002 /* IM_MIC_SHRT_EINT */ 1285a91eb199SMark Brown #define WM8904_IM_MIC_SHRT_EINT_MASK 0x0002 /* IM_MIC_SHRT_EINT */ 1286a91eb199SMark Brown #define WM8904_IM_MIC_SHRT_EINT_SHIFT 1 /* IM_MIC_SHRT_EINT */ 1287a91eb199SMark Brown #define WM8904_IM_MIC_SHRT_EINT_WIDTH 1 /* IM_MIC_SHRT_EINT */ 1288a91eb199SMark Brown #define WM8904_IM_MIC_DET_EINT 0x0001 /* IM_MIC_DET_EINT */ 1289a91eb199SMark Brown #define WM8904_IM_MIC_DET_EINT_MASK 0x0001 /* IM_MIC_DET_EINT */ 1290a91eb199SMark Brown #define WM8904_IM_MIC_DET_EINT_SHIFT 0 /* IM_MIC_DET_EINT */ 1291a91eb199SMark Brown #define WM8904_IM_MIC_DET_EINT_WIDTH 1 /* IM_MIC_DET_EINT */ 1292a91eb199SMark Brown 1293a91eb199SMark Brown /* 1294a91eb199SMark Brown * R129 (0x81) - Interrupt Polarity 1295a91eb199SMark Brown */ 1296a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_POL 0x0200 /* GPIO_BCLK_EINT_POL */ 1297a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_POL_MASK 0x0200 /* GPIO_BCLK_EINT_POL */ 1298a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_POL_SHIFT 9 /* GPIO_BCLK_EINT_POL */ 1299a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_POL_WIDTH 1 /* GPIO_BCLK_EINT_POL */ 1300a91eb199SMark Brown #define WM8904_WSEQ_EINT_POL 0x0100 /* WSEQ_EINT_POL */ 1301a91eb199SMark Brown #define WM8904_WSEQ_EINT_POL_MASK 0x0100 /* WSEQ_EINT_POL */ 1302a91eb199SMark Brown #define WM8904_WSEQ_EINT_POL_SHIFT 8 /* WSEQ_EINT_POL */ 1303a91eb199SMark Brown #define WM8904_WSEQ_EINT_POL_WIDTH 1 /* WSEQ_EINT_POL */ 1304a91eb199SMark Brown #define WM8904_GPIO3_EINT_POL 0x0080 /* GPIO3_EINT_POL */ 1305a91eb199SMark Brown #define WM8904_GPIO3_EINT_POL_MASK 0x0080 /* GPIO3_EINT_POL */ 1306a91eb199SMark Brown #define WM8904_GPIO3_EINT_POL_SHIFT 7 /* GPIO3_EINT_POL */ 1307a91eb199SMark Brown #define WM8904_GPIO3_EINT_POL_WIDTH 1 /* GPIO3_EINT_POL */ 1308a91eb199SMark Brown #define WM8904_GPIO2_EINT_POL 0x0040 /* GPIO2_EINT_POL */ 1309a91eb199SMark Brown #define WM8904_GPIO2_EINT_POL_MASK 0x0040 /* GPIO2_EINT_POL */ 1310a91eb199SMark Brown #define WM8904_GPIO2_EINT_POL_SHIFT 6 /* GPIO2_EINT_POL */ 1311a91eb199SMark Brown #define WM8904_GPIO2_EINT_POL_WIDTH 1 /* GPIO2_EINT_POL */ 1312a91eb199SMark Brown #define WM8904_GPIO1_EINT_POL 0x0020 /* GPIO1_EINT_POL */ 1313a91eb199SMark Brown #define WM8904_GPIO1_EINT_POL_MASK 0x0020 /* GPIO1_EINT_POL */ 1314a91eb199SMark Brown #define WM8904_GPIO1_EINT_POL_SHIFT 5 /* GPIO1_EINT_POL */ 1315a91eb199SMark Brown #define WM8904_GPIO1_EINT_POL_WIDTH 1 /* GPIO1_EINT_POL */ 1316a91eb199SMark Brown #define WM8904_GPI8_EINT_POL 0x0010 /* GPI8_EINT_POL */ 1317a91eb199SMark Brown #define WM8904_GPI8_EINT_POL_MASK 0x0010 /* GPI8_EINT_POL */ 1318a91eb199SMark Brown #define WM8904_GPI8_EINT_POL_SHIFT 4 /* GPI8_EINT_POL */ 1319a91eb199SMark Brown #define WM8904_GPI8_EINT_POL_WIDTH 1 /* GPI8_EINT_POL */ 1320a91eb199SMark Brown #define WM8904_GPI7_EINT_POL 0x0008 /* GPI7_EINT_POL */ 1321a91eb199SMark Brown #define WM8904_GPI7_EINT_POL_MASK 0x0008 /* GPI7_EINT_POL */ 1322a91eb199SMark Brown #define WM8904_GPI7_EINT_POL_SHIFT 3 /* GPI7_EINT_POL */ 1323a91eb199SMark Brown #define WM8904_GPI7_EINT_POL_WIDTH 1 /* GPI7_EINT_POL */ 1324a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_POL 0x0004 /* FLL_LOCK_EINT_POL */ 1325a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_POL_MASK 0x0004 /* FLL_LOCK_EINT_POL */ 1326a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_POL_SHIFT 2 /* FLL_LOCK_EINT_POL */ 1327a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_POL_WIDTH 1 /* FLL_LOCK_EINT_POL */ 1328a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_POL 0x0002 /* MIC_SHRT_EINT_POL */ 1329a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_POL_MASK 0x0002 /* MIC_SHRT_EINT_POL */ 1330a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_POL_SHIFT 1 /* MIC_SHRT_EINT_POL */ 1331a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_POL_WIDTH 1 /* MIC_SHRT_EINT_POL */ 1332a91eb199SMark Brown #define WM8904_MIC_DET_EINT_POL 0x0001 /* MIC_DET_EINT_POL */ 1333a91eb199SMark Brown #define WM8904_MIC_DET_EINT_POL_MASK 0x0001 /* MIC_DET_EINT_POL */ 1334a91eb199SMark Brown #define WM8904_MIC_DET_EINT_POL_SHIFT 0 /* MIC_DET_EINT_POL */ 1335a91eb199SMark Brown #define WM8904_MIC_DET_EINT_POL_WIDTH 1 /* MIC_DET_EINT_POL */ 1336a91eb199SMark Brown 1337a91eb199SMark Brown /* 1338a91eb199SMark Brown * R130 (0x82) - Interrupt Debounce 1339a91eb199SMark Brown */ 1340a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_DB 0x0200 /* GPIO_BCLK_EINT_DB */ 1341a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_DB_MASK 0x0200 /* GPIO_BCLK_EINT_DB */ 1342a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_DB_SHIFT 9 /* GPIO_BCLK_EINT_DB */ 1343a91eb199SMark Brown #define WM8904_GPIO_BCLK_EINT_DB_WIDTH 1 /* GPIO_BCLK_EINT_DB */ 1344a91eb199SMark Brown #define WM8904_WSEQ_EINT_DB 0x0100 /* WSEQ_EINT_DB */ 1345a91eb199SMark Brown #define WM8904_WSEQ_EINT_DB_MASK 0x0100 /* WSEQ_EINT_DB */ 1346a91eb199SMark Brown #define WM8904_WSEQ_EINT_DB_SHIFT 8 /* WSEQ_EINT_DB */ 1347a91eb199SMark Brown #define WM8904_WSEQ_EINT_DB_WIDTH 1 /* WSEQ_EINT_DB */ 1348a91eb199SMark Brown #define WM8904_GPIO3_EINT_DB 0x0080 /* GPIO3_EINT_DB */ 1349a91eb199SMark Brown #define WM8904_GPIO3_EINT_DB_MASK 0x0080 /* GPIO3_EINT_DB */ 1350a91eb199SMark Brown #define WM8904_GPIO3_EINT_DB_SHIFT 7 /* GPIO3_EINT_DB */ 1351a91eb199SMark Brown #define WM8904_GPIO3_EINT_DB_WIDTH 1 /* GPIO3_EINT_DB */ 1352a91eb199SMark Brown #define WM8904_GPIO2_EINT_DB 0x0040 /* GPIO2_EINT_DB */ 1353a91eb199SMark Brown #define WM8904_GPIO2_EINT_DB_MASK 0x0040 /* GPIO2_EINT_DB */ 1354a91eb199SMark Brown #define WM8904_GPIO2_EINT_DB_SHIFT 6 /* GPIO2_EINT_DB */ 1355a91eb199SMark Brown #define WM8904_GPIO2_EINT_DB_WIDTH 1 /* GPIO2_EINT_DB */ 1356a91eb199SMark Brown #define WM8904_GPIO1_EINT_DB 0x0020 /* GPIO1_EINT_DB */ 1357a91eb199SMark Brown #define WM8904_GPIO1_EINT_DB_MASK 0x0020 /* GPIO1_EINT_DB */ 1358a91eb199SMark Brown #define WM8904_GPIO1_EINT_DB_SHIFT 5 /* GPIO1_EINT_DB */ 1359a91eb199SMark Brown #define WM8904_GPIO1_EINT_DB_WIDTH 1 /* GPIO1_EINT_DB */ 1360a91eb199SMark Brown #define WM8904_GPI8_EINT_DB 0x0010 /* GPI8_EINT_DB */ 1361a91eb199SMark Brown #define WM8904_GPI8_EINT_DB_MASK 0x0010 /* GPI8_EINT_DB */ 1362a91eb199SMark Brown #define WM8904_GPI8_EINT_DB_SHIFT 4 /* GPI8_EINT_DB */ 1363a91eb199SMark Brown #define WM8904_GPI8_EINT_DB_WIDTH 1 /* GPI8_EINT_DB */ 1364a91eb199SMark Brown #define WM8904_GPI7_EINT_DB 0x0008 /* GPI7_EINT_DB */ 1365a91eb199SMark Brown #define WM8904_GPI7_EINT_DB_MASK 0x0008 /* GPI7_EINT_DB */ 1366a91eb199SMark Brown #define WM8904_GPI7_EINT_DB_SHIFT 3 /* GPI7_EINT_DB */ 1367a91eb199SMark Brown #define WM8904_GPI7_EINT_DB_WIDTH 1 /* GPI7_EINT_DB */ 1368a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_DB 0x0004 /* FLL_LOCK_EINT_DB */ 1369a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_DB_MASK 0x0004 /* FLL_LOCK_EINT_DB */ 1370a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_DB_SHIFT 2 /* FLL_LOCK_EINT_DB */ 1371a91eb199SMark Brown #define WM8904_FLL_LOCK_EINT_DB_WIDTH 1 /* FLL_LOCK_EINT_DB */ 1372a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_DB 0x0002 /* MIC_SHRT_EINT_DB */ 1373a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_DB_MASK 0x0002 /* MIC_SHRT_EINT_DB */ 1374a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_DB_SHIFT 1 /* MIC_SHRT_EINT_DB */ 1375a91eb199SMark Brown #define WM8904_MIC_SHRT_EINT_DB_WIDTH 1 /* MIC_SHRT_EINT_DB */ 1376a91eb199SMark Brown #define WM8904_MIC_DET_EINT_DB 0x0001 /* MIC_DET_EINT_DB */ 1377a91eb199SMark Brown #define WM8904_MIC_DET_EINT_DB_MASK 0x0001 /* MIC_DET_EINT_DB */ 1378a91eb199SMark Brown #define WM8904_MIC_DET_EINT_DB_SHIFT 0 /* MIC_DET_EINT_DB */ 1379a91eb199SMark Brown #define WM8904_MIC_DET_EINT_DB_WIDTH 1 /* MIC_DET_EINT_DB */ 1380a91eb199SMark Brown 1381a91eb199SMark Brown /* 1382a91eb199SMark Brown * R134 (0x86) - EQ1 1383a91eb199SMark Brown */ 1384a91eb199SMark Brown #define WM8904_EQ_ENA 0x0001 /* EQ_ENA */ 1385a91eb199SMark Brown #define WM8904_EQ_ENA_MASK 0x0001 /* EQ_ENA */ 1386a91eb199SMark Brown #define WM8904_EQ_ENA_SHIFT 0 /* EQ_ENA */ 1387a91eb199SMark Brown #define WM8904_EQ_ENA_WIDTH 1 /* EQ_ENA */ 1388a91eb199SMark Brown 1389a91eb199SMark Brown /* 1390a91eb199SMark Brown * R135 (0x87) - EQ2 1391a91eb199SMark Brown */ 1392a91eb199SMark Brown #define WM8904_EQ_B1_GAIN_MASK 0x001F /* EQ_B1_GAIN - [4:0] */ 1393a91eb199SMark Brown #define WM8904_EQ_B1_GAIN_SHIFT 0 /* EQ_B1_GAIN - [4:0] */ 1394a91eb199SMark Brown #define WM8904_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [4:0] */ 1395a91eb199SMark Brown 1396a91eb199SMark Brown /* 1397a91eb199SMark Brown * R136 (0x88) - EQ3 1398a91eb199SMark Brown */ 1399a91eb199SMark Brown #define WM8904_EQ_B2_GAIN_MASK 0x001F /* EQ_B2_GAIN - [4:0] */ 1400a91eb199SMark Brown #define WM8904_EQ_B2_GAIN_SHIFT 0 /* EQ_B2_GAIN - [4:0] */ 1401a91eb199SMark Brown #define WM8904_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [4:0] */ 1402a91eb199SMark Brown 1403a91eb199SMark Brown /* 1404a91eb199SMark Brown * R137 (0x89) - EQ4 1405a91eb199SMark Brown */ 1406a91eb199SMark Brown #define WM8904_EQ_B3_GAIN_MASK 0x001F /* EQ_B3_GAIN - [4:0] */ 1407a91eb199SMark Brown #define WM8904_EQ_B3_GAIN_SHIFT 0 /* EQ_B3_GAIN - [4:0] */ 1408a91eb199SMark Brown #define WM8904_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [4:0] */ 1409a91eb199SMark Brown 1410a91eb199SMark Brown /* 1411a91eb199SMark Brown * R138 (0x8A) - EQ5 1412a91eb199SMark Brown */ 1413a91eb199SMark Brown #define WM8904_EQ_B4_GAIN_MASK 0x001F /* EQ_B4_GAIN - [4:0] */ 1414a91eb199SMark Brown #define WM8904_EQ_B4_GAIN_SHIFT 0 /* EQ_B4_GAIN - [4:0] */ 1415a91eb199SMark Brown #define WM8904_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [4:0] */ 1416a91eb199SMark Brown 1417a91eb199SMark Brown /* 1418a91eb199SMark Brown * R139 (0x8B) - EQ6 1419a91eb199SMark Brown */ 1420a91eb199SMark Brown #define WM8904_EQ_B5_GAIN_MASK 0x001F /* EQ_B5_GAIN - [4:0] */ 1421a91eb199SMark Brown #define WM8904_EQ_B5_GAIN_SHIFT 0 /* EQ_B5_GAIN - [4:0] */ 1422a91eb199SMark Brown #define WM8904_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [4:0] */ 1423a91eb199SMark Brown 1424a91eb199SMark Brown /* 1425a91eb199SMark Brown * R140 (0x8C) - EQ7 1426a91eb199SMark Brown */ 1427a91eb199SMark Brown #define WM8904_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */ 1428a91eb199SMark Brown #define WM8904_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */ 1429a91eb199SMark Brown #define WM8904_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */ 1430a91eb199SMark Brown 1431a91eb199SMark Brown /* 1432a91eb199SMark Brown * R141 (0x8D) - EQ8 1433a91eb199SMark Brown */ 1434a91eb199SMark Brown #define WM8904_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */ 1435a91eb199SMark Brown #define WM8904_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */ 1436a91eb199SMark Brown #define WM8904_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */ 1437a91eb199SMark Brown 1438a91eb199SMark Brown /* 1439a91eb199SMark Brown * R142 (0x8E) - EQ9 1440a91eb199SMark Brown */ 1441a91eb199SMark Brown #define WM8904_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */ 1442a91eb199SMark Brown #define WM8904_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */ 1443a91eb199SMark Brown #define WM8904_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */ 1444a91eb199SMark Brown 1445a91eb199SMark Brown /* 1446a91eb199SMark Brown * R143 (0x8F) - EQ10 1447a91eb199SMark Brown */ 1448a91eb199SMark Brown #define WM8904_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */ 1449a91eb199SMark Brown #define WM8904_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */ 1450a91eb199SMark Brown #define WM8904_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */ 1451a91eb199SMark Brown 1452a91eb199SMark Brown /* 1453a91eb199SMark Brown * R144 (0x90) - EQ11 1454a91eb199SMark Brown */ 1455a91eb199SMark Brown #define WM8904_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */ 1456a91eb199SMark Brown #define WM8904_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */ 1457a91eb199SMark Brown #define WM8904_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */ 1458a91eb199SMark Brown 1459a91eb199SMark Brown /* 1460a91eb199SMark Brown * R145 (0x91) - EQ12 1461a91eb199SMark Brown */ 1462a91eb199SMark Brown #define WM8904_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */ 1463a91eb199SMark Brown #define WM8904_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */ 1464a91eb199SMark Brown #define WM8904_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */ 1465a91eb199SMark Brown 1466a91eb199SMark Brown /* 1467a91eb199SMark Brown * R146 (0x92) - EQ13 1468a91eb199SMark Brown */ 1469a91eb199SMark Brown #define WM8904_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */ 1470a91eb199SMark Brown #define WM8904_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */ 1471a91eb199SMark Brown #define WM8904_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */ 1472a91eb199SMark Brown 1473a91eb199SMark Brown /* 1474a91eb199SMark Brown * R147 (0x93) - EQ14 1475a91eb199SMark Brown */ 1476a91eb199SMark Brown #define WM8904_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */ 1477a91eb199SMark Brown #define WM8904_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */ 1478a91eb199SMark Brown #define WM8904_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */ 1479a91eb199SMark Brown 1480a91eb199SMark Brown /* 1481a91eb199SMark Brown * R148 (0x94) - EQ15 1482a91eb199SMark Brown */ 1483a91eb199SMark Brown #define WM8904_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */ 1484a91eb199SMark Brown #define WM8904_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */ 1485a91eb199SMark Brown #define WM8904_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */ 1486a91eb199SMark Brown 1487a91eb199SMark Brown /* 1488a91eb199SMark Brown * R149 (0x95) - EQ16 1489a91eb199SMark Brown */ 1490a91eb199SMark Brown #define WM8904_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */ 1491a91eb199SMark Brown #define WM8904_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */ 1492a91eb199SMark Brown #define WM8904_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */ 1493a91eb199SMark Brown 1494a91eb199SMark Brown /* 1495a91eb199SMark Brown * R150 (0x96) - EQ17 1496a91eb199SMark Brown */ 1497a91eb199SMark Brown #define WM8904_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */ 1498a91eb199SMark Brown #define WM8904_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */ 1499a91eb199SMark Brown #define WM8904_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */ 1500a91eb199SMark Brown 1501a91eb199SMark Brown /* 1502a91eb199SMark Brown * R151 (0x97) - EQ18 1503a91eb199SMark Brown */ 1504a91eb199SMark Brown #define WM8904_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */ 1505a91eb199SMark Brown #define WM8904_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */ 1506a91eb199SMark Brown #define WM8904_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */ 1507a91eb199SMark Brown 1508a91eb199SMark Brown /* 1509a91eb199SMark Brown * R152 (0x98) - EQ19 1510a91eb199SMark Brown */ 1511a91eb199SMark Brown #define WM8904_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */ 1512a91eb199SMark Brown #define WM8904_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */ 1513a91eb199SMark Brown #define WM8904_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */ 1514a91eb199SMark Brown 1515a91eb199SMark Brown /* 1516a91eb199SMark Brown * R153 (0x99) - EQ20 1517a91eb199SMark Brown */ 1518a91eb199SMark Brown #define WM8904_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */ 1519a91eb199SMark Brown #define WM8904_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */ 1520a91eb199SMark Brown #define WM8904_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */ 1521a91eb199SMark Brown 1522a91eb199SMark Brown /* 1523a91eb199SMark Brown * R154 (0x9A) - EQ21 1524a91eb199SMark Brown */ 1525a91eb199SMark Brown #define WM8904_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */ 1526a91eb199SMark Brown #define WM8904_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */ 1527a91eb199SMark Brown #define WM8904_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */ 1528a91eb199SMark Brown 1529a91eb199SMark Brown /* 1530a91eb199SMark Brown * R155 (0x9B) - EQ22 1531a91eb199SMark Brown */ 1532a91eb199SMark Brown #define WM8904_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */ 1533a91eb199SMark Brown #define WM8904_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */ 1534a91eb199SMark Brown #define WM8904_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */ 1535a91eb199SMark Brown 1536a91eb199SMark Brown /* 1537a91eb199SMark Brown * R156 (0x9C) - EQ23 1538a91eb199SMark Brown */ 1539a91eb199SMark Brown #define WM8904_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */ 1540a91eb199SMark Brown #define WM8904_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */ 1541a91eb199SMark Brown #define WM8904_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */ 1542a91eb199SMark Brown 1543a91eb199SMark Brown /* 1544a91eb199SMark Brown * R157 (0x9D) - EQ24 1545a91eb199SMark Brown */ 1546a91eb199SMark Brown #define WM8904_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */ 1547a91eb199SMark Brown #define WM8904_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */ 1548a91eb199SMark Brown #define WM8904_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */ 1549a91eb199SMark Brown 1550a91eb199SMark Brown /* 1551a91eb199SMark Brown * R161 (0xA1) - Control Interface Test 1 1552a91eb199SMark Brown */ 1553a91eb199SMark Brown #define WM8904_USER_KEY 0x0002 /* USER_KEY */ 1554a91eb199SMark Brown #define WM8904_USER_KEY_MASK 0x0002 /* USER_KEY */ 1555a91eb199SMark Brown #define WM8904_USER_KEY_SHIFT 1 /* USER_KEY */ 1556a91eb199SMark Brown #define WM8904_USER_KEY_WIDTH 1 /* USER_KEY */ 1557a91eb199SMark Brown 1558a91eb199SMark Brown /* 15599b85fc90SMark Brown * R198 (0xC6) - ADC Test 0 15609b85fc90SMark Brown */ 15619b85fc90SMark Brown #define WM8904_ADC_128_OSR_TST_MODE 0x0004 /* ADC_128_OSR_TST_MODE */ 15629b85fc90SMark Brown #define WM8904_ADC_128_OSR_TST_MODE_SHIFT 2 /* ADC_128_OSR_TST_MODE */ 15639b85fc90SMark Brown #define WM8904_ADC_128_OSR_TST_MODE_WIDTH 1 /* ADC_128_OSR_TST_MODE */ 15649b85fc90SMark Brown #define WM8904_ADC_BIASX1P5 0x0001 /* ADC_BIASX1P5 */ 15659b85fc90SMark Brown #define WM8904_ADC_BIASX1P5_SHIFT 0 /* ADC_BIASX1P5 */ 15669b85fc90SMark Brown #define WM8904_ADC_BIASX1P5_WIDTH 1 /* ADC_BIASX1P5 */ 15679b85fc90SMark Brown 15689b85fc90SMark Brown /* 1569a91eb199SMark Brown * R204 (0xCC) - Analogue Output Bias 0 1570a91eb199SMark Brown */ 1571a91eb199SMark Brown #define WM8904_PGA_BIAS_MASK 0x0070 /* PGA_BIAS - [6:4] */ 1572a91eb199SMark Brown #define WM8904_PGA_BIAS_SHIFT 4 /* PGA_BIAS - [6:4] */ 1573a91eb199SMark Brown #define WM8904_PGA_BIAS_WIDTH 3 /* PGA_BIAS - [6:4] */ 1574a91eb199SMark Brown 1575a91eb199SMark Brown /* 1576a91eb199SMark Brown * R247 (0xF7) - FLL NCO Test 0 1577a91eb199SMark Brown */ 1578a91eb199SMark Brown #define WM8904_FLL_FRC_NCO 0x0001 /* FLL_FRC_NCO */ 1579a91eb199SMark Brown #define WM8904_FLL_FRC_NCO_MASK 0x0001 /* FLL_FRC_NCO */ 1580a91eb199SMark Brown #define WM8904_FLL_FRC_NCO_SHIFT 0 /* FLL_FRC_NCO */ 1581a91eb199SMark Brown #define WM8904_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */ 1582a91eb199SMark Brown 1583a91eb199SMark Brown /* 1584a91eb199SMark Brown * R248 (0xF8) - FLL NCO Test 1 1585a91eb199SMark Brown */ 1586a91eb199SMark Brown #define WM8904_FLL_FRC_NCO_VAL_MASK 0x003F /* FLL_FRC_NCO_VAL - [5:0] */ 1587a91eb199SMark Brown #define WM8904_FLL_FRC_NCO_VAL_SHIFT 0 /* FLL_FRC_NCO_VAL - [5:0] */ 1588a91eb199SMark Brown #define WM8904_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [5:0] */ 1589a91eb199SMark Brown 1590a91eb199SMark Brown #endif 1591