1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 273b34eadSMark Brown /* 373b34eadSMark Brown * linux/sound/wm8903.h -- Platform data for WM8903 473b34eadSMark Brown * 573b34eadSMark Brown * Copyright 2010 Wolfson Microelectronics. PLC. 673b34eadSMark Brown */ 773b34eadSMark Brown 873b34eadSMark Brown #ifndef __LINUX_SND_WM8903_H 973b34eadSMark Brown #define __LINUX_SND_WM8903_H 1073b34eadSMark Brown 11a0f203d3SStephen Warren /* 12a0f203d3SStephen Warren * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of 13a0f203d3SStephen Warren * zero in platform data means "don't touch this pin". 14a0f203d3SStephen Warren */ 15a0f203d3SStephen Warren #define WM8903_GPIO_CONFIG_ZERO 0x8000 1673b34eadSMark Brown 1773b34eadSMark Brown /* 1837f88e84SMark Brown * R6 (0x06) - Mic Bias Control 0 1937f88e84SMark Brown */ 2028d639f7SStephen Warren #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */ 2128d639f7SStephen Warren #define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [5:4] */ 2228d639f7SStephen Warren #define WM8903_MICDET_THR_WIDTH 2 /* MICDET_THR - [5:4] */ 2337f88e84SMark Brown #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ 2437f88e84SMark Brown #define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ 2537f88e84SMark Brown #define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ 2637f88e84SMark Brown #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */ 2737f88e84SMark Brown #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ 2837f88e84SMark Brown #define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ 2937f88e84SMark Brown #define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ 3037f88e84SMark Brown #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ 3137f88e84SMark Brown #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ 3237f88e84SMark Brown #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ 3337f88e84SMark Brown #define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ 3437f88e84SMark Brown 3537f88e84SMark Brown /* 367cfe5617SStephen Warren * WM8903_GPn_FN values 377cfe5617SStephen Warren * 387cfe5617SStephen Warren * See datasheets for list of valid values per pin 397cfe5617SStephen Warren */ 407cfe5617SStephen Warren #define WM8903_GPn_FN_GPIO_OUTPUT 0 417cfe5617SStephen Warren #define WM8903_GPn_FN_BCLK 1 427cfe5617SStephen Warren #define WM8903_GPn_FN_IRQ_OUTPT 2 437cfe5617SStephen Warren #define WM8903_GPn_FN_GPIO_INPUT 3 447cfe5617SStephen Warren #define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT 4 457cfe5617SStephen Warren #define WM8903_GPn_FN_MICBIAS_SHORT_DETECT 5 467cfe5617SStephen Warren #define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT 6 477cfe5617SStephen Warren #define WM8903_GPn_FN_FLL_LOCK_OUTPUT 8 487cfe5617SStephen Warren #define WM8903_GPn_FN_FLL_CLOCK_OUTPUT 9 497cfe5617SStephen Warren 507cfe5617SStephen Warren /* 5173b34eadSMark Brown * R116 (0x74) - GPIO Control 1 5273b34eadSMark Brown */ 5373b34eadSMark Brown #define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ 5473b34eadSMark Brown #define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ 5573b34eadSMark Brown #define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ 5673b34eadSMark Brown #define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ 5773b34eadSMark Brown #define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ 5873b34eadSMark Brown #define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ 5973b34eadSMark Brown #define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ 6073b34eadSMark Brown #define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ 6173b34eadSMark Brown #define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ 6273b34eadSMark Brown #define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ 6373b34eadSMark Brown #define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 6473b34eadSMark Brown #define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ 6573b34eadSMark Brown #define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ 6673b34eadSMark Brown #define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ 6773b34eadSMark Brown #define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ 6873b34eadSMark Brown #define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ 6973b34eadSMark Brown #define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ 7073b34eadSMark Brown #define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ 7173b34eadSMark Brown #define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ 7273b34eadSMark Brown #define WM8903_GP1_PD 0x0008 /* GP1_PD */ 7373b34eadSMark Brown #define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ 7473b34eadSMark Brown #define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ 7573b34eadSMark Brown #define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ 7673b34eadSMark Brown #define WM8903_GP1_PU 0x0004 /* GP1_PU */ 7773b34eadSMark Brown #define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ 7873b34eadSMark Brown #define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ 7973b34eadSMark Brown #define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ 8073b34eadSMark Brown #define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ 8173b34eadSMark Brown #define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ 8273b34eadSMark Brown #define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ 8373b34eadSMark Brown #define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ 8473b34eadSMark Brown #define WM8903_GP1_DB 0x0001 /* GP1_DB */ 8573b34eadSMark Brown #define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ 8673b34eadSMark Brown #define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ 8773b34eadSMark Brown #define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ 8873b34eadSMark Brown 8973b34eadSMark Brown /* 9073b34eadSMark Brown * R117 (0x75) - GPIO Control 2 9173b34eadSMark Brown */ 9273b34eadSMark Brown #define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ 9373b34eadSMark Brown #define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ 9473b34eadSMark Brown #define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ 9573b34eadSMark Brown #define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ 9673b34eadSMark Brown #define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ 9773b34eadSMark Brown #define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ 9873b34eadSMark Brown #define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ 9973b34eadSMark Brown #define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ 10073b34eadSMark Brown #define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ 10173b34eadSMark Brown #define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ 10273b34eadSMark Brown #define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 10373b34eadSMark Brown #define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ 10473b34eadSMark Brown #define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ 10573b34eadSMark Brown #define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ 10673b34eadSMark Brown #define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ 10773b34eadSMark Brown #define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ 10873b34eadSMark Brown #define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ 10973b34eadSMark Brown #define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ 11073b34eadSMark Brown #define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ 11173b34eadSMark Brown #define WM8903_GP2_PD 0x0008 /* GP2_PD */ 11273b34eadSMark Brown #define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ 11373b34eadSMark Brown #define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ 11473b34eadSMark Brown #define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ 11573b34eadSMark Brown #define WM8903_GP2_PU 0x0004 /* GP2_PU */ 11673b34eadSMark Brown #define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ 11773b34eadSMark Brown #define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ 11873b34eadSMark Brown #define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ 11973b34eadSMark Brown #define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ 12073b34eadSMark Brown #define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ 12173b34eadSMark Brown #define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ 12273b34eadSMark Brown #define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ 12373b34eadSMark Brown #define WM8903_GP2_DB 0x0001 /* GP2_DB */ 12473b34eadSMark Brown #define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ 12573b34eadSMark Brown #define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ 12673b34eadSMark Brown #define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ 12773b34eadSMark Brown 12873b34eadSMark Brown /* 12973b34eadSMark Brown * R118 (0x76) - GPIO Control 3 13073b34eadSMark Brown */ 13173b34eadSMark Brown #define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ 13273b34eadSMark Brown #define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ 13373b34eadSMark Brown #define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ 13473b34eadSMark Brown #define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ 13573b34eadSMark Brown #define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ 13673b34eadSMark Brown #define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ 13773b34eadSMark Brown #define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ 13873b34eadSMark Brown #define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ 13973b34eadSMark Brown #define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ 14073b34eadSMark Brown #define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ 14173b34eadSMark Brown #define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 14273b34eadSMark Brown #define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ 14373b34eadSMark Brown #define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ 14473b34eadSMark Brown #define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ 14573b34eadSMark Brown #define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ 14673b34eadSMark Brown #define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ 14773b34eadSMark Brown #define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ 14873b34eadSMark Brown #define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ 14973b34eadSMark Brown #define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ 15073b34eadSMark Brown #define WM8903_GP3_PD 0x0008 /* GP3_PD */ 15173b34eadSMark Brown #define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ 15273b34eadSMark Brown #define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ 15373b34eadSMark Brown #define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ 15473b34eadSMark Brown #define WM8903_GP3_PU 0x0004 /* GP3_PU */ 15573b34eadSMark Brown #define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ 15673b34eadSMark Brown #define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ 15773b34eadSMark Brown #define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ 15873b34eadSMark Brown #define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ 15973b34eadSMark Brown #define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ 16073b34eadSMark Brown #define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ 16173b34eadSMark Brown #define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ 16273b34eadSMark Brown #define WM8903_GP3_DB 0x0001 /* GP3_DB */ 16373b34eadSMark Brown #define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ 16473b34eadSMark Brown #define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ 16573b34eadSMark Brown #define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ 16673b34eadSMark Brown 16773b34eadSMark Brown /* 16873b34eadSMark Brown * R119 (0x77) - GPIO Control 4 16973b34eadSMark Brown */ 17073b34eadSMark Brown #define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ 17173b34eadSMark Brown #define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ 17273b34eadSMark Brown #define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ 17373b34eadSMark Brown #define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ 17473b34eadSMark Brown #define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ 17573b34eadSMark Brown #define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ 17673b34eadSMark Brown #define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ 17773b34eadSMark Brown #define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ 17873b34eadSMark Brown #define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ 17973b34eadSMark Brown #define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ 18073b34eadSMark Brown #define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 18173b34eadSMark Brown #define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ 18273b34eadSMark Brown #define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ 18373b34eadSMark Brown #define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ 18473b34eadSMark Brown #define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ 18573b34eadSMark Brown #define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ 18673b34eadSMark Brown #define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ 18773b34eadSMark Brown #define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ 18873b34eadSMark Brown #define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ 18973b34eadSMark Brown #define WM8903_GP4_PD 0x0008 /* GP4_PD */ 19073b34eadSMark Brown #define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ 19173b34eadSMark Brown #define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ 19273b34eadSMark Brown #define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ 19373b34eadSMark Brown #define WM8903_GP4_PU 0x0004 /* GP4_PU */ 19473b34eadSMark Brown #define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ 19573b34eadSMark Brown #define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ 19673b34eadSMark Brown #define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ 19773b34eadSMark Brown #define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ 19873b34eadSMark Brown #define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ 19973b34eadSMark Brown #define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ 20073b34eadSMark Brown #define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ 20173b34eadSMark Brown #define WM8903_GP4_DB 0x0001 /* GP4_DB */ 20273b34eadSMark Brown #define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ 20373b34eadSMark Brown #define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ 20473b34eadSMark Brown #define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ 20573b34eadSMark Brown 20673b34eadSMark Brown /* 20773b34eadSMark Brown * R120 (0x78) - GPIO Control 5 20873b34eadSMark Brown */ 20973b34eadSMark Brown #define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ 21073b34eadSMark Brown #define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ 21173b34eadSMark Brown #define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ 21273b34eadSMark Brown #define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ 21373b34eadSMark Brown #define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ 21473b34eadSMark Brown #define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ 21573b34eadSMark Brown #define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ 21673b34eadSMark Brown #define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ 21773b34eadSMark Brown #define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ 21873b34eadSMark Brown #define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ 21973b34eadSMark Brown #define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 22073b34eadSMark Brown #define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ 22173b34eadSMark Brown #define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ 22273b34eadSMark Brown #define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ 22373b34eadSMark Brown #define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ 22473b34eadSMark Brown #define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ 22573b34eadSMark Brown #define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ 22673b34eadSMark Brown #define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ 22773b34eadSMark Brown #define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ 22873b34eadSMark Brown #define WM8903_GP5_PD 0x0008 /* GP5_PD */ 22973b34eadSMark Brown #define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ 23073b34eadSMark Brown #define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ 23173b34eadSMark Brown #define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ 23273b34eadSMark Brown #define WM8903_GP5_PU 0x0004 /* GP5_PU */ 23373b34eadSMark Brown #define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ 23473b34eadSMark Brown #define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ 23573b34eadSMark Brown #define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ 23673b34eadSMark Brown #define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ 23773b34eadSMark Brown #define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ 23873b34eadSMark Brown #define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ 23973b34eadSMark Brown #define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ 24073b34eadSMark Brown #define WM8903_GP5_DB 0x0001 /* GP5_DB */ 24173b34eadSMark Brown #define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ 24273b34eadSMark Brown #define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ 24373b34eadSMark Brown #define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ 24473b34eadSMark Brown 2457cfe5617SStephen Warren #define WM8903_NUM_GPIO 5 2467cfe5617SStephen Warren 24773b34eadSMark Brown struct wm8903_platform_data { 2488abd16a6SMark Brown bool irq_active_low; /* Set if IRQ active low, default high */ 2498abd16a6SMark Brown 25037f88e84SMark Brown /* Default register value for R6 (Mic bias), used to configure 25137f88e84SMark Brown * microphone detection. In conjunction with gpio_cfg this 25237f88e84SMark Brown * can be used to route the microphone status signals out onto 25337f88e84SMark Brown * the GPIOs for use with snd_soc_jack_add_gpios(). 25437f88e84SMark Brown */ 25537f88e84SMark Brown u16 micdet_cfg; 25637f88e84SMark Brown 2577245387eSMark Brown int micdet_delay; /* Delay after microphone detection (ms) */ 2587245387eSMark Brown 2597cfe5617SStephen Warren int gpio_base; 2607cfe5617SStephen Warren u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */ 26173b34eadSMark Brown }; 26273b34eadSMark Brown 26373b34eadSMark Brown #endif 264