Lines Matching +full:0 +full:x0001
45 * 31 16 0
60 * if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
68 * 0-+ 0-+
72 * 4 | (7:0) 4 | (7:0)
76 * 8 Custom csum enable = 1 8 Custom csum enable = 0
115 #define TPD_CXSUMSTART_MASK 0x00FF
116 #define TPD_CXSUMSTART_SHIFT 0
117 #define TPD_L4HDROFFSET_MASK 0x00FF
118 #define TPD_L4HDROFFSET_SHIFT 0
119 #define TPD_CXSUM_EN_MASK 0x0001
121 #define TPD_IP_XSUM_MASK 0x0001
123 #define TPD_TCP_XSUM_MASK 0x0001
125 #define TPD_UDP_XSUM_MASK 0x0001
127 #define TPD_LSO_EN_MASK 0x0001
129 #define TPD_LSO_V2_MASK 0x0001
131 #define TPD_VLTAGGED_MASK 0x0001
133 #define TPD_INS_VLTAG_MASK 0x0001
135 #define TPD_IPV4_MASK 0x0001
137 #define TPD_ETHTYPE_MASK 0x0001
139 #define TPD_CXSUMOFFSET_MASK 0x00FF
141 #define TPD_MSS_MASK 0x1FFF
143 #define TPD_EOP_MASK 0x0001
158 * 31 16 0
160 * | Word 0 |
169 * Word 0 depiction & Word 2 depiction:
171 * 0--+ 0--+
179 * 8 | (15:0) 8 | (15:0)
206 * 0--+
214 * 8 | (13:0)
246 /* rrd word 0 */
247 #define RRD_XSUM_MASK 0xFFFF
248 #define RRD_XSUM_SHIFT 0
249 #define RRD_NOR_MASK 0x000F
251 #define RRD_SI_MASK 0x0FFF
255 #define RRD_VLTAG_MASK 0xFFFF
256 #define RRD_VLTAG_SHIFT 0
257 #define RRD_PID_MASK 0x00FF
260 #define RRD_PID_NONIP 0
277 #define RRD_RSSQ_MASK 0x0007
279 #define RRD_RSSALG_MASK 0x000F
281 #define RRD_RSSALG_TCPV6 0x1
282 #define RRD_RSSALG_IPV6 0x2
283 #define RRD_RSSALG_TCPV4 0x4
284 #define RRD_RSSALG_IPV4 0x8
287 #define RRD_PKTLEN_MASK 0x3FFF
288 #define RRD_PKTLEN_SHIFT 0
289 #define RRD_ERR_L4_MASK 0x0001
291 #define RRD_ERR_IPV4_MASK 0x0001
293 #define RRD_VLTAGGED_MASK 0x0001
295 #define RRD_OLD_PID_MASK 0x0007
297 #define RRD_ERR_RES_MASK 0x0001
299 #define RRD_ERR_FCS_MASK 0x0001
301 #define RRD_ERR_FAE_MASK 0x0001
303 #define RRD_ERR_TRUNC_MASK 0x0001
305 #define RRD_ERR_RUNT_MASK 0x0001
307 #define RRD_ERR_ICMP_MASK 0x0001
309 #define RRD_BCAST_MASK 0x0001
311 #define RRD_MCAST_MASK 0x0001
313 #define RRD_ETHTYPE_MASK 0x0001
315 #define RRD_ERR_FIFOV_MASK 0x0001
317 #define RRD_ERR_LEN_MASK 0x0001
319 #define RRD_UPDATED_MASK 0x0001
326 #define ALX_FC_RX 0x01
327 #define ALX_FC_TX 0x02
328 #define ALX_FC_ANEG 0x04
331 #define ALX_SLEEP_WOL_PHY 0x00000001
332 #define ALX_SLEEP_WOL_MAGIC 0x00000002
333 #define ALX_SLEEP_CIFS 0x00000004
339 #define ALX_RSS_HASH_TYPE_IPV4 0x1
340 #define ALX_RSS_HASH_TYPE_IPV4_TCP 0x2
341 #define ALX_RSS_HASH_TYPE_IPV6 0x4
342 #define ALX_RSS_HASH_TYPE_IPV6_TCP 0x8
462 } while (0)
581 return 0; in alx_speed_to_ethadv()